8431AMI-21LF

ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8431I-21 is a general purpose clock frequency synthesizer for IA64/32 application. The VCO operates at a frequency range of 250MHz to 700MHz providing an output frequency range of 62.5MHz to 350MHz. The output frequency can be programmed using the parallel interface, M0 through M8 to the configuration logic, and the output divider control pin, DIV_SEL. Spread spectrum clocking is programmed via the control inputs SSC_CTL0 and SSC_CTL1. • Fully integrated PLL Programmable features of the ICS8431I-21 support four operational modes. The four modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes which are controlled by the SSC_CTL[1:0] pins. Unlike other synthesizers, the ICS8431I-21 can immediately change spread-spectrum operation without having to reset the device. • Programmable PLL loop divider for generating a variety of output frequencies • Differential 3.3V LVPECL output • Crystal oscillator interface • Output frequency range: 62.5MHz to 350MHz • Crystal input frequency range: 14MHz to 25MHz • VCO range: 250MHz to 700MHz • Spread Spectrum Clocking (SSC) fixed at 1/2% modulation for environments requiring ultra low EMI • PLL bypass modes supporting in-circuit testing and on-chip functional block characterization • Cycle-to-cycle jitter: 30ps (maximum) In SSC mode, the output clock is modulated in order to achieve a reduction in EMI. In one of the PLL bypass test modes, the PLL is disconnected as the source to the differential output allowing an external source to be connected to the TEST_I/O pin. This is useful for in-circuit testing and allows the differential output to be driven at a lower frequency throughout the system clock tree. In the other PLL bypass mode, the oscillator divider is used as the source to both the M and the Fout divide by 2. This is useful for characterizing the oscillator and internal dividers. • 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Replaces ICS8431I-01 • Available in both, Standard and RoHS/Lead-Free compliant packages BLOCK DIAGRAM PIN ASSIGNMENT XTAL_IN OSC XTAL_OUT ÷ 16 PLL PHASE DETECTOR ÷2 VCO ÷4 ÷M FOUT nFOUT M0 M1 M2 M3 M4 M5 M6 M7 M8 SSC_CTL0 SSC_CTL1 VEE TEST_I/O VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nP_LOAD VCC XTAL_IN XTAL_OUT nc nc VCCA VEE MR DIV_SEL VCCO FOUT nFOUT VEE ICS8431I-21 TEST_I/O M0:M8 Configuration Logic nP_LOAD 8431AMI-21 SSC Control Logic SSC_CTL0 SSC_CTL1 28-Lead SOIC 7.5mm x 18.05mm x 2.25mm package body M Package Top View DIV_SEL www.idt.com 1 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION The ICS8431I-21 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The PLL loop divider or M divider is programmed by using inputs M0 through M8. While the nP_LOAD input is held LOW, the data present at M0:M8 is transparent to the M divider. On the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is latched into the M divider and any further changes at the M0:M8 inputs will not be seen by the M divider until the next LOW transition on nP_LOAD. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fxtal x fVCO = M 16 The M value and the required values of M0:M8 for programming the VCO are shown in Table 3B, Programmable VCO Frequency Function Table. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N 16 x N For the ICS8431I-21, the output divider may be set to either ÷2 or ÷4 by the DIV_SEL pin. For an input of 16 MHz, valid M values for which the PLL will achieve lock are defined as: 250 ≤ M ≤ 511. The programmable features of the ICS8431I-21 support four output operational modes and a programmable M divider and output divider. The four output operational modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes and are controlled by the SSC_CTL[1:0] pins. 8431AMI-21 www.idt.com 2 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number 1, 2, 3, 4, 5, 6, 7 8, 9 Name Type M0-M6 Input Input 12, 15, 21 M7-M8 SSC CTL0, SSC CTL1 VEE 13 TEST I/O 10, 11 Input Description Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL pins interface levels. Pullup Pullup SCC control pins. LVTTL / LVCMOS interface levels. 14, 27 VCC Power Input / Output Power Negative supply pins. Connect all VEE pins to board ground. 16, 17 nFOUT, FOUT Output Differential outputs for the synthesizer. 3.3V LVPECL interface levels. 18 VCCO Power 19 DIV_SEL Input 20 MR Input 22 VCCA Power Output supply pin. Determines the output divide value for FOUT. Pulldown LVCMOS / LVTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output FOUT to go low and the inver ted output Pulldown nFOUT to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not effect loaded M and T values. LVCMOS / LVTTL interface levels. Analog supply pin. 23, 24 nc XTAL_OUT, XTAL_IN Unused Programmed as defined in Table 3A Function Table. Core supply pin. No connect. Crystal oscillator interface. XTAL_IN is the input. 25, 26 Input XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 28 nP_LOAD Input Pulldown is loaded into M divider. LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Pin Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 8431AMI-21 Test Conditions www.idt.com 3 Minimum Typical Maximum Units REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 3A. SSC CONTROL INPUT FUNCTION TABLE Inputs SSC_CTL1 SSC_CTL0 Outputs TEST_I/O Source SSC FOUT, nFOUT DIV_SEL0 DIV_SEL1 0 0 Internal Disabled fXTAL ÷ 32 fXTAL ÷ 64 0 1 PLL Enabled fXTAL x M 32 fXTAL x M 64 1 0 External Disabled Test Clk Test Clk fXTAL x M 32 NOTE 1: Used for in house debug and characterization. 1 1 PLL fXTAL ÷ 16 PLL bypass; oscillator, M and N ÷M dividers test mode. NOTE 1 Default SSC; Hi-Z Modulation Factor = ½ Percent PLL Bypass Mode, NOTE 1; Input (1MHz≤ Test Clk ≤ 200MHz) fXTAL x M 64 Disabled Operational Modes TEST_I/O Hi-Z No SSC Modulation TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1) 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 250 0 1 1 1 1 1 0 1 0 VCO Frequency (MHz) M Count 250 251 251 0 1 1 1 1 1 0 1 1 252 252 0 1 1 1 1 1 1 0 0 253 253 0 1 1 1 1 1 1 0 1 • • • • • • • • • • • • • • • • • • • • • • 508 508 1 1 1 1 1 1 1 0 0 509 509 1 1 1 1 1 1 1 0 1 510 510 1 1 1 1 1 1 1 1 0 511 511 1 1 1 1 1 1 1 1 1 NOTE 1: Assumes a 16MHz cr ystal. TABLE 3C. FUNCTION TABLE Inputs DIV_SEL 8431AMI-21 N Divider Value Output Frequency (MHz) Minimum Maximum 0 2 125 350 1 4 62.5 175 www.idt.com 4 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 46.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VCC VCCO Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V Output Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 VCCA Analog Supply Voltage 3.465 V IEE Power Supply Current 155 mA ICCA Analog Supply Current 16 mA Maximum Units 2 VCC + 0.3 V -0.3 0.8 V VCC = VIN = 3.465V 5 µA VCC = VIN = 3.465V 150 µA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol VIH Input VIL Input IIH Input IIL Input Parameter M0:M8, SSC_CTL0, SSC_CTL1, MR, High Voltage DIV_SEL, TEST_I/O, nP_LOAD M0:M8, SSC_CTL0, SSC_CTL1, MR, Low Voltage DIV_SEL, TEST_I/O, nP_LOAD M7, M8, SSC_CTL0, SSC_CTL1, TEST_IO High Current M0:M6, DIV_SEL nP_LOAD, MR M7, M8, SSC_CTL0, SSC_CTL1, TEST_IO Low Current M0:M6, DIV_SEL nP_LOAD, MR Test Conditions Minimum Typical VCC = 3.465V, VIN = 0V -150 µA VCC = 3.465V, VIN = 0V -5 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCCO - 1.4 VCCO - 0.9 V VCCO - 2.0 VCCO - 1.7 V 0.6 1.0 V NOTE 1: Output terminated with 50Ω to VCCO - 2V. See Parameter Measurement Section, 3.3V Output Load Test Circuit. 8431AMI-21 www.idt.com 5 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 14 16 Equivalent Series Resistance (ESR) Shunt Capacitance 3 25 MHz 40 Ω 7 pF TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter FOUT Output Frequency t j it(cc) Cycle-to-Cycle Jitter ; NOTE 1, 5 odc Output Duty Cycle tR / tF Output Rise/Fall Time Test Conditions Typical Maximum Units 350 MHz 19 30 ps 50 52 % 700 ps 62.5 FOUT ≥ 100MHz 48 20% to 80% 200 29 Fxtal Cr ystal Input Range; NOTE 2, 3 FM SSC Modulation Frequency; NOTE 4 FOUT = 200MHz FMF SSC Modulation Factor ; NOTE 4 FOUT = 200MHz SSCred Spectral Reduction; NOTE 4 FOUT = 200MHz 14 Power-up to Stable Clock Output tSTABLE See Figures in the Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Only valid within the VCO operating range. NOTE 3: For XTAL input, refer to Application Note. NOTE 4: Spread Spectrum clocking enabled. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 8431AMI-21 Minimum www.idt.com 6 16 0.4 7 25 MHz 33.33 KHz 0.6 % 10 ms 10 dB REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V V CC , VCCA, VCCO Qx nFOUT SCOPE FOUT tcycle ➤ ➤ LVPECL ➤ n tcycle n+1 ➤ nQx VEE t jit(cc) = tcycle n –tcycle n+1 1000 Cycles -1.3V ± 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT CYCLE-TO-CYCLE JITTER nFOUT 80% 80% FOUT VSW I N G Clock Outputs t PW 20% 20% tR t PERIOD tF odc = t PW x 100% t PERIOD OUTPUT RISE/FALL TIME 8431AMI-21 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.idt.com 7 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8431I-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, better power supply isolation is required. Figure 1 illustrates how a 10Ω along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. TERMINATION FOR 3.3V VCC .01μF 10Ω V CCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING LVPECL OUTPUTS The clock layout topology shown below is typical for IA64/32 platforms. The two different layouts mentioned are recommended only as guidelines. drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 8431AMI-21 125Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.idt.com 8 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER CRYSTAL INPUT INTERFACE were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS8431I-21 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p FIGURE 3. CRYSTAL INPUT INTERFACE SPREAD SPECTRUM The ICS8431I-21 triangle modulation frequency deviation will not exceed 0.6% down-spread from the nominal clock frequency (+0.0% / -0.5%). An example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 4B. The ratio of this width to the fundamental frequency is typically 0.4%, and will not exceed 0.6%. The resulting spectral reduction will be greater than 7dB, as shown in Figure 4B. It is important to note the ICS8431I-21 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction. Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 30kHz triangle waveform is used with 0.5% down-spread (+0.0% / -0.5%) from the nominal 200MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 4A below. The ramp profile can be expressed as: ➤ • Fnom = Nominal Clock Frequency in Spread OFF mode (200MHz with 16MHz IN) • Fm = Nominal Modulation Frequency (30kHz) • δ = Modulation Factor (0.5% down spread) (1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t < 1 , 2 fm (1 - δ) fnom - 2 fm x δ x fnom x t when 1 < t < 1 2 fm fm Δ − 10 dBm Fnom A B ➤ (1 - δ) Fnom δ = .4% ➤ ➤ 0.5/fm 1/fm FIGURE 4A. TRIANGLE FREQUENCY MODULATION FIGURE 4B. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN (A) SPREAD -SPECTRUM OFF (B) SPREAD -S PECTRUM ON 8431AMI-21 www.idt.com 9 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE in Figure 5B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types and the density of the P.C. board. The schematic of the ICS8431I-21 layout example used in this layout guideline is shown in Figure 5A. The ICS8431I-21 recommended PCB board layout for this example is shown Logic Input Pin Examples VCC=3.3V Set Logic Input to '1' VCC SP=Spare, not installed RU1 1K VCC C6 0.01uF C8 VCC C1 0.1uF M0 M1 M2 M3 M4 M5 M6 M7 M8 SSC_CTL0 SSC_CTL1 VEE TEST_IO VCC nP_LOAD VCC XTAL_IN XTAL_OUT NC NC VCCA VEE MR DIV_SEL VCCO FOUT nFOUT VEE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RU2 SP To Logic Input pins U1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Set Logic Input to '0' VCC 22pF To Logic Input pins RD1 SP RD2 1K X1 C7 22pF VCC R5 VCC VCCA VCC C3 0.01uF C4 10uF 10 R1 125 R3 125 Zo = 50 Ohm + Zo = 50 Ohm ICS8431I-21 ICS8431-21 - C2 0.1uF R2 84 R4 84 FIGURE 5A. SCHEMATIC EXAMPLE 8431AMI-21 www.idt.com 10 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. GROUNDING Place the decoupling capacitors C1, C2 and C6, as close as possible to the power pins. If space allows, placment of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • Make sure no other signal traces are routed between the clock trace pair. The RC filter consisting of R5, C3, and C4 should be placed as close to the VCCA pin as possible. CLOCK TRACES AND • The matching termination resistors should be located as close to the receiver input pins as possible. TERMINATION The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination scheme can also be used but is not shown in the example. Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 25 (XTAL_OUT) and 26 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. • The 50Ω output trace pair should have same length. C8 GND U1 ICS8431-21 VCC Signals C6 VIA X1 C3 C4 R5 C7 C2 Zo=50 Ohm C1 Zo=50 Ohm FIGURE 5B. PCB BOARD LAYOUT FOR ICS8431I-21 8431AMI-21 www.idt.com 11 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8431I-21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8431I-21 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.1mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 1 * 30mW = 30mW Total Power_MAX (3.465V, with all outputs switching) = 537.1mW + 30mW = 567.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.567W * 39.7°C/W = 107.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 7. THERMAL RESISTANCE θJA FOR 28-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 76.2°C/W 46.2°C/W 60.8°C/W 39.7°C/W 53.2°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8431AMI-21 www.idt.com 12 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT TERMINATION AND To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V CCO_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V )= OH_MAX [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V )= OL_MAX [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8431AMI-21 www.idt.com 13 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 28 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 76.2°C/W 46.2°C/W 60.8°C/W 39.7°C/W 53.2°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8431I-21 is: 4790 8431AMI-21 www.idt.com 14 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - M SUFFIX FOR 28 LEAD SOIC TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUM N MAXIMUM 28 A -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 17.70 18.40 E 7.40 7.60 e H 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 8431AMI-21 www.idt.com 15 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8431AMI-21 ICS8431AMI-21 28 Lead SOIC Tube -40°C to 85°C 8431AMI-21T ICS8431AMI-21 28 Lead SOIC 1000 tape & reel -40°C to 85°C 8431AMI-21LF ICS8431AMI-21LF 28 Lead "Lead-Free" SOIC Tube -40°C to 85°C 8431AMI-21LFT ICS8431AMI-21LF 28 Lead "Lead-Free" SOIC 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 8431AMI-21 www.idt.com 16 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev A 8431AMI-21 Table Page T10 17 19 Description of Change Updated datasheet's header/footer with IDT from ICS. Ordering Information Table - removed ICS prefix from Par t/Order Number column. Added lead-free marking. Added Contact Page. www.idt.com 17 Date 11/22/10 REV. A NOVEMBER 22, 2010 ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales Tech Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 netcom@idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8431AMI-21 www.idt.com 18 REV. A NOVEMBER 22, 2010