8536CGI-33LF

LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOSTO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER ICS8536I-33 GENERAL DESCRIPTION The ICS8536I-33 is a low skew, high performance IC S 1-to-6 Crystal Oscillator/LVCMOS-to-3.3V, 2.5V HiPerClockS™ LVPECL/LVCMOS fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS8536I-33 has selectable single ended clock or crystal inputs. The single-ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The output enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the ICS8536I-33 ideal for those applications demanding well defined performance and repeatability. FEATURES • Three differential LVPECL outputs, and three single ended LVCMOS outputs • Selectable LVCMOS/LVTTL CLK or crystal inputs • CLK can accept the following input levels: LVCMOS, LVTTL • Crystal frequency: 25MHz • Maximum output frequency: 266MHz • Output skew: 80ps (maximum) • Part-to-part skew: 800ps (maximum) • Propagation delay: 1.95ns (maximum) • Additive phase jitter, RMS: 0.32ps (typical), LVPECL output • Full 3.3V or 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM CLK_EN Pullup PIN ASSIGNMENT D LE CLK_EN XTAL_IN XTAL_OUT VCC CLK CLK_SEL VEE Q0 nQ0 VCCO_LVPECL 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VEE Q5 Q4 VCCO_LVCMOS Q3 VEE Q2 nQ2 nQ1 Q1 CLK Pulldown 0 LVPECL Q0 nQ0 25MHz XTAL_IN OSC XTAL_OUT CLK_SEL Pullup 1 Q1 nQ1 Q2 nQ2 ICS8536I-33 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View LVCMOS Q3 Q4 Q5 IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER 1 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 1 2, 3 4 5 6 7, 15, 20 8, 9 10 11, 12 13, 14 16, 18, 19 17 Name CLK_EN XTAL_IN, XTAL_OUT VCC CLK CLK_SEL VEE Q0, nQ0 VCCO_LVPECL Q1, nQ1 nQ2, Q2 Q3, Q4, Q5 VCCO_LVCMOS Input Input Power Input Input Power Output Power Output Output Output Power Type Pullup Description Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Q outputs are forced low, nQ0 output is forced high. LVCMOS / LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Positive supply pins. Pulldown Single-ended clock input. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects XTAL inputs. Pullup When LOW, selects CLK input. LVCMOS / LVTTL interface levels. Negative supply pin. Differential clock outputs. LVPECL interface levels. Output power supply mode for LVPECL clock outputs. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Single ended clock outputs. LVCMOS / LVTTL interface levels. Output power supply mode for LVCMOS / LVTTL clock outputs. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance Q3:Q5 Q3:Q5 VCC, VCCO_LVCMOS = 3.465V VCC, VCCO_LVCMOS = 2.625V Q3:Q5 VCC, VCCO_LVCMOS = 3.465V VCC, VCCO_LVCMOS = 2.625V Test Conditions Minimum Typical 4 8 5 51 51 15 20 Maximum Units pF pF pF kΩ kΩ Ω Ω IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 2 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs CLK_EN 0 0 1 CLK_SEL 0 1 0 Selected Source CLK XTAL_IN, XTAL_OUT CLK Q0:Q2 Disabled; LOW Disabled; LOW Enabled Outputs nQ0:nQ2 Disabled; HIGH Disabled; HIGH Enabled Q3:Q5 Disabled; LOW Disabled; LOW Enabled 1 1 XTAL_IN, XTAL_OUT Enabled Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or cr ystal oscillator edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK input as described in Table 3B. Disabled Enabled CLK CLK_EN nQ0:nQ2 Q0:Q5 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs CLK 0 1 Q0:Q2 LOW HIGH Outputs nQ0:nQ2 HIGH LOW Q3:Q5 LOW HIGH IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 3 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI (LVCMOS) Outputs, VO (LVCMOS) Inputs, VI (LVPECL) Outputs, IO (LVPECL) Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO_LVCMOS + 0.5V -0.5V to VCC + 0.5V 50mA 100mA -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 91.1°C/W (0 mps) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVPECL = VCCO_LVCMOS = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol VCC Parameter Power Supply Voltage Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 80 25 45 Units V V mA mA mA VCCO_LVPECL, Power Supply Voltage VCCO_LVCMOS IEE ICCO_LVPECL ICCO_LVCMOS Power Supply Current Power Supply Current Power Supply Current TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVPECL = VCCO_LVCMOS = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol VCC Parameter Power Supply Voltage Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 80 30 45 Units V V mA mA mA VCCO_LVPECL, Power Supply Voltage VCCO_LVCMOS IEE ICCO_LVPECL ICCO_LVCMOS Power Supply Current Power Supply Current Power Supply Current IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 4 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C Symbol VIH VIL VHYS IIH Parameter Input High Voltage Input Low Voltage Input Hysteresis Input High Current Input Low Current CLK_EN, CLK_SEL CLK CLK_EN, CLK_SEL CLK CLK_EN, CLK_SEL Test Conditions VCC = 3.3V VCC = 2.5V VCC = 3.3V VCC = 2.5V Minimum Typical 2 1.7 -0.3 -0.3 100 VCC = VIN = 3.465V or 2.625V VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V VCC = 3.465V or 2.625V, VIN = 0V VCCO_LVCMOS = 3.465V VCCO_LVCMOS = 2.625V -5 -150 2.6 1.8 150 5 Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 Units V V V V mV µA µA µA µA V V IIL VOH Output High Voltage; NOTE 1 V OL Output Low Voltage; NOTE 1 VCCO_LVCMOS = 3.465 or 2.625V 0.5 V NOTE 1: Outputs terminated with 50Ω to VCCO_LVCMOS/2. See Parameter Measurement Information Section. "LVCMOS Output Load Test circuit" diagrams. TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO_LVPECL = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO_LVPECL - 1.4 VCCO_LVPECL - 2.0 0.6 Typical Maximum VCCO_LVPECL - 0.9 VCCO_LVPECL - 1.7 1. 0 Units V V V NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V. TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCO_LVPECL = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO_LVPECL - 1.4 VCCO_LVPECL - 2.0 0.4 Typical Maximum VCCO_LVPECL - 0.9 VCCO_LVPECL - 1.5 1.0 Units V V V NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 12 Test Conditions Minimum Typical Maximum Fundamental 40 50 7 1 MHz Ω pF mW Units IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 5 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER TABLE 6A. LVPECL AC CHARACTERISTICS, VCC = VCCO_LVPECL = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Bank Skew; NOTE 2, 5 Output Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 4, 5 Output Rise/Fall Time 20% to 80% 25 0 155.52MHz, (Integration Range: 12kHz - 20MHz) 1.2 0.35 55 80 800 600 Test Conditions Minimum Typical Maximum 266 1.95 Units MHz ns ps ps ps ps ps t jit t sk(b) t sk(o) t sk(pp) tR / tF o dc Output Duty Cycle 46 54 % All parameters measured at ƒ ≤ 266MHz unless noted otherwise. NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point. NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the LVPECL output differential cross points. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the LVPECL output differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. TABLE 6B. LVPECL AC CHARACTERISTICS, VCC = VCCO_LVPECL = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Bank Skew; NOTE 2, 5 Output Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 4, 5 Output Rise/Fall Time 20% to 80% 25 0 155.52MHz, (Integration Range: 12kHz - 20MHz) 1.3 0.32 65 80 425 800 Test Conditions Minimum Typical Maximum 266 2 Units MHz ns ps ps ps ps ps t jit t sk(b) t sk(o) t sk(pp) tR / tF o dc Output Duty Cycle 46 54 % All parameters measured at ƒ ≤ 266MHz unless noted otherwise. NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point. NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the LVPECL output differential cross points. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the LVPECL output differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 6 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER TABLE 6C. LVCMOS AC CHARACTERISTICS, VCC = VCCO_LVCMOS = 3.3V±5%, TA = -40°C TO 85°C Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Bank Skew; NOTE 2, 5 Output Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 4, 5 Output Rise/Fall Time 20% to 80% 0.730 0.3 155.52MHz, (Integration Range: 12kHz - 20MHz) 2.4 0.35 65 80 800 1.15 Test Conditions Minimum Typical Maximum 266 3.5 Units MHz ns ps ps ps ps ns t jit t sk(b) t sk(o) t sk(pp) tR / tF o dc Output Duty Cycle 46 54 % All parameters measured at ƒ ≤ 266MHz unless noted otherwise. NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO_LVCMOS/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VCCO_LVCMOS/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. TABLE 6D. LVCMOS AC CHARACTERISTICS, VCC = VCCO_LVCMOS = 2.5V±5%, TA = -40°C TO 85°C Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Bank Skew; NOTE 2, 5 Output Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 4, 5 Output Rise/Fall Time 20% to 80% 0.425 155.52MHz, (Integration Range: 12kHz - 20MHz) 2.5 0.32 75 80 800 1.85 Test Conditions Minimum Typical Maximum 266 3.75 Units MHz ns ps ps ps ps ns t jit t sk(b) t sk(o) t sk(pp) tR / tF o dc Output Duty Cycle 46 54 % All parameters measured at ƒ ≤ 266MHz unless noted otherwise. NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO_LVCMOS/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VCCO_LVCMOS/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 7 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V 2V VCC, VCCO_LVPECL Qx SCOPE VCC, VCCO_LVPECL Qx SCOPE LVPECL nQx VEE LVPECL nQx VEE -1.3V ± 0.165V -0.5V ± 0.125V 3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT 1.65V±5% 2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT 1.25V±5% SCOPE VCC, VCCO_LVCMOS Qx SCOPE VCC, VCCO_LVCMOS Qx LVCMOS GND LVCMOS GND -1.65V±5% -1.25V±5% 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT 2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT VCC CLK nQ0:nQ2 2 CLK VCC 2 VCCO_LVCMOS Q0:Q2 tPD Q3:Q5 t PD 2 LVPECL PROPAGATION DELAY LVCMOS PROPAGATION DELAY IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 8 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER nQx V CCO_LVCMOS Qx nQy Qy t sk(o) Qx 2 V CCO_LVCMOS Qy 2 t sk(o) LVPECL OUTPUT SKEW LVCMOS OUTPUT SKEW nQ0:nQ2 Q0:Q2 Q3:Q5 V CCO_LVCMOS 2 t PW t PERIOD t PW t PERIOD odc = t PW t PERIOD x 100% odc = t PW t PERIOD x 100% LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD nQ0:nQ2 80% 80% VSW I N G Q0:Q2 20% tR tF 20% LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% 20% Q3:Q5 80% 20% tR tF LVPECL OUTPUT RISE/FALL TIME LVCMOS OUTPUT RISE/FALL TIME nQx Qx VCCO_LVCMOS/2 Qy t sk(b) BANK SKEW IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 9 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. CLK INPUT For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. OUTPUTS: LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CRYSTAL INPUT INTERFACE The ICS8536I-33 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. These same capacitor values will tune any 18pF parallel resonant crystal over the frequency range and other parameters specified in this data sheet. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p FIGURE 2. CRYSTAL INPUt INTERFACE IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 10 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD R1 Ro Rs Zo = 50 .1uf XTAL_IN Zo = Ro + Rs R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω t ransmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Zo = 50Ω 125Ω 3.3V 125Ω FOUT Zo = 50Ω 50Ω 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o 50Ω FIN Zo = 50Ω FOUT FIN Zo = 50Ω 84Ω 84Ω VCC - 2V RTT RTT = FIGURE 4A. LVPECL OUTPUT TERMINATION FIGURE 4B. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 11 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER TERMINATION FOR 2.5V LVPECL OUTPUTS Figure 5A a nd F igure 5B s how examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC – 2V. For VCCO = 2.5V, the VCCO_LVCMOS – 2V is 2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250 very close to _LVCMOSground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 R3 18 FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 12 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8536I-33. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8536I-33 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Core and LVPECL Output Power Dissipation • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 3 * 30mW = 90mW LVCMOS Output Power Dissipation • • • Output Impedance ROUT Power Dissipation due to Loading 50Ω to VCCO_LVCMOS/2 Output Current IOUT = VCCO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 15Ω] = 26.7mA Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15Ω * (26.7mA)2 = 10.7mW per output Total Power Dissipation on the ROUT Total Power (ROUT) = 10.7mW * 3 = 32.1mW Total Power Dissipation • Total Power = Power (LVPECL) + Total Power (ROUT) = 277.2mW + 90mW + 32.1mW = 399.3mW IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 13 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 91.1°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.3993W * 91.1°C/W = 121.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θ JA FOR 20-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 91.1°C/W 200 86.7°C/W 500 84.6°C/W IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 14 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50Ω VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO – 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V • For logic low, V OUT =V OL_MAX =V CCO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V – (V – 2V))/R ] * (V –V ) = [(2V – (V –V –V )= OH_MAX CCO_MAX L CCO_MAX OH_MAX CC_MAX OH_MAX L CC_MAX OH_MAX [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX – 2V))/R ] * (V L CCO_MAX –V OL_MAX ) = [(2V – (V CCO_MAX –V OL_MAX ))/R ] * (V L CCO_MAX –V OL_MAX )= [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 15 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 91.1°C/W 1 86.7°C/W 2.5 84.6°C/W TRANSISTOR COUNT The transistor count for ICS8536I-33 is: 550 PACKAGE OUTLINE & PACKAGE DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS SYMBOL MIN N A A1 A2 b c D E E1 e L α aaa 0.45 0° -4.30 0.65 BASIC 0.75 8° 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 16 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER TABLE 10. ORDERING INFORMATION Part/Order Number 8536CGI-33 8536CGI-33T 8536CGI-33LF 8536CGI-33LFT Marking ICS8536CGI33 ICS8536CGI33 ICS8536CI33L ICS8536CI33L Package 20 lead TSSOP 20 lead TSSOP 20 lead "Lead-Free" TSSOP 20 lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 17 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER REVISION HISTORY SHEET Rev B Table T1 Page 1 2 Description of Change Pin Assignment - corrected pins 13 & 14. Pin Description Table - corrected pin 13 & 14. Date 6/25/08 IDT ™ / ICS™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER 18 ICS8536CGI-33 REV. B OCTOBER 27, 2008 ICS8536I-33 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA