FemtoClock®
Crystal/LVCMOS-to-LVPECL/ LVCMOS
Frequency Synthesizer
843001I-23
DATA SHEET
General Description
Features
The 843001I-23 is a highly versatile, low phase noise
LVPECL/LVCMOS Synthesizer which can generate low jitter
reference clocks for a variety of communication applications. The
dual crystal interface allows the synthesizer to support up to three
communication standards in a given application (i.e. SONET with a
19.44MHz crystal, 1Gb/10Gb Ethernet and Fibre Channel using a
25MHz crystal). The RMS phase jitter performance is typically less
than 1ps, thus making the device acceptable for use in demanding
applications such as OC48 SONET, GbE/10Gb Ethernet and SAN
applications. The 843001I-23 is packaged in a small 24-pin TSSOP,
E-Pad package.
•
One 3.3Vdifferential LVPECL output pair and
one LVCMOS/LVTTL single-ended reference clock output
•
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
•
•
Crystal and CLK range: 19.44MHz – 27MHz
•
•
VCO range: 1.12GHz – 1.275GHz
•
RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.9ps (typical), 3.3V
•
Supply modes
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
•
•
-40°C to 85°C ambient operating temperature
Able to generate GbE/10GbE/12GbE, Fibre Channel
(1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal
Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
Available in lead-free (RoHS 6) package
Pin Assignment
Block Diagram
3
VCCO_LVCMOS
N0
N1
N2
N2:N0
SEL0 Pulldown
SEL1 Pulldown
N
XTAL_IN0
OSC
00
11
XTAL_OUT0
XTAL_IN1
01
OSC
Phase
Detector
VCO
XTAL_OUT1
10
11
CLK Pulldown
000
001
010
011
100
111
10
01
00
000
001
010
011
100
÷2
÷4
÷5
÷6
÷8 (default)
101
110
111
÷10
÷12
÷16
Q
VCCO_LVPECL
Q
nQ
VEE
VCCA
VCC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
REF_OUT
VEE
OE_REF
M2
M1
M0
MR
SEL1
SEL0
CLK
XTAL_IN0
XTAL_OUT0
nQ
843001I-23
24-Lead TSSOP, E-Pad
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
M
÷44
÷45
÷48
÷50
÷51
÷64 (default)
MR Pulldown
M2:M0 Pullup
3
REF_OUT
OE_REF Pulldown
843001I-23 Rev A 11/17/15
1
©2015 Integrated Device Technology, Inc.
843001I-23 DATA SHEET
Table 1. Pin Descriptions
Number
Name
1
VCCO_LVCMOS
Power
Type
2, 3
N0, N1
Input
Pulldown
4
N2
Input
Pullup
Description
Output supply pin for REF_CLK output.
Output divider select pins. LVCMOS/LVTTL interface levels. See Table 3C.
5
VCCO_LVPECL
Power
Output supply pin for LVPECL output.
6, 7
Q, nQ
Output
Differential output pair. LVPECL interface levels.
8, 23
VEE
Power
Negative supply pins.
9
VCCA
Power
Analog supply pin.
10
VCC
Power
Core supply pin.
11,
12
XTAL_OUT1,
XTAL_IN1
Input
Parallel resonant crystal interface.
XTAL_OUT1 is the output, XTAL_IN1 is the input.
13,
14
XTAL_OUT0,
XTAL_IN0
Input
Parallel resonant crystal interface.
XTAL_OUT0 is the output, XTAL_IN0 is the input.
15
CLK
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
16, 17
SEL0, SEL1
Input
Pulldown
Input MUX select pins. LVCMOS/LVTTL interface levels. See Table 3D.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true output Q to go low and the inverted output nQ to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
18
MR
Input
Pulldown
19, 20, 21
M0, M1, M2
Input
Pullup
22
OE_REF
Input
Pulldown
24
REF_OUT
Output
Feedback divider select pins. LVCMOS/LVTTL interface levels. See Table 3B.
Reference clock output enable. Default LOW. See Table 3E.
LVCMOS/LVTTL interface levels.
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
Output Impedance
VCCO = 3.3V
21
ROUT
VCCO = 2.5V
25
Rev A 11/17/15
Test Conditions
REF_OUT
2
Minimum
Typical
Maximum
Units
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
843001I-23 DATA SHEET
Function Tables
Table 3A. Common Configuration Table
Input Frequency
(MHz)
M Feedback Divider
Value
VCO
Frequency
(MHz)
N Output Divider
Value
Output Frequency (MHz)
Application
27
44
1188
16
74.25
HDTV
24.75
48
1188
16
74.25
HDTV
19.44
64
1244.16
8
155.52
SONET
19.44
64
1244.16
2
622.08
SONET
19.44
64
1244.16
4
311.04
SONET
25
50
1250
10
125
GigE
25
50
1250
8
156.25
10 GigE
25
50
1250
5
250
GigE
25
50
1250
4
312.5
XGMII
25
50
1250
2
625
10 GigE
25
45
1125
6
187.5
12 GigE
25
48
1200
12
100
PCI Express
25
48
1200
8
150
SATA
25
48
1200
16
75
SATA
25
51
1275
12
106.25
Fibre Channel
25
51
1275
8
159.375
10 Gig Fibre Channel
25
51
1275
6
212.5
4 Gig Fibre Channel
Table 3B. Programmable M Feedback Divider Function Table
Inputs
Input Frequency (MHz)
M2
M1
M0
M Feedback Divider
Value
0
0
0
44
25.5
27
0
0
1
45
24.9
27
0
1
0
48
23.3
26.56
0
1
1
50
22.4
25.5
1
0
0
51
22.0
25
1
0
1
64 (default)
19.44
19.92
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
Minimum
Maximum
3
Rev A 11/17/15
843001I-23 DATA SHEET
Table 3C. Programmable N Output Divider Function Table
Inputs
N2
N1
N0
N Divider Value
0
0
0
2
0
0
1
4
0
1
0
5
0
1
1
6
1
0
0
8 (default)
1
0
1
10
1
1
0
12
1
1
1
16
Table 3D. Select Mode Function Table
Inputs
SEL1
SEL0
Reference Input
PLL Mode
0
0
XTAL0
Active (default)
0
1
XTAL1
Active
1
0
CLK
Active
1
1
CLK
Bypass
Table 3E. OE_REF Output Function Table
Input
Output
OE_REF
REF_OUT
0
High-Impedance (default)
1
Active
Rev A 11/17/15
4
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
843001I-23 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
XTAL_IN
Other Input
0V to VCC
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, VO (LVCMOS)
-0.5V to VCCO_LVCMOS + 0.5V
Package Thermal Impedance, JA
32.1C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 3.3V ± 5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Analog Supply Voltage
Test Conditions
VCCO_LVPECL,
Output Supply Voltage
VCCO_LVCMOS
IEE
Power Supply Current
ICCA
Analog Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCC – 0.11
3.3
VCC
V
3.135
3.3
3.465
V
140
mA
11
mA
Outputs Unterminated
Table 4B. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Analog Supply Voltage
Test Conditions
VCCO_LVPECL,
Output Supply Voltage
VCCO_LVCMOS
IEE
Power Supply Current
ICCA
Analog Supply Current
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
Outputs Unterminated
5
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCC – 0.11
3.3
VCC
V
2.375
2.5
2.625
V
139
mA
11
mA
Rev A 11/17/15
843001I-23 DATA SHEET
Table 4C. Power Supply DC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
2.375
2.5
2.625
V
VCCA
Analog Supply Voltage
VCC – 0.10
2.5
VCC
V
VCCO_PECL,
VCCO_CMOS
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
133
mA
ICCA
Analog Supply Current
10
mA
Maximum
Units
Outputs Unterminated
Table 4D. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
VOH
VOL
Test Conditions
Minimum
Typical
VCC = 3.3V
2
VCC + 0.3
V
VCC = 2.5V
1.7
VCC + 0.3
V
VCC = 3.3V
-0.3
0.8
V
VCC = 2.5V
-0.3
0.7
V
CLK, OE_REF, MR,
N0, N1 SEL0, SEL1
VCC = VIN = 3.465V or
2.625V
150
µA
N2, M[2:0]
VCC = VIN = 3.465V or
2.625V
5
µA
Input High Current
CLK, OE_REF, MR,
N0, N1 SEL0, SEL1
VCC = 3.465V or 2.625V,
VIN = 0V
-5
µA
N2, M[2:0]
VCC = 3.465V or 2.625V,
VIN = 0V
-150
µA
VCCO_LVCMOS = 3.465V,
IOH = -12mA
2.6
V
VCCO_LVCMOS = 2.625V,
IOH = -12mA
1.8
V
Input Low Current
Output High Voltage
Output Low Voltage
REF_OUT
REF_OUT
VCCO_LVCMOS = 3.465V or
2.625V, IOL = 12mA
0.5
V
.
Table 4E. LVPECL DC Characteristics, VCC = VCCO_LVPECL = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCCO_LVPECL – 1.4
VCCO_LVPECL – 0.9
V
VCCO_LVPECL – 2.0
VCCO_LVPECL – 1.7
V
0.6
1.0
V
NOTE 1: Outputs terminated with 50 to VCCO_LVPECL – 2V.
Rev A 11/17/15
6
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
843001I-23 DATA SHEET
Table 4F. LVPECL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VCCO_LVPECL = 2.5V ± 5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Minimum
Typical
Maximum
Units
VCCO_LVPECL – 1.4
VCCO_LVPECL – 0.9
V
VCCO_LVPECL – 2.0
VCCO_LVPECL – 1.5
V
0.4
1.0
V
NOTE 1: Outputs terminated with 50 to VCCO_LVPECL – 2V.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Maximum
Units
27
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
Mode of Oscillation
Typical
Fundamental
Frequency
19.44
NOTE: Characterized using an 18pF parallel resonant crystal.
AC Electrical Characteristics
Table 6A. AC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Maximum
Units
70
637.5
MHz
REF_OUT
19.44
27
MHz
CLK to
REF_OUT
2.2
2.7
ns
Q, nQ
fOUT
Output Frequency
tPD
Propagation Delay;
NOTE 1
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 2
fVCO
PLL VCO Lock Range
tR / tF
Output
Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Minimum
622.08MHz,
(12kHz – 20MHz)
Typical
0.97
ps
1.12
1.275
GHz
Q, nQ
20% to 80%
200
700
ps
REF_OUT,
NOTE 3
20% to 80%
250
650
ps
46
54
%
48
52
%
60
ms
Q, nQ
REF_OUT;
NOTE 3
Using Clock Input
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%.
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
7
Rev A 11/17/15
843001I-23 DATA SHEET
Table 6B. AC Characteristics, VCC = 3.3V ± 5%, VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
fOUT
Output Frequency
tPD
Propagation Delay;
NOTE 1
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 2
fVCO
PLL VCO Lock Range
tR / tF
Output
Rise/Fall Time
Q, nQ
Output Duty Cycle
tLOCK
PLL Lock Time
Typical
Maximum
Units
70
637.5
MHz
REF_OUT
19.44
27
MHz
CLK to
REF_OUT
2.3
2.9
ns
622.08MHz,
(12kHz – 20MHz)
1
ps
1.12
1.275
GHz
Q, nQ
20% to 80%
200
700
ps
REF_OUT
20% to 80%
350
750
ps
46
54
%
48
52
%
60
ms
Q, nQ
odc
Minimum
REF_OUT;
NOTE 3
Using Clock Input
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%.
Table 6C. AC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
fOUT
Output Frequency
Maximum
Units
70
637.5
MHz
tPD
Propagation Delay;
NOTE 1
REF_OUT
19.44
27
MHz
CLK to
REF_OUT
2.3
2.9
ns
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 2
fVCO
PLL VCO Lock Range
tR / tF
Output
Rise/Fall Time
Q, nQ
622.08MHz,
(12kHz – 20MHz)
Output Duty Cycle
tLOCK
PLL Lock Time
Typical
1.1
ps
1.12
1.275
GHz
Q, nQ
20% to 80%
200
700
ps
REF_OUT
20% to 80%
350
750
ps
46
54
%
48
52
%
60
ms
Q, nQ
odc
Minimum
REF_OUT;
NOTE 3
Using Clock Input
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%.
Rev A 11/17/15
8
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
843001I-23 DATA SHEET
Typical Phase Noise at 622.08MHz
.
Noise Power
dBc
Hz
622.08MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.97ps (typical)
Offset Frequency (Hz)
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
9
Rev A 11/17/15
843001I-23 DATA SHEET
Parameter Measurement Information
2V
1.65V±5%
2V
1.65V±5%
SCOPE
VCC,
VCCO_LVCMOS
VCC,
VCCA
VCCO_LVPECL
VCCA
Qx
VEE
-1.65V±5%
-1.3V± 0.165V
3.3V LVCMOS Output Load AC Test Circuit
3.3V LVPECL Output Load AC Test Circuit
2V
1.25V±5%
1.25V±5%
2V
SCOPE
VCC,
VCCO_LVCMOS
VCCA
VCC,
VCCO_LVPECL
VCCA
Qx
VEE
-1.25V±5%
-0.5V±0.125V
2.5V LVCMOS Output Load AC Test Circuit
2.5V LVPECL Output Load AC Test Circuit
2.8V±0.04V
2.05V±5%
2V
1.25V±5%
2.8V±0.04V
2.05V±5%
VCC
Qx
SCOPE
VCCO_LVPECL
VCCA
VCCA
nQx
Qx
VEE
VEE
-1.25V±5%
-0.5V±0.125V
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
3.3 Core/2.5V LVPECL Output Load AC Test Circuit
Rev A 11/17/15
SCOPE
VCC
VCCO_LVPECL
10
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
843001I-23 DATA SHEET
Parameter Measurement Information, continued
V
CCO_CMOS
2
REF_OUT
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
RMS Phase Jitter
LVCMOS Output Duty Cycle/Pulse Width/Period
nQ
Q
80%
80%
tR
tF
20%
20%
REF_OUT
LVPECL Output Duty Cycle/Pulse Width/Period
LVCMOS Output Rise/Fall Time
nQ
Q
LVPECL Output Rise/Fall Time
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
11
Rev A 11/17/15
843001I-23 DATA SHEET
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVPECL Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
The unused LVPECL output pair can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Output
CLK Input
All unused LVCMOS output can be left floating. We recommend that
there is no trace attached.
For applications not requiring the use of the clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Rev A 11/17/15
12
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
843001I-23 DATA SHEET
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 1A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be accomplished
by removing R1 and making R2 50. By overdriving the crystal
oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
3.3V
3.3V
R1
100
Ro ~ 7 Ohm
C1
Zo = 50 Ohm
XTAL_IN
RS
43
R2
100
Driv er_LVCMOS
0.1uF
XTAL_OUT
Cry stal Input Interf ace
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
R1
50
Zo = 50 Ohm
0.1uF
XTAL_OUT
LVPECL
Cry stal Input Interf ace
R2
50
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
13
Rev A 11/17/15
843001I-23 DATA SHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 2A. 3.3V LVPECL Output Termination
Rev A 11/17/15
R2
84
Figure 2B. 3.3V LVPECL Output Termination
14
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
843001I-23 DATA SHEET
Termination for 2.5V LVPECL Outputs
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in Figure 3C.
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50 to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to
2.5V
VCCO = 2.5V
2.5V
2.5V
VCCO = 2.5V
R1
250
R3
250
50
+
50
+
50
–
50
2.5V LVPECL Driver
–
R1
50
2.5V LVPECL Driver
R2
62.5
R2
50
R4
62.5
R3
18
Figure 3A. 2.5V LVPECL Driver Termination Example
Figure 3B. 2.5V LVPECL Driver Termination Example
2.5V
VCCO = 2.5V
50
+
50
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 3C. 2.5V LVPECL Driver Termination Example
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
15
Rev A 11/17/15
843001I-23 DATA SHEET
Schematic Layout
Figure 6 (next page) shows an example of 843001I-23 application
schematic. In this example, the device is operated VCC =
VCCO_LVCMOS = VCCO_LVPECL = 3.3V. The 18pF parallel resonant
17.5-29.54MHz crystal is used. The load capacitance C1 = 22pF and
C2 = 22pF are recommended for frequency accuracy. Depending on
the parasitic of the printed circuit board layout, these values might
require a slight adjustment to optimize the frequency accuracy.
Crystals with other load capacitance specifications can be used. This
will require adjusting C1 and C2. For this device, the crystal load
capacitors are required for proper operation.
0.1uF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the
PCB.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequency. This
low-pass filter starts to attenuate noise at approximately 10kHz. If a
specific frequency noise component with high amplitude interference
is known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally general design practice for
power plane voltage stability suggests adding bulk capacitances in
the general area of all devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 843001I-23 provides separate
power supplies to isolate any high switching noise from coupling into
the internal PLL.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
Rev A 11/17/15
16
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
843001I-23 DATA SHEET
R1
33
Z o = 50 Ohm
R E F_O U T
3. 3V
LV C MOS
U1
R2
133
V CCO
Zo = 50 Ohm
R3
133
Q
VC C O
V CC
R4
10
1
2
3
4
5
6
7
8
9
10
11
12
N0
N1
N2
V CCA
C4
10u
Q
nQ
C6
0. 1u
VC C
XTA L_O U T1
XTAL_I N 1
24
23
22
21
20
19
18
17
16
15
14
13
V C C O_LV C MOS R E F_OU T
N0
VE E
N1
O E_R E F
N2
M2
V C C O_LV PE C L
M1
Q
M0
nQ
MR
V EE
S EL1
V CCA
S EL0
V CC
C LK
XTA L_OU T1
XTA L_I N 0
XTA L_IN 1
XTAL_OU T0
TL2
OE _R E F
M2
M1
M0
MR
SE L1
SE L0
C LK
XTAL_I N 0
XTA L_O U T0
+
Zo = 50 Ohm
/Q
-
TL3
R5
82. 5
VCC=3.3V
R6
82. 5
VCCO_LVCMOS=3.3V
VCCO_LVPECL=3.3V
F
p
8
1
X1
C2
22pF
17. 5MH z - 29.54MH z
X2
F
p
8
1
C3
22pF
Zo = 50 O hm
17. 5MH z - 29. 54MH z
Q
C5
22pF
+
C1
22pF
Zo = 50 O hm
/Q
-
V DD
Logic Control Input Examples
Set Logic
Input to
'1'
VC C
R U1
1K
Q1
Ro ~ 7 Ohm
Set Logic
Input to
'0'
VC C
R D1
N ot I ns t all
To Logic
Input
pins
R9
Z o = 50 Ohm
43
RU2
N ot I ns t all
To Logic
Input
pins
R7
50
Optional
LVPECL
Y-Termination
R8
50
R 10
50
D riv er_LVC MO S
3. 3V
RD2
1K
m urAt a, BLM18B B221S N 1
1
F B1
2
(U1:10)
C8
C9
C7
0. 1uF
10uF
V CC
0. 1uF
3. 3V
m urAt a, BLM18B B221S N 1
1
F B2
C 10
0. 1uF
2
(U1:1)
(U1:5)
C 11
C 12
C 13
10uF
0. 1uF
V CCO
0. 1uF
Figure 6. 843001I-23 Layout Example
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
17
Rev A 11/17/15
843001I-23 DATA SHEET
EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 7. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
PIN
PIN PAD
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
SOLDER
PIN PAD
Figure 7. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
Rev A 11/17/15
18
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
843001I-23 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 843001I-23.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 843001I-23 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
LVCMOS Output Power Dissipation
•
Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2
Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 21)] = 24.4mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 21 * (24.4mA)2 = 12.5mW per output
Total Power Dissipation
•
Total Power
= Power (core) + Power (LVPECL output) + Power (ROUT)
= 485.1mW + 30mW + 12.5mW = 527.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 32.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.528W * 32.1°C/W = 102°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resitance JA for 24 Lead TSSOP, E-Pad Forced Convection
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
32.1°C/W
25.5°C/W
24.0°C/W
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
19
Rev A 11/17/15
843001I-23 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCOO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/R ] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
L
L
Pd_L = [(VOL_MAX (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/R ] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
–
L
L
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
Rev A 11/17/15
20
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
843001I-23 DATA SHEET
Reliability Information
Table 8. JA vs. Air Flow Table for a 24 Lead TSSOP, E-pad
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
32.1°C/W
25.5°C/W
24.0°C/W
Transistor Count
The transistor count for 843001I-23 is: 4165
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
21
Rev A 11/17/15
843001I-23 DATA SHEET
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP, E-Pad
Table 9. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
24
A
1.10
A1
0.05
0.15
A2
0.85
0.95
b
0.19
0.30
b1
0.19
0.25
c
0.09
0.20
c1
0.09
0.16
D
7.70
7.90
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.50
0.70
P
5.0
5.5
P1
3.0
3.2
0°
8°
aaa
0.076
bbb
0.10
Reference Document: JEDEC Publication 95, MO-153
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
22
Rev A 11/17/15
843001I-23 DATA SHEET
Ordering Information
Table 10. Ordering Information
Part/Order Number
843001CGI-23LF
843001CGI-23LFT
Marking
ICS43001CI23L
ICS43001CI23L
Package
“Lead-Free” 24 Lead TSSOP, E-Pad
“Lead-Free” 24 Lead TSSOP, E-Pad
Shipping Packaging
Tube
Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Rev A 11/17/15
23
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
843001I-23 DATA SHEET
Revision History Sheet
Rev
A
Table
Page
T10
23
Description of Change
Date
Ordering Information - removed leaded devices.
Updated data sheet format.
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS
FREQUENCY SYNTHESIZER
24
11/17/15
Rev A 11/17/15
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as
those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved.
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.
工商网监
湘ICP备2023018690号
