FemtoClock™ Crystal/LVCMOS-to-3.3V,
2.5V LVPECL Frequency Synthesizer
843001I-22
DATA SHEET
General Description
Features
The 843001I-22 is a a highly versatile, low phase noise
LVPECL/LVCMOS Synthesizer which can generate low jitter
reference clocks for a variety of communications applications and is
a member of the family of high performance clock solutions from IDT.
The dual crystal interface allows the synthesizer to support up to two
communication standards in a given application (i.e. 1GB Ethernet
with a 25MHz crystal and 1Gb Fibre Channel using a 26.5625MHz
crystal). The rms phase jitter performance is typically less than 1ps,
thus making the device acceptable for use in demanding
applications such as OC48 SONET and 10Gb Ethernet. The
843001I-22 is packaged in a small 24-pin TSSOP package.
•
One 3.3Vdifferential LVPECL output pair and
one LVCMOS/LVTTL single-ended reference clock output
•
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
•
•
•
VCO range: 490MHz – 640MHz
•
RMS phase jitter @ 125MHz (1.875MHz - 20MHz):
0.50ps (typical)
•
•
•
Control Input Function Table
Input
Output frequency range: 49MHz – 640MHz
Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
Full 3.3V or 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Outputs
OE
Q/nQ
REF_OUT
0
High-Impedance
High-Impedance
1
High-Impedance
Active
FLOAT
Active
High-Impedance
Pin Assignment
VCCO_LVCMOS
N0
N1
N2
VCCO_LVPECL
Q
nQ
VEE
VCCA
VCC
XTAL_OUT1
XTAL_IN1
Block Diagram
3
N2:N0
SEL0 Pulldown
N
XTAL_IN0
00
11
XTAL_OUT0
XTAL_IN1
OSC
01
Phase
Detector
VCO
490MHz-640MHz
10
01
00
XTAL_OUT1
CLK Pulldown
24
23
22
21
20
19
18
17
16
15
14
13
REF_OUT
VEE
OE
M2
M1
M0
MR
SEL1
SEL0
CLK
XTAL_IN0
XTAL_OUT0
843001I-22
SEL1 Pulldown
OSC
1
2
3
4
5
6
7
8
9
10
11
12
10
000
001
010
011
100
101
000
001
010
011
÷1
÷2
÷3
÷4 (default)
100
101
110
111
÷5
÷6
÷8
÷10
Q
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
nQ
M
÷18
÷22
÷24
÷25
÷32 (default)
÷40
MR Pulldown
M2:M0
3
REF_CLK
OE Pullup/Pulldown
843001I-22 Rev B 11/16/15
1
©2015 Integrated Device Technology, Inc.
843001I-22 DATA SHEET
Table 1. Pin Descriptions
Number
Name
1
VCCO_LVCMOS
Power
Type
2, 3
N0, N1
Input
Pullup
4
N2
Input
Pulldown
Description
Output supply pin for REF_CLK output.
Output divider select pins. Default ÷4. LVCMOS/LVTTL interface levels.
See Table 3C.
5
VCCO_LVPECL
Power
Output supply pin for LVPECL output.
6, 7
Q, nQ
Output
Differential output pair. LVPECL interface levels.
8, 23
VEE
Power
Negative supply pins.
9
VCCA
Power
Analog supply pin.
10
VCC
Power
Core supply pin.
11,
12
XTAL_OUT1,
XTAL_IN1
Input
Parallel resonant crystal interface.
XTAL_OUT1 is the output, XTAL_IN1 is the input.
13,
14
XTAL_OUT0,
XTAL_IN0
Input
Parallel resonant crystal interface.
XTAL_OUT0 is the output, XTAL_IN0 is the input.
15
CLK
Input
Pulldown
LVCMOS/LVTTL clock input.
16, 17
SEL0, SEL1
Input
Pulldown
Input MUX select pins. LVCMOS/LVTTL interface levels. See Table 3D.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true output Q to go low and the inverted output nQ to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
18
MR
Input
Pulldown
19, 20
M0, M1
Input
Pulldown
21
M2
Input
Pullup
22
OE
Input
24
REF_OUT
Output
Feedback divider select pins. Default value = ÷32. See Table 3B.
LVCMOS/LVTTL interface levels.
3-State clock output enable, (High/Low/Float). See page 1, Control Input Function
Table.
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
ROUT
Output Impedance
15
Rev B 11/16/15
Test Conditions
REF_OUT
2
Minimum
Typical
Maximum
Units
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843001I-22 DATA SHEET
Function Tables
Table 3A. Common Configuration Table
Input
Reference Clock (MHz)
M Divider
Value
N Divider
Value
VCO (MHz)
Output Frequency
(MHz)
Application
27
22
8
594
74.25
HDTV
22.4
25
8
560
70
24.75
24
8
594
74.25
HDTV
25
24
3
600
200
Processor
14.8351649
40
8
593.4066
74.1758245
HDTV
19.44
32
4
622.08
155.52
SONET
19.44
32
8
622.08
77.76
SONET
19.44
32
1
622.08
622.08
SONET
19.44
32
2
622.08
311.04
SONET
19.53125
32
4
625
156.25
10 GigE
20
25
2
500
250
Ethernet
25
25
5
625
125
1 GigE
25
25
10
625
62.5
1 GigE
25
24
6
600
100
PCI Express
25
24
4
600
150
SATA
25
24
8
600
75
SATA
26.5625
24
6
637.5
106.25
Fibre Channel 1
26.5625
24
3
637.5
212.5
4 Gig Fibre Channel
26.5625
24
4
637.5
159.375
10 Gig Fibre Channel
31.25
18
3
562.5
187.5
12 GigE
Table 3B. Programmable M Output Divider Function Table
Inputs
Input Frequency (MHz)
M2
M1
M0
M Divider
Value
0
0
0
18
27.22
35.56
0
0
1
22
22.27
29.09
0
1
0
24
20.41
26.67
0
1
1
25
19.6
25.6
1
0
0
32
15.31
20
1
0
1
40
12.25
16
Minimum
Maximum
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
3
Rev B 11/16/15
843001I-22 DATA SHEET
Table 3C. Programmable N Output DividerFunction Table
Inputs
N2
N1
N0
M Divider
Value
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4 (default)
1
0
0
5
1
0
1
6
1
1
0
8
1
1
1
10
Table 3D. Bypass Mode Function Table
Inputs
SEL1
SEL0
Reference
PLL Mode
0
0
XTAL0
Active
0
1
XTAL1
Active
1
0
CLK
Active
1
1
CLK
Bypass
Rev B 11/16/15
4
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843001I-22 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, VO (LVCMOS)
-0.5V to VCCO_LVCMOS + 0.5V
Package Thermal Impedance, JA
70C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 3.3V ± 10%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
VCC
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
2.97
3.3
3.63
V
VCCA
Analog Supply Voltage
2.97
3.3
3.63
V
VCCO_PECL,
VCCO_CMOS
Output Supply Voltage
2.97
3.3
3.63
V
IEE
Power Supply Current
160
mA
ICCO_LVPECL +
ICCO_LVCMOS
Output Supply Current
8
mA
Table 4B. Power Supply DC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
VCC
Minimum
Typical
Maximum
Units
Core Supply Voltage
2.375
2.5
2.625
V
VCCA
Analog Supply Voltage
2.375
2.5
2.625
V
VCCO_PECL,
VCCO_CMOS
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
155
mA
ICCO_LVPECL +
ICCO_LVCMOS
Output Supply Current
8
mA
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
Test Conditions
5
Rev B 11/16/15
843001I-22 DATA SHEET
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = VCCO_LVCMOS = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIM
Input Medium Voltage
VIL
Input Low Voltage
IIH
IIM
IIL
Test Conditions
Minimum
VCC = 3.63V
VCC = 2.625V
Typical
Maximum
Units
2
VCC + 0.3
V
1.7
VCC + 0.3
V
VCC = 3.63V
V
VCC = 2.625V
V
VCC = 3.63V
-0.3
0.8
V
VCC = 2.625V
-0.3
0.7
V
CLK, M0, M1, N2,
MR, OE, SEL0, SEL1
VCC = VIN = 3.63V or
2.625V
150
µA
M2, N0, N1
VCC = VIN = 3.63V or
2.625V
5
µA
Input High Current
Input Medium Current
µA
CLK, M0, M1, N2,
MR, OE, SEL0, SEL1
VCC = 3.63V or 2.625V,
VIN = 0V
-5
µA
M2, N0, N1, OE
VCC = 3.63V or 2.625V,
VIN = 0V
-150
µA
VCCO_LVCMOS = 3.63V
2.6
V
VCCO_LVCMOS = 2.625V
1.8
V
Input Low Current
VOH
Output High Voltage:
NOTE 1
REF_OUT
VOL
Output Low Voltage:
NOTE 1
REF_OUT
VCCO_LVCMOS = 3.63V or
2.625V
0.5
V
NOTE 1: Output terminated with 50 to VCCO _LVCMOS/2. See Parameter Measurement Information Section,
"3.3V LVCMOS Output Load Test Circuit Diagram”.
Table 4D. LVPECL DC Characteristics, VCC = VCCO_LVPECL = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Current; NOTE 1
VOL
Output Low Current; NOTE 1
VSWING
Peak-toPeak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCCO – 1.4
VCCO – 0.9
µA
VCCO – 2.0
VCCO – 1.7
µA
0.6
1.0
V
NOTE 1: Outputs termination with 50 to VCCO_LVPECL – 2V.
Rev B 11/16/15
6
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843001I-22 DATA SHEET
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Maximum
Units
35.55
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
Drive Level
1
mW
Mode of Oscillation
Typical
Fundamental
Frequency
14
NOTE: Characterized using an 18pF parallel resonant crystal.
Table 6. Input Frequency Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL 3.3V ± 10%, VEE = 0V,TA = -40°C to 85°C
Symbol
Parameter
fIN
Input Frequency
Test Conditions
Minimum
CLK
SEL1 = 1, SEL0 = 0
CLK
SEL1 = 1, SEL0 = 0
Typical
Maximum
Units
14
35.55
MHz
DC
250
MHz
AC Electrical Characteristics
Table 7A. AC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 3.3V ± 10%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 1
fVCO
PLL VCO Lock Range
tR / tF
Output
Rise/Fall Time
odc
Output Duty Cycle
Minimum
Typical
49
125MHz,
(1.875MHz – 20MHz)
Maximum
Units
640
MHz
0.50
ps
490
640
MHz
Q/nQ
20% to 80%
200
500
ps
REF_OUT
20% to 80%
200
700
ps
45
55
%
ƒ 250MHz
44
56
%
Q/nQ
REF_OUT
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Phase jitter measured using a crystal interface.
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
7
Rev B 11/16/15
843001I-22 DATA SHEET
Table 7B. AC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 1
fVCO
PLL VCO Lock Range
tR / tF
Output
Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
49
125MHz,
(1.875MHz – 20MHz)
Maximum
Units
640
MHz
0.50
ps
490
640
MHz
Q/nQ
20% to 80%
200
500
ps
REF_OUT
20% to 80%
300
800
ps
45
55
%
44
56
%
Q/nQ
REF_OUT
ƒ 250MHz
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Phase jitter measured using a crystal interface.
Rev B 11/16/15
8
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843001I-22 DATA SHEET
Typical Phase Noise at 125MHz
.
0
-20
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.50ps (typical)
-10
10Gb Ethernet Filter
-30
-40
-50
-70
-80
-90
-100
-110
Noise Power
dBc
Hz
-60
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
9
Rev B 11/16/15
843001I-22 DATA SHEET
Parameter Measurement Information
2V
1.65V±5%
VCC,
VCCA,
VCCO_LVPECL
Qx
SCOPE
SCOPE
VCC,
VCCA,
VCCO_LVCMOS
Qx
GND
nQx
VEE
-1.65V±5%
-1.3V± 0.165V
3.3V LVPECL Output Load AC Test Circuit
3.3V LVCMOS Output Load AC Test Circuit
2V
1.25V±5%
VCC,
Qx
SCOPE
SCOPE
VCC,
VCCA,
VCCO_LVCMOS
VCCA,
VCCO_LVPECL
nQx
Qx
GND
VEE
-1.25V±5%
-0.5V±0.125V
2.5V LVPECL Output Load AC Test Circuit
2.5V LVCMOS Output Load AC Test Circuit
Phase Noise Plot
V
Noise Power
CCO_CMOS
2
REF_OUT
t PW
t
Phase Noise Mask
f1
Offset Frequency
odc =
PERIOD
t PW
x 100%
t PERIOD
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
Rev B 11/16/15
LVCMOS Output Duty Cycle/Pulse Width/Period
10
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843001I-22 DATA SHEET
Parameter Measurement Information, continued
nQ
80%
80%
Q
20%
20%
REF_OUT
LVPECL Output Duty Cycle/Pulse Width/Period
tR
tF
LVCMOS Output Rise/Fall Time
nQ
Q
LVPECL Output Rise/Fall Time
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 843001I-22 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VCC, VCCA, VCCO_X should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VCC pin and also shows that VCCA requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the VCCA pin.
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
3.3V or 2.5V
VCC
.01µF
10Ω
.01µF
10µF
VCCA
Figure 1. Power Supply Filtering
11
Rev B 11/16/15
843001I-22 DATA SHEET
Crystal Input Interface
The 843001I-22 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 26.5625MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
XTAL_IN
C1
22pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
22pF
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
VDD
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 applications, R1 and R2
can be 100. This can also be accomplished by removing R1 and
making R2 50. By overdriving the crystal oscillator, the device will
be functional, but note, the device performance is guaranteed by
using a quartz crystal.
VDD
R1
Ro
Rs
0.1µf
50Ω
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
Rev B 11/16/15
12
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843001I-22 DATA SHEET
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVPECL Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
The unused LVPECL output pair can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Output
CLK Input
All unused LVCMOS output can be left floating. We recommend that
there is no trace attached.
For applications not requiring the use of the clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 4A. 3.3V LVPECL Output Termination
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
R2
84
Figure 4B. 3.3V LVPECL Output Termination
13
Rev B 11/16/15
843001I-22 DATA SHEET
Termination for 2.5V LVPECL Outputs
level. The R3 in Figure 5B can be eliminated and the termination is
shown in Figure 5C.
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground
2.5V
2.5V
VCCO = 2.5V
2.5V
VCCO = 2.5V
R1
250
R3
250
50
+
50
+
50
–
50
–
2.5V LVPECL Driver
R1
50
2.5V LVPECL Driver
R2
62.5
R4
62.5
R2
50
R3
18
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V
VCCO = 2.5V
50
+
50
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 5C. 2.5V LVPECL Driver Termination Example
Rev B 11/16/15
14
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843001I-22 DATA SHEET
Schematic Layout
and C5 may be slightly adjusted for optimizing frequency accuracy.
Two examples of LVPECL terminations and one example of
LVCMOS are shown in this schematic. Additional termination
approaches are shown in the LVPECL Termination Application
Note.
Figure 6 shows an example of 843001I-22 application schematic. In
this example, the device is operated at VCC = VCCO_LVCMOS =
VCCO_LVPECL = 3.3V. The 18pF parallel resonant 25MHz crystal is
used. The C1 = C2 = 22pF and C4 = C5 = 22pF are recommended
for frequency accuracy. For different board layouts, the C1, C2, C4
Logic Control Input Examples
Set Logic
Input to
'1'
VCC
RU1
1K
Set Logic
Input to
'0'
VCC
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
R1
33
To Logic
Input
pins
Zo = 50 Ohm
REF_OUT
RD2
1K
3.3V
LVCMOS
VCC
VCCO_LVCMOS
R2
133
U1
Zo = 50 Ohm
VCCO_LVPECL
N0
N1
N2
VCC
R4
VCC
10
VCCA
C7
0.1u
C6
10u
Q
nQ
VCC
XTAL_OUT1
XTAL_IN1
C3
.1uf
1
2
3
4
5
6
7
8
9
10
11
12
VCCO_LVCMOS REF_OUT
N0
VEE
N1
OE
M2
N2
VCCO_LVPECL
M1
Q
M0
nQ
MR
VEE
SEL1
VCCA
SEL0
VCC
CLK
XTAL_OUT1
XTAL_IN0
XTAL_IN1
XTAL_OUT0
RU3
1K
24
23
22
21
20
19
18
17
16
15
14
13
R3
133
Q
TL2
OE
M2
M1
M0
MR
SEL1
SEL0
CLK
XTAL_IN0
XTAL_OUT0
+
Zo = 50 Ohm
/Q
RD3
1K
-
TL3
R5
82.5
VCC=3.3V
R6
82.5
VCCO_LVCMOS=3.3V
VCCO_LVPECL=3.3V
F
p
8
1
C2
22pF
X2
26.5625MHz
F
p
8
1
X1
25MHz
C4
22pF
Zo = 50 Ohm
Q
C5
22pF
+
C1
22pF
Zo = 50 Ohm
/Q
-
VDD
VCCO
R7
50
Q1
(U1:1) VDDO (U1:5)
Ro ~ 7 Ohm
R9
43
C8
.1uf
C9
.1uf
Zo = 50 Ohm
Optional
LVPECL
Y-Termination
R8
50
R10
50
Driv er_LVCMOS
843001I-22 Layout Example
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
15
Rev B 11/16/15
843001I-22 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 843001I-22.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 843001I-22 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 160mA = 554.4mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.3V, with all outputs switching) = 554.4mW + 30mW = 584.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air
flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.584W * 65°C/W = 123°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 8. Thermal Resitance JA for 24 Lead TSSOP, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
Rev B 11/16/15
0
1
2.5
70°C/W
65°C/W
62°C/W
16
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843001I-22 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCOO_MAX – 1.7V
(VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) =
[(2V - 0.9V)/50] * 0.9V = 19.8mW
L
L
Pd_L = [(VOL_MAX (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) =
[(2V - 1.7V)/50] * 1.7V = 10.2mW
–
L
L
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
17
Rev B 11/16/15
843001I-22 DATA SHEET
Reliability Information
Table 9. JA vs. Air Flow Table for a 24 Lead TSSOP
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
Transistor Count
The transistor count for 843001I-22 is: 3881
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP
Table 10. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
24
A
1.20
A1
0.5
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
6.10 mm. Body, 0.65 mm. Pitch TSSOP
(240 mil)*
Rev B 11/16/15
(25.6mil)*
18
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843001I-22 DATA SHEET
Ordering Information
Table 11. Ordering Information
Part/Order Number
843001AGI-22LF
843001AGI-22LFT
Marking
ICS43001AI22L
ICS43001AI22L
Package
“Lead-Free” 24 Lead TSSOP
“Lead-Free” 24 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
19
Rev B 11/16/15
843001I-22 DATA SHEET
Revision History Sheet
Rev
Table
Page
1
A
A
B
B
B
Rev B 11/16/15
3/23/07
16
19
Power Considerations - Changed Ambient Temperature from 70° to 85°
Ordering Information - Removed “ICS” from Part/Order Number
2/19/09
1
Corrected block diagram. When updated format on 3/23/07, block diagram was not
duplicated correctly.
Added Schematic layout.
Updated header/footer.
6/25/09
Removed leaded orderable parts from Ordering Information table
11/14/12
Updated data sheet format.
11/16/15
15
T11
Date
General Description - corrected crystal frequency from 25.5625MHz crystal to
26.5625MHz crystal.
Added LVCMOS to XTAL Interface section.
Updated format throughout the datasheet.
12
T11
Description of Change
19
20
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
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