PRELIMINARY
ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO3.3V LVPECL/LVCMOS SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS843001I-23 is a highly versatile, low phase
ICS
noise LVPECL/LVCMOS Synthesizer which can
HiPerClockS™ generate low jitter reference clocks for a variety of
communication applications and is a member of
the HiPerClocksTM family of high performance clock
solutions from IDT. The dual crystal interface
allows the synthesizer to support up to three communication
standards in a given application (i.e. SONET with a 19.44MHz
crystal, 1Gb/10Gb Ethernet and Fibre Channel using a 25MHz
crystal). The rms phase jitter performance is typically less than
1ps, thus making the device acceptable for use in demanding
applications such as OC48 SONET, GbE/10Gb Ethernet
and SAN applications. The ICS843001I-23 is packaged in
a small 24-pin TSSOP package.
• One 3.3V LVPECL output pair and
one LVCMOS/LVTTL REF_OUT output
• Selectable crystal oscillator interfaces
or LVCMOS/LVTTL single-ended input
• Crystal and CLK range: 17.5MHz - 29.54MHz
• Able to generate GbE/10GbE/12GbE, Fibre Channel
(1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal
• VCO range: 1.12GHz - 1.3GHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.9ps (typical) @ 3.3V
• Supply modes:
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
3
N2:N0
SEL0 Pulldown
SEL1 Pulldown
N
XTAL_IN0
OSC
00
11
XTAL_OUT0
XTAL_IN1
01
OSC
Phase
Detector
VCO
XTAL_OUT1
10
11
CLK Pulldown
000
001
010
011
100
111
10
01
00
000
001
÷2
÷4
010
011
100
÷5
÷6
÷8 (default)
101
110
111
÷10
÷12
÷16
Q
nQ
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
REF_OUT
VEE
OE_REF
M2
M1
M0
MR
SEL1
SEL0
CLK
XTAL_IN0
XTAL_OUT0
ICS843001I-23
M
÷44
÷45
÷48
÷50
÷51
÷64 (default)
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
MR Pulldown
M2:M0 Pullup
VCCO_LVCMOS
N0
N1
N2
VCCO_LVPECL
Q
nQ
VEE
VCCA
VCC
XTAL_OUT1
XTAL_IN1
3
REF_OUT
OE_REF Pulldown
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VCCO_CMOS
Power
Type
Description
2, 3
N0, N1
Input
4
N2
Input
5
VCCO_LVPECL
Power
Output supply pin for LVPECL output.
Output supply pin for LVCMOS/LVTTL REF_OUT output.
Pulldown Output divider select pins. See Table 3C.
LVCMOS/LVTTL interface levels.
Pullup
6, 7
Q, nQ
Ouput
Differential output pair. LVPECL interface levels.
8, 23
VEE
Power
Negative supply pin.
9
VCCA
Power
Analog supply pin.
10
11
12
13
14
15
VCC
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
CLK
Power
16, 17
SEL0, SEL1
Input
18
MR
Input
19, 20 , 21
M0, M1, M2
Input
22
OE_REF
Input
24
REF_OUT
Output
Input
Input
Input
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant cr ystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Pulldown LVCMOS/LVTTL clock input.
Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true output Q to go low and the inver ted output nQ to
Pulldown
go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Feedback divider select pins. See Table 3B.
Pullup
LVCMOS/LVTTL interface levels.
Reference clock output enable. Default Low. See Table 3E.
Pulldown
LVCMOS/LVTTL interface levels.
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLDOWN
Power Dissipation
Capacitance
Input Pulldown Resistor
51
kΩ
RPULLUP
Input Pullup Resistor
51
kΩ
Rout
Output Impedance
20
Ω
CPD
pF
REF_OUT
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TABLE 3A. COMMON CONFIGURATIONS TABLE
Input
XTAL Input (MHz)
Feedback
Divider
VCO (MHz)
N Divider Value
Output Frequency
(MHz)
Application
27
44
1188
16
74.25
HDTV
24.75
48
1188
16
74.25
HDTV
19.44
64
1244.16
8
155.52
SONET
19.44
64
1244.16
2
622.08
SONET
19.44
64
1244.16
4
311.04
SONET
25
50
1250
10
125
GigE
25
50
1250
8
156.25
10 GigE
25
50
1250
5
25 0
GigE
25
50
1250
4
312.5
XGMII
25
50
1250
2
625
10 GigE
25
45
1125
6
187.5
12 GigE
25
48
1200
12
100
PCI Express
25
48
1200
8
150
SATA
25
48
1200
16
75
SATA
25
51
1275
12
106.25
Fibre Channel
25
51
1275
8
159.375
10 Gig Fibre Channel
25
51
1275
6
212.5
4 Gig Fibre Channel
TABLE 3C. PROGRAMMABLE N OUTPUT DIVIDER
FUNCTION TABLE
TABLE 3B. PROGRAMMABLE M OUTPUT DIVIDER
FUNCTION TABLE
Inputs
Inputs
Input Frequency
M2
M1
M0
M Divider
Value
Minimum
Maximum
N2
N1
N0
0
0
0
44
25.5
29.54
0
0
0
2
0
1
4
1
0
5
0
0
1
45
24.9
28.88
0
0
1
0
48
23.3
27.08
0
N Divide Value
0
1
1
50
22.4
26.0
0
1
1
6
1
0
0
51
22.0
25.49
1
0
0
8 (default)
1
1
1
(default)
17.5
20.31
1
0
1
10
1
1
0
12
1
1
1
16
64
TABLE 3D. BYPASS MODE FUNCTION TABLE
Inputs
SEL1
SEL0
Reference Input
TABLE 3E. OE_REF OUTPUT FUNCTION TABLE
PLL Mode
Inputs
Output
OE_REF
REF_OUT
0
0
XTAL0
Active
0
Hi-Z
0
1
XTAL1
Active
1
Active
1
0
CLK
Active
1
1
CL K
Bypass
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, VO (LVCMOS)
-0.5V to VCCO_LVCMOS + 0.5V
Package Thermal Impedance, θJA
Storage Temperature, TSTG
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
82.3°C/W (0 mps)
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Analog Supply Voltage
VCCO_LVPECL
Output Supply Voltage
VCCO_LVCMOS
Output Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCC – 0.05
3.3
VCC
V
3.135
3.3
3.465
V
3.135
3.3
3.465
V
IEE
Power Supply Current
105
mA
ICCA
Analog Supply Current
5
mA
ICCO
Output Supply Current
5
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VCC – 0.05
3.3
VCC
V
VCCO_LVPECL
Output Supply Voltage
2.375
2.5
2.625
V
VCCO_LVCMOS
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
105
mA
ICCA
Analog Supply Current
5
mA
ICCO
Output Supply Current
5
mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Analog Supply Voltage
VCCO_LVPECL
Output Supply Voltage
VCCO_LVCMOS
Output Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
VCC – 0.05
2.5
VCC
V
2.375
2.5
2.625
V
2.375
2.5
2.625
V
IEE
Power Supply Current
100
mA
ICCA
Analog Supply Current
5
mA
ICCO
Output Supply Current
5
mA
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
IIL
VOH
Input
Low Current
Output High
Voltage; NOTE 1
Test Conditions
CLK, SEL0, SEL1,
OE_REF, MR, N0, N1
N2, M0:M2
CLK, SEL0, SEL1,
OE_REF, MR, N0, N1
N2, M0:M2
Maximum
Units
VCC = 3.3V
Minimum Typical
2
VCC + 0.3
V
VCC = 2.5V
1.7
VCC + 0.3
V
VCC = 3.3V
-0.3
0.8
V
VCC = 2.5V
VCC = VIN = 3.465V
or 2.625V
VCC = VIN = 3.465V
-0.3
0.7
V
150
µA
5
µA
or 2.625V
VCC = 3.465V or 2.625V,
VIN = 0V
VCC = 3.465V or 2.625V,
VIN = 0V
VCCO_LVCMOS = 3.465V
REF_OUT
-5
µA
-150
µA
2.6
V
VCCO_LVCMOS = 2.625V
1. 8
VCCO_LVCMOS = 3.465V
VOL
REF_OUT
or 2.625V
Input Edge Rate CLK
20% - 80%
ΔV/ΔT
NOTE 1: Output terminated with 50Ω to VCCO _LVCMOS/2. See Parameter Measurement Information Section,
"Output Load Test Circuit Diagram" diagrams.
Output Low
Voltage; NOTE 1
V
0.5
V
TB D
V/ns
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCO_LVPECL = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
VCCO_LVPECL - 1.4
Minimum
Typical
VCCO_LVPECL - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO_LVPECL - 2.0
VCCO_LVPECL - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V.
TABLE 4F. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5% or 2.5V±5%, VCCO_LVPECL = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCCO_LVPECL - 1.4
VCCO_LVPECL - 0.9
V
VCCO_LVPECL - 2.0
VCCO_LVPECL - 1.5
V
0.4
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Fundamental
Frequency
17.5
Units
MHz
29.54
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TABLE 6A. AC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
fVCO
Output Frequency
Propagation
CLK to
Delay, NOTE 1
REF_OUT
RMS Phase Jitter, (Random);
NOTE 2, 3
PLL VCO Lock Range
tL_SEL
Select Time
tL_M
PLL Lock Time
tPD
tjit(Ø)
t R / tF
Output
Rise/Fall Time
Test Conditions
Minimum
Typical
56
622.08MHz (12kHz - 20MHz)
Maximum
Units
650
MHz
2.5
ns
0. 9
ps
1.12
1.3
GHz
ms
ms
Q/nQ
20% to 80%
300
ps
REF_OUT
20% to 80%
50 0
ps
Q/nQ
50
%
odc
Output Duty Cycle
REF_OUT
50
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quar tz cr ystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
fVCO
Output Frequency
Propagation
CLK to
Delay, NOTE 1
REF_OUT
RMS Phase Jitter, (Random);
NOTE 2, 3
PLL VCO Lock Range
tL_SEL
Select Time
ms
tL_M
PLL Lock Time
ms
t R / tF
Output
Rise/Fall Time
tPD
tjit(Ø)
Test Conditions
Minimum
Typical
56
622.08MHz (12kHz - 20MHz)
Maximum
Units
650
MHz
3.5
ns
1
ps
1.12
1.3
GHz
Q/nQ
20% to 80%
300
ps
REF_OUT
20% to 80%
50 0
ps
Q/nQ
50
%
REF_OUT
50
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quar tz cr ystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
odc
Output Duty Cycle
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TABLE 6C. AC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Test Conditions
fVCO
Output Frequency
Propagation
CLK to
Delay, NOTE 1
REF_OUT
RMS Phase Jitter, (Random);
NOTE 2, 3
PLL VCO Lock Range
tL_SEL
Select Time
tL_M
PLL Lock Time
tPD
tjit(Ø)
t R / tF
Output
Rise/Fall Time
Minimum
Typical
56
622.08MHz (12kHz - 20MHz)
Maximum
Units
650
MHz
3
ns
1.1
ps
1.12
1.3
GHz
ms
ms
Q/nQ
20% to 80%
300
ps
REF_OUT
20% to 80%
500
ps
Q/nQ
50
%
odc
Output Duty Cycle
REF_OUT
50
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quar tz cr ystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
2V
1.65V±5%
2V
VCC,
VCCO_LVPECL
Qx
SCOPE
VCC,
VCCO_LVCMOS
SCOPE
VCCA
VCCA
Qx
LVCMOS
LVPECL
GND
nQx
VEE
-1.65V±5%
-1.3V±0.165V
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
2.8V±0.04V
2.05V±5%
2V
1.25V±5%
2.8V±0.04V
2.05V±5%
VCC
VCCO_LVPECL
Qx
SCOPE
VCCO_LVCMOS
VCCA
LVPECL
SCOPE
VCC
Qx
VCCA
LVCMOS
nQx
GND
VEE
-1.25V±5%
-0.5V±0.125V
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
1.25V±5%
2V
1.25V±5%
2V
VCC,
VCCO_LVPECL
Qx
SCOPE
VCC,
VCCO_LVCMOS
SCOPE
VCCA
VCCA
Qx
LVCMOS
LVPECL
GND
nQx
VEE
-1.25V±5%
-0.5V±0.125V
2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
Noise Power
Phase Noise Plot
nQ
Q
Phase Noise Mask
t PW
t
f1
Offset Frequency
f2
odc =
PERIOD
t PW
x 100%
t PERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
RMS PHASE JITTER
nQ
V
CCO_LVCMOS
80%
2
REF_OUT
VSW I N G
t PW
t
odc =
80%
20%
20%
Q,
REF_OUT
PERIOD
t PW
tR
tF
x 100%
t PERIOD
OUTPUT RISE/FALL TIME
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VCC
2
CLK
VCCO_LVCMOS
REF_OUT
2
t
PD
PROPAGATION DELAY
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843001I-23
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_X
should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 1 illustrates this for a generic VCC pin and
also shows that VCCA requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the VCCA pin.
3.3V or 2.5V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
OUTPUTS:
LVCMOS OUTPUT
The unused LVCMOS output can be left floating. There should
be no trace attached.
LVPECL OUTPUT
The unused LVPECL output pair can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or terminated.
CLK INPUT
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
CRYSTAL INPUT INTERFACE
Figure 2 below were determined using an 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The ICS843001I-23 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS84332
FIGURE 2. CRYSTAL INPUT INTERFACE
LVCMOS TO XTAL INTERFACE
series resistance (Rs) equals the transmission line impedance.
In addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the transmission
line impedance. For most 50Ω applications, R1 and R2 can be
100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram
is shown in Figure 3. The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS
signals, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration
requires that the output impedance of the driver (Ro) plus the
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
Zo = Ro + Rs
XTAL_IN
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
11
TO
XTAL INPUT INTERFACE
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended that the
board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FOUT
50Ω
VCC - 2V
FIN
Zo = 50Ω
RTT
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
84Ω
FIGURE 4B. LVPECL OUTPUT TERMINATION
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PRELIMINARY
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination
is shown in Figure 5C.
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001I-23.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001I-23 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 105mA = 363.8mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 363.8mW + 30mW = 393.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 82.3°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.394W * 82.3°C/W = 117.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 7. THERMAL RESISTANCE θJA
FOR
24-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
0
1
2.5
82.3°C/W
78.0°C/W
75.9°C/W
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (V _MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) =
L
CCO
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (V
L
CCO_MAX
- VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) =
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
82.3°C/W
78.0°C/W
75.9°C/W
TRANSISTOR COUNT
The transistor count for ICS843001I-23 is: 4165
PACKAGE OUTLINE
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
AND
DIMENSIONS
TABLE 9. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
24
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
E
E1
7.90
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
843001BGI-23
ICS843001BI23
24 Lead TSSOP
tube
-40°C to 85°C
843001BGI-23T
ICS843001BI23
24 Lead TSSOP
2500 tape & reel
-40°C to 85°C
843001BGI-23LF
ICS43001BI23L
24 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
843001BGI-23LFT
ICS43001BI23L
24 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT ™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
PRELIMINARY
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www.IDT.com
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Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
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