843001CGI-23LF

FemtoClock® Crystal/LVCMOS-toLVPECL/ LVCMOS Frequency Synthesizer ICS843001I-23 DATA SHEET General Description The ICS843001I-23 is a highly versatile, low phase noise LVPECL/LVCMOS Synthesizer which can generate low jitter reference clocks for a variety of communication applications. The dual crystal interface allows the synthesizer to support up to three communication standards in a given application (i.e. SONET with a 19.44MHz crystal, 1Gb/10Gb Ethernet and Fibre Channel using a 25MHz crystal). The RMS phase jitter performance is typically less than 1ps, thus making the device acceptable for use in demanding applications such as OC48 SONET, GbE/10Gb Ethernet and SAN applications. The ICS843001I-23 is packaged in a small 24-pin TSSOP, E-Pad package. Features • • • • • • • • One 3.3Vdifferential LVPECL output pair and one LVCMOS/LVTTL single-ended reference clock output Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input Crystal and CLK range: 19.44MHz – 27MHz Able to generate GbE/10GbE/12GbE, Fibre Channel (1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal VCO range: 1.12GHz – 1.275GHz Supports the following applications: SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV RMS phase jitter @ 622.08MHz (12kHz - 20MHz): 0.9ps (typical), 3.3V Supply modes VCC/VCCO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) package • • Block Diagram 3 N2:N0 SEL0 Pulldown SEL1 Pulldown N XTAL_IN0 000 001 010 011 100 101 110 111 ÷2 ÷4 ÷5 ÷6 ÷8 (default) ÷10 ÷12 ÷16 Pin Assignment VCCO_LVCMOS N0 N1 N2 VCCO_LVPECL Q nQ VEE VCCA VCC XTAL_OUT1 XTAL_IN1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF_OUT VEE OE_REF M2 M1 M0 MR SEL1 SEL0 CLK XTAL_IN0 XTAL_OUT0 OSC XTAL_OUT0 XTAL_IN1 00 11 Q nQ OSC XTAL_OUT1 CLK Pulldown 01 Phase Detector VCO 10 01 00 ICS843001I-23 24-Lead TSSOP, E-Pad 4.4mm x 7.8mm x 0.925mm package body G Package Top View 10 11 000 001 010 011 100 111 M ÷44 ÷45 ÷48 ÷50 ÷51 ÷64 (default) MR Pulldown M2:M0 Pullup 3 REF_OUT OE_REF Pulldown ICS843001CGI-23 REVISION A OCTOBER 4, 2011 1 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Table 1. Pin Descriptions Number 1 2, 3 4 5 6, 7 8, 23 9 10 11, 12 13, 14 15 16, 17 Name VCCO_LVCMOS N0, N1 N2 VCCO_LVPECL Q, nQ VEE VCCA VCC XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 CLK SEL0, SEL1 Power Input Input Power Output Power Power Power Input Input Input Input Pulldown Pulldown Pulldown Pullup Type Description Output supply pin for REF_CLK output. Output divider select pins. LVCMOS/LVTTL interface levels. See Table 3C. Output supply pin for LVPECL output. Differential output pair. LVPECL interface levels. Negative supply pins. Analog supply pin. Core supply pin. Parallel resonant crystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Parallel resonant crystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. Single-ended clock input. LVCMOS/LVTTL interface levels. Input MUX select pins. LVCMOS/LVTTL interface levels. See Table 3D. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inverted output nQ to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Feedback divider select pins. LVCMOS/LVTTL interface levels. See Table 3B. Reference clock output enable. Default LOW. See Table 3E. LVCMOS/LVTTL interface levels. Reference clock output. LVCMOS/LVTTL interface levels. 18 MR Input Pulldown 19, 20, 21 22 24 M0, M1, M2 OE_REF REF_OUT Input Input Output Pullup Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance REF_OUT VCCO = 3.3V VCCO = 2.5V Test Conditions Minimum Typical 4 51 51 21 25 Maximum Units pF kΩ kΩ Ω Ω ICS843001CGI-23 REVISION A OCTOBER 4, 2011 2 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Function Tables Table 3A. Common Configuration Table Input Frequency (MHz) 27 24.75 19.44 19.44 19.44 25 25 25 25 25 25 25 25 25 25 25 25 M Feedback Divider Value 44 48 64 64 64 50 50 50 50 50 45 48 48 48 51 51 51 VCO Frequency (MHz) 1188 1188 1244.16 1244.16 1244.16 1250 1250 1250 1250 1250 1125 1200 1200 1200 1275 1275 1275 N Output Divider Value 16 16 8 2 4 10 8 5 4 2 6 12 8 16 12 8 6 Output Frequency (MHz) 74.25 74.25 155.52 622.08 311.04 125 156.25 250 312.5 625 187.5 100 150 75 106.25 159.375 212.5 Application HDTV HDTV SONET SONET SONET GigE 10 GigE GigE XGMII 10 GigE 12 GigE PCI Express SATA SATA Fibre Channel 10 Gig Fibre Channel 4 Gig Fibre Channel Table 3B. Programmable M Feedback Divider Function Table Inputs M2 0 0 0 0 1 1 M1 0 0 1 1 0 0 M0 0 1 0 1 0 1 M Feedback Divider Value 44 45 48 50 51 64 (default) Input Frequency (MHz) Minimum 25.5 24.9 23.3 22.4 22.0 19.44 Maximum 27 27 26.56 25.5 25 19.92 ICS843001CGI-23 REVISION A OCTOBER 4, 2011 3 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Table 3C. Programmable N Output Divider Function Table Inputs N2 0 0 0 0 1 1 1 1 N1 0 0 1 1 0 0 1 1 N0 0 1 0 1 0 1 0 1 N Divider Value 2 4 5 6 8 (default) 10 12 16 Table 3D. Select Mode Function Table Inputs SEL1 0 0 1 1 SEL0 0 1 0 1 Reference Input XTAL0 XTAL1 CLK CLK PLL Mode Active (default) Active Active Bypass Table 3E. OE_REF Output Function Table Input OE_REF 0 1 Output REF_OUT High-Impedance (default) Active ICS843001CGI-23 REVISION A OCTOBER 4, 2011 4 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI XTAL_IN Other Input Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, VO (LVCMOS) Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V 0V to VCC -0.5V to VCC + 0.5V 50mA 100mA -0.5V to VCCO_LVCMOS + 0.5V 32.1°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VCC VCCA Parameter Core Supply Voltage Analog Supply Voltage Test Conditions Minimum 3.135 VCC – 0.11 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VCC 3.465 140 Outputs Unterminated 11 Units V V V mA mA VCCO_LVPECL, Output Supply Voltage VCCO_LVCMOS IEE ICCA Power Supply Current Analog Supply Current Table 4B. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VCC VCCA Parameter Core Supply Voltage Analog Supply Voltage Test Conditions Minimum 3.135 VCC – 0.11 2.375 Typical 3.3 3.3 2.5 Maximum 3.465 VCC 2.625 139 Outputs Unterminated 11 Units V V V mA mA VCCO_LVPECL, Output Supply Voltage VCCO_LVCMOS IEE ICCA Power Supply Current Analog Supply Current ICS843001CGI-23 REVISION A OCTOBER 4, 2011 5 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Table 4C. Power Supply DC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VCC VCCA VCCO_PECL, VCCO_CMOS IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Outputs Unterminated Test Conditions Minimum 2.375 VCC – 0.10 2.375 Typical 2.5 2.5 2.5 Maximum 2.625 VCC 2.625 133 10 Units V V V mA mA Table 4D. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C Symbol VIH Parameter Input High Voltage Test Conditions VCC = 3.3V VCC = 2.5V Input Low Voltage CLK, OE_REF, MR, N0, N1 SEL0, SEL1 IIH Input High Current N2, M[2:0] CLK, OE_REF, MR, N0, N1 SEL0, SEL1 IIL Input Low Current N2, M[2:0] VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V VCC = 3.465V or 2.625V, VIN = 0V VCCO_LVCMOS = 3.465V, IOH = -12mA VCCO_LVCMOS = 2.625V, IOH = -12mA Output Low Voltage REF_OUT VCCO_LVCMOS = 3.465V or 2.625V, IOL = 12mA -5 -150 2.6 1.8 0.5 5 µA µA µA V V V VCC = 3.3V VCC = 2.5V VCC = VIN = 3.465V or 2.625V Minimum 2 1.7 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 150 Units V V V V µA VIL VOH Output High Voltage REF_OUT VOL . Table 4E. LVPECL DC Characteristics, VCC = VCCO_LVPECL = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO_LVPECL – 1.4 VCCO_LVPECL – 2.0 0.6 Typical Maximum VCCO_LVPECL – 0.9 VCCO_LVPECL – 1.7 1.0 Units V V V NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL – 2V. ICS843001CGI-23 REVISION A OCTOBER 4, 2011 6 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Table 4F. LVPECL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VCCO_LVPECL = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO_LVPECL – 1.4 VCCO_LVPECL – 2.0 0.4 Typical Maximum VCCO_LVPECL – 0.9 VCCO_LVPECL – 1.5 1.0 Units V V V NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL – 2V. Table 5. Crystal Characteristics Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pF parallel resonant crystal. 19.44 Test Conditions Minimum Typical Fundamental 27 50 7 MHz Maximum Units Ω pF AC Electrical Characteristics Table 6A. AC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol fOUT tPD tjit(Ø) fVCO tR / tF Parameter Output Frequency Propagation Delay; NOTE 1 Q, nQ REF_OUT CLK to REF_OUT 622.08MHz, (12kHz – 20MHz) 1.12 Q, nQ REF_OUT, NOTE 3 Q, nQ odc tLOCK Output Duty Cycle PLL Lock Time REF_OUT; NOTE 3 Using Clock Input 20% to 80% 20% to 80% 200 250 46 48 Test Conditions Minimum 70 19.44 2.2 0.97 1.275 700 650 54 52 60 Typical Maximum 637.5 27 2.7 Units MHz MHz ns ps GHz ps ps % % ms RMS Phase Jitter, (Random); NOTE 2 PLL VCO Lock Range Output Rise/Fall Time NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal. NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%. ICS843001CGI-23 REVISION A OCTOBER 4, 2011 7 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Table 6B. AC Characteristics, VCC = 3.3V ± 5%, VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol fOUT tPD tjit(Ø) fVCO tR / tF Parameter Output Frequency Propagation Delay; NOTE 1 Q, nQ REF_OUT CLK to REF_OUT 622.08MHz, (12kHz – 20MHz) 1.12 Q, nQ REF_OUT Q, nQ odc tLOCK Output Duty Cycle PLL Lock Time REF_OUT; NOTE 3 Using Clock Input 20% to 80% 20% to 80% 200 350 46 48 Test Conditions Minimum 70 19.44 2.3 1 1.275 700 750 54 52 60 Typical Maximum 637.5 27 2.9 Units MHz MHz ns ps GHz ps ps % % ms RMS Phase Jitter, (Random); NOTE 2 PLL VCO Lock Range Output Rise/Fall Time NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal. NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%. Table 6C. AC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol fOUT tPD tjit(Ø) fVCO tR / tF Parameter Output Frequency Propagation Delay; NOTE 1 Q, nQ REF_OUT CLK to REF_OUT 622.08MHz, (12kHz – 20MHz) 1.12 Q, nQ REF_OUT Q, nQ odc tLOCK Output Duty Cycle PLL Lock Time REF_OUT; NOTE 3 Using Clock Input 20% to 80% 20% to 80% 200 350 46 48 Test Conditions Minimum 70 19.44 2.3 1.1 1.275 700 750 54 52 60 Typical Maximum 637.5 27 2.9 Units MHz MHz ns ps GHz ps ps % % ms RMS Phase Jitter, (Random); NOTE 2 PLL VCO Lock Range Output Rise/Fall Time NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal. NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%. ICS843001CGI-23 REVISION A OCTOBER 4, 2011 8 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Typical Phase Noise at 622.08MHz . 622.08MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.97ps (typical) Noise Power dBc Hz Offset Frequency (Hz) ICS843001CGI-23 REVISION A OCTOBER 4, 2011 9 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Parameter Measurement Information 2V 2V 1.65V±5% 1.65V±5% Qx VCC, VCCA VCCO_LVPECL SCOPE VCC, VCCO_LVCMOS VCCA SCOPE Qx nQx VEE VEE -1.3V± 0.165V -1.65V±5% 3.3V LVPECL Output Load AC Test Circuit 2V 2V 3.3V LVCMOS Output Load AC Test Circuit 1.25V±5% 1.25V±5% Qx VCC, VCCO_LVPECL VCCA SCOPE SCOPE VCC, VCCO_LVCMOS VCCA Qx nQx VEE VEE -0.5V±0.125V -1.25V±5% 2.5V LVPECL Output Load AC Test Circuit 2.8V±0.04V 2V 2.8V±0.04V 2.5V LVCMOS Output Load AC Test Circuit 2.05V±5% 1.25V±5% 2.05V±5% VCC Qx VCCO_LVPECL VCCA SCOPE VCC VCCO_LVPECL VCCA SCOPE Qx nQx VEE VEE -0.5V±0.125V -1.25V±5% 3.3 Core/2.5V LVPECL Output Load AC Test Circuit 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit ICS843001CGI-23 REVISION A OCTOBER 4, 2011 10 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Parameter Measurement Information, continued Phase Noise Plot V CCO_CMOS Noise Power REF_OUT 2 t PW t PERIOD f1 Offset Frequency odc = f2 t PW t PERIOD x 100% RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter LVCMOS Output Duty Cycle/Pulse Width/Period nQ Q t PW t PERIOD 80% 20% 80% 20% odc = t PW t PERIOD REF_OUT x 100% tR tF LVPECL Output Duty Cycle/Pulse Width/Period LVCMOS Output Rise/Fall Time nQ 80% 80% VSW I N G Q 20% tR tF 20% LVPECL Output Rise/Fall Time ICS843001CGI-23 REVISION A OCTOBER 4, 2011 11 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Applications Information Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. Outputs: LVPECL Outputs The unused LVPECL output pair can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Output CLK Input For applications not requiring the use of the clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS843001CGI-23 REVISION A OCTOBER 4, 2011 12 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 1A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, 3.3V 3.3V R1 100 Ro ~ 7 Ohm RS Driv er_LVCMOS 43 Zo = 50 Ohm C1 XTAL_IN R2 100 0.1uF XTAL_OUT matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. Cry stal Input Interf ace Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC=3.3V Zo = 50 Ohm C1 XTAL_IN R1 50 0.1uF XTAL_OUT Zo = 50 Ohm LVPECL R2 50 Cry stal Input Interf ace R3 50 Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface ICS843001CGI-23 REVISION A OCTOBER 4, 2011 13 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V 3.3V Zo = 50Ω + 3.3V R3 125Ω Zo = 50Ω 3.3V R4 125Ω 3.3V + _ LVPECL Zo = 50Ω R1 50Ω RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 50Ω VCC - 2V RTT Input LVPECL Zo = 50Ω R1 84Ω R2 84Ω _ Input Figure 2A. 3.3V LVPECL Output Termination Figure 2B. 3.3V LVPECL Output Termination ICS843001CGI-23 REVISION A OCTOBER 4, 2011 14 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Termination for 2.5V LVPECL Outputs Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V 2.5V 2.5V VCCO = 2.5V R1 250 50Ω + 50Ω – 50Ω – R3 250 50Ω + VCCO = 2.5V 2.5V LVPECL Driver R1 50 R2 50 2.5V LVPECL Driver R2 62.5 R4 62.5 R3 18 Figure 3A. 2.5V LVPECL Driver Termination Example Figure 3B. 2.5V LVPECL Driver Termination Example 2.5V VCCO = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 3C. 2.5V LVPECL Driver Termination Example ICS843001CGI-23 REVISION A OCTOBER 4, 2011 15 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Schematic Layout Figure 6 (next page) shows an example of ICS843001I-23 application schematic. In this example, the device is operated VCC = VCCO_LVCMOS = VCCO_LVPECL = 3.3V. The 18pF parallel resonant 17.5-29.54MHz crystal is used. The load capacitance C1 = 22pF and C2 = 22pF are recommended for frequency accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are required for proper operation. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843001I-23 provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequency. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component with high amplitude interference is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally general design practice for power plane voltage stability suggests adding bulk capacitances in the general area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. ICS843001CGI-23 REVISION A OCTOBER 4, 2011 16 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER R E F_O U T R1 33 Z o = 50 Ohm 3. 3V U1 Zo = 50 Ohm Q VC C O V CC R4 10 C4 10u V CCA C6 0. 1u N0 N1 N2 Q nQ VC C XTA L_O U T1 XTAL_I N 1 1 2 3 4 5 6 7 8 9 10 11 12 V C C O_LV C MOS R E F_OU T N0 VE E N1 O E_R E F N2 M2 V C C O_LV PE C L M1 Q M0 nQ MR V EE S EL1 V CCA S EL0 V CC C LK XTA L_OU T1 XTA L_I N 0 XTA L_IN 1 XTAL_OU T0 24 23 22 21 20 19 18 17 16 15 14 13 OE _R E F M2 M1 M0 MR SE L1 SE L0 C LK XTAL_I N 0 XTA L_O U T0 TL2 Zo = 50 Ohm /Q TL3 R5 82. 5 R6 82. 5 + R2 133 R3 133 LV C MOS V CCO VCC=3.3V VCCO_LVCMOS=3.3V VCCO_LVP ECL=3.3V C3 22pF X1 17. 5MH z - 29.54MH z 18pF C2 22pF 1 8 p F X2 17. 5MH z - 29. 54MH z Q C1 22pF /Q Zo = 50 O hm R7 50 Ro ~ 7 Ohm R9 43 Z o = 50 Ohm R8 50 Zo = 50 O hm + C5 22pF V DD Logic Control Input Examples VC C Q1 Set Logic Input to '1' R U1 1K VC C Set Logic Input to '0' RU2 N ot I ns t all Optional LVPECL Y-Termination R 10 50 D riv er_LVC MO S To Logic Input pins R D1 N ot I ns t all RD2 1K To Logic Input pins 3. 3V 1 m urAt a, BLM18B B221S N 1 2 F B1 C7 0. 1uF C8 10uF (U1:10) C9 0. 1uF V CC 3. 3V 1 C 10 0. 1uF m urAt a, BLM18B B221S N 1 2 F B2 C 11 10uF (U1:1) C 12 0. 1uF (U1:5) C 13 0. 1uF V CCO Figure 6. ICS843001I-23 Layout Example ICS843001CGI-23 REVISION A OCTOBER 4, 2011 17 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 7. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology. SOLDER PIN EXPOSED HEAT SLUG SOLDER PIN SOLDER PIN PAD GROUND PLANE THERMAL VIA LAND PATTERN (GROUND PAD) PIN PAD Figure 7. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale) ICS843001CGI-23 REVISION A OCTOBER 4, 2011 18 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS843001I-23. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843001I-23 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW Power (outputs)MAX = 30mW/Loaded Output pair LVCMOS Output Power Dissipation • • Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 21Ω)] = 24.4mA Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 21Ω * (24.4mA)2 = 12.5mW per output Total Power Dissipation • Total Power = Power (core) + Power (LVPECL output) + Power (ROUT) = 485.1mW + 30mW + 12.5mW = 527.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 32.1°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.528W * 32.1°C/W = 102°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resitance θJA for 24 Lead TSSOP, E-Pad Forced Convection θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 32.1°C/W 1 25.5°C/W 2.5 24.0°C/W ICS843001CGI-23 REVISION A OCTOBER 4, 2011 19 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 7. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO – 2V. • • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VCOO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/R ] * (VCCO_MAX – VOH_MAX) = [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW L L Pd_L = [(VOL_MAX (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/R ] * (VCCO_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW – L L Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS843001CGI-23 REVISION A OCTOBER 4, 2011 20 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Reliability Information Table 8. θJA vs. Air Flow Table for a 24 Lead TSSOP, E-pad θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 32.1°C/W 1 25.5°C/W 2.5 24.0°C/W Transistor Count The transistor count for ICS843001I-23 is: 4165 ICS843001CGI-23 REVISION A OCTOBER 4, 2011 21 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP, E-Pad Table 9. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 1.10 A1 0.05 0.15 A2 0.85 0.95 b 0.19 0.30 b1 0.19 0.25 c 0.09 0.20 c1 0.09 0.16 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.50 0.70 P 5.0 5.5 P1 3.0 3.2 α 0° 8° aaa 0.076 bbb 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS843001CGI-23 REVISION A OCTOBER 4, 2011 22 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Ordering Information Table 10. Ordering Information Part/Order Number 843001CGI-23 843001CGI-23T 843001CGI-23LF 843001CGI-23LFT Marking ICS843001CI23 ICS843001CI23 ICS43001CI23L ICS43001CI23L Package 24 Lead TSSOP, E-Pad 24 Lead TSSOP, E-Pad “Lead-Free” 24 Lead TSSOP, E-Pad “Lead-Free” 24 Lead TSSOP, E-Pad Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS843001CGI-23 REVISION A OCTOBER 4, 2011 23 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.