ISL28110FRTZ

Precision Low Noise JFET Operational Amplifiers ISL28110, ISL28210 The ISL28110, ISL28210, are single and dual JFET amplifiers featuring low noise, high slew rate, low input bias current and offset voltage, making them the ideal choice for high impedance applications where precision and low noise are important. The combination of precision, low noise, and high speed combined with a small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. Applications for these amplifiers include precision medical and analytical instrumentation, sensor conditioning, precision power supply controls, industrial controls and photodiode amplifiers. The ISL28110 single amplifier is available in the 8 Ld SOIC, TDFN, and MSOP packages. The ISL28210 dual amplifier is available in the 8 Ld SOIC and TDFN packages. All devices are offered in standard pin configurations and operate over the extended temperature range from -40°C to +125°C. ISL28110, ISL28210 Features • Wide Supply Range. . . . . . . . . . . . . . . . . 9V to 40V • Low Voltage Noise . . . . . . . . . . . . . . . . . . 6nV/√Hz • Input Bias Current . . . . . . . . . . . . . . . . . . . . . 2pA • High Slew Rate. . . . . . . . . . . . . . . . . . . . . . 23V/µs • High Bandwidth . . . . . . . . . . . . . . . . . . . .12.5MHz • Low Input Offset . . . . . . . . . . . . . . . . .300µV, Max • Offset Drift . . . . . . . . . . . . . . . . Grade C 10µV/°C • Low Current Consumption . . . . . . . . . . . . . 2.55mA • Operating Temperature Range . . . -40°C to +125°C • Small Package Offerings in Single, and Dual • Pb-Free (RoHS compliant) Applications*(see page 22) • Precision Instruments • Photodiode Amplifiers • High Impedance Buffers • Medical Instrumentation • Active Filter Blocks • Industrial Controls Typical Application RF CF Input Bias Current vs Common Mode Input Voltage NORMALIZED INPUT BIAS CURRENT (pA) 10 8 6 4 2 0 -2 -4 -6 -8 -10 -15 -10 -5 0 VCM (V) 5 10 15 VS = ±15V V+ PHOTO DIODE RSH CT + OUTPUT V- BASIC APPLICATION CIRCUIT - PHOTODIODE AMPLIFIER December 8, 2010 FN6639.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL28110, ISL28110, ISL28210 Pin Configurations ISL28110 (8 LD TDFN) TOP VIEW NC 1 -IN A 2 +IN A 3 V- 4 PAD -+ 8 NC 7 V+ 6 VOUT A 5 NC ISL28110 (8 LD, SOIC, MSOP) TOP VIEW NC -IN A +IN A V1 2 3 4 -+ 8 NC 7 V+ 6 VOUT A 5 NC ISL28210 (8 LD TDFN) TOP VIEW VOUT A -IN A +IN A V1 2 3 4 PAD -+ +8 V+ 7 VOUT B 6 -IN B 5 +IN B VOUT A -IN A +IN A V1 2 3 4 ISL28210 (8 LD SOIC) TOP VIEW 8 V+ -+ +7 VOUT B 6 -IN B 5 +IN B Pin Descriptions ISL28110 (8 Ld TDFN) 3 2 6 4 ISL28110 (8 Ld SOIC, ISL28210 8 Ld MSOP) (8 Ld TDFN) 3 2 6 4 3 2 1 4 5 6 7 7 1, 5, 8 PAD 7 1, 5, 8 PAD PAD 8 ISL28210 (8 Ld SOIC) 3 2 1 4 5 6 7 8 PIN NAME +IN A -IN A VOUT A V+IN B -IN B VOUT B V+ EQUIVALENT CIRCUIT Circuit 1 Circuit 1 Circuit 2 Circuit 3 Circuit 1 Circuit 1 Circuit 2 Circuit 3 DESCRIPTION Amplifier A non-inverting input Amplifier A inverting input Amplifier A output Negative power supply Amplifier B non-inverting input Amplifier B inverting input Amplifier B output Positive power supply No connect Thermal Pad is electrically isolated from active circuitry. Pad can float, connect to Ground or to a potential source that is free from signals or noise sources. V+ CAPACITIVELY TRIGGERED ESD CLAMP VCIRCUIT 3 V+ ININ+ V+ OUT VCIRCUIT 2 V- CIRCUIT 1 2 FN6639.1 December 8, 2010 ISL28110, ISL28110, ISL28210 Ordering Information PART NUMBER (Notes 1, 2, 3) ISL28110FBZ ISL28210FBZ Coming Soon ISL28110FRTZ Coming Soon ISL28210FRTZ Coming Soon ISL28110FRTBZ Coming Soon ISL28210FRTBZ Coming Soon ISL28110FBBZ Coming Soon ISL28210FBBZ Coming Soon ISL28110FUBZ Coming Soon ISL28110FUZ NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28110, ISL28210. For more information on MSL please see techbrief TB363. PART MARKING 28110 FBZ -C 28210 FBZ -C -C 8110 -C 8210 8110 8210 28110 FBZ -C 28210 FBZ 8110Z 8110Z TCVOS (µV/°C) 10 (C Grade) 10 (C Grade) 10 (C Grade) 10 (C Grade) 4 (B Grade) 4 (B Grade) 4 (B Grade) 4 (B Grade) 4 (B Grade) 10 (C Grade) PACKAGE (Pb-free) 8 Ld SOIC 8 Ld SOIC 8 Ld TDFN 8 Ld TDFN 8 Ld TDFN 8 Ld TDFN 8 Ld SOIC 8 Ld SOIC 8 Ld MSOP 8 Ld MSOP PKG. DWG. # M8.15E M8.15E L8.3x3A L8.3x3A L8.3x3A L8.3x3A M8.15E M8.15E M8.118 M8.118 3 FN6639.1 December 8, 2010 ISL28110, ISL28110, ISL28210 Absolute Voltage Ratings Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Supply Turn On Voltage Slew Rate . . . . . . . . 1V/µs Maximum Differential Input Voltage . . . . . . . . . . . . . . . 33V Min/Max Input Voltage . . . . . . . . . . . V- - 0.5V to V+ + 0.5V Max/Min Input Current for Input Voltage >V+ or 33V reverse breakdown voltage which enables the device to function reliably in large signal pulse applications without the need for anti-parallel clamp diodes required on MOSFET and most bipolar input stage op amps. No special input signal restrictions are needed for power supply operation up to ±15V, and input signal distortion caused by nonlinear clamps under high slew rate conditions are avoided. For power supply operation greater than ±16V (>32V), the internal ESD clamp diodes alone cannot clamp the maximum input differential signal to the power supply rails without the risk of exceeding the 33V breakdown of the JFET gate. Under these conditions, differential input voltage limiting is necessary to prevent damage to the JFET input stage. Operating Voltage Range The devices are designed to operate over the 9V (±4.5V) to 40V (±20V) range and are fully characterized at 10V (±5V) and 30V (±15V). The JFET input stage maintains high impedance over a maximum input differential 14 FN6639.1 December 8, 2010 ISL28110, ISL28210 In applications where one or both amplifier input terminals are at risk of exposure to voltages beyond the supply rails, current limiting resistors may be needed at each input terminal (see Figure 41 RIN+, RIN-) to limit current through the power supply ESD diodes to 20mA. V+ RINRIN + Output Drive Capability The complementary bipolar emitter follower output stage features low output impedance (Figure 40) and is capable of substantial current drive over the full temperature range (Figures 27, 28) while driving the output voltage close to the supply rails. The output current is internally limited to approximately ±50mA at +25°C. The amplifiers can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only 1 amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long term reliability. VINVIN+ RL V- Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28110 and ISL28210 are immune to output phase reversal, out to 0.5V beyond the rail (VABS MAX) limit. Beyond these limits, the device is still immune to reversal to 1V beyond the rails but damage to the internal ESD protection diodes can result unless these input currents are limited. FIGURE 41. INPUT ESD DIODE CURRENT LIMITING JFET Input Stage Performance The ISL28110, ISL28210 JFET input stage has the linear gain characteristics of the MOSFET but can operate at high frequency with much lower noise. The reversedbiased gate PN gate junction has significantly lower gate capacitance than the MOSFET, enabling input slew rates that rival op amps using bipolar input stages. The added advantage for high impedance, precision amplifiers is the lack of a significant 1/f component of current noise (Figures 13, 14) as there is virtually no gate current. The input stage JFETs are bootstrapped to maintain a constant JFET drain to source voltage which keeps the JFET gate currents and input stage frequency response nearly constant over the common mode input range of the device. These enhancements provide excellent CMRR, AC performance and very low input distortion over a wide temperature range. The common mode input performance for offset voltage and bias current is shown in Figure 42. Note that the input bias current remains low even after the maximum input stage common mode voltage is exceeded (as indicated by the abrupt change in input offset voltage). NORMALIZED INPUT BIAS CURRENT (pA) Maximizing Dynamic Signal Range The amplifiers maximum undistorted output swing is a figure of merit for precision, low distortion applications. Audio amplifiers are a good example of amplifiers that require low noise and low signal distortion over a wide output dynamic range. When these applications operate from batteries, raising the amplifier supply voltage to overcome poor output voltage swing has the penalty of increased power consumption and shorter battery life. Amplifiers whose input and output stages can swing closest to the power supply rails while providing low noise and undistorted performance, will provide maximum useful dynamic signal range and longer battery life. Rail-to-rail input and output (RRIO) amplifiers have the highest dynamic signal range but their added complexity degrades input noise and amplifier distortion. Many contain two input pairs, one pair operating to each supply rail. The trade-offs for these are increased input noise and distortion caused by non-linear input bias current and capacitance when amplifying high impedance sources. Their rail-to-rail output stages swing to within a few millivolts of the rail, but output impedances are high so that their output swing decreases and distortion increases rapidly with increasing load current. At heavy load currents the maximum output voltage swing of RRO op amps can be lower than a good emitter follower output stage. The ISL28110 and ISL28210 low noise input stage and high performance output stage are optimized for low THD+N into moderate loads over the full -40°C to +125°C temperature range. Figures 19 and 20 show the 1kHz THD+N unity gain performance vs output voltage swing at load resistances of 2kΩ and 600Ω. Figure 43 shows the unity-gain THD+N performance driving 600Ω from ±5V supplies. 10 8 6 4 2 0 -2 -4 -6 -8 -10 -15 -10 -5 0 VCM (V) 5 INPUT BIAS (IB) INPUT OFFSET VOLTAGE (VOS) VS = ±15V T = +25°C 500 400 200 100 0 -100 -200 -300 -400 -500 15 NORMALIZED VOS (uV) 300 10 FIGURE 42. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs COMMON MODE INPUT VOLTAGE 15 FN6639.1 December 8, 2010 ISL28110, ISL28210 1 VS = ±5V RL = 600Ω 0.1 THD+N (%) AV = 1 +125°C 0.01 +85°C +25°C ISL28110 and ISL28210 SPICE Model Figure 44 shows the SPICE model schematic and Figure 45 shows the net list for the SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise voltage, Slew Rate, CMRR, Gain and Phase. The DC parameters are IOS, total supply current and output voltage swing. The model uses typical parameters given in the “Electrical Specifications” Table beginning on page 4. The AVOL is adjusted for 125dB with the dominant pole at 7Hz. The CMRR is set 120dB, f = 280kHz. The input stage models the actual device to present an accurate AC representation. The model is configured for ambient temperature of +25°C. Figures 46 through 59 show the characterization vs simulation results for the Noise Voltage, Closed Loop Gain vs Frequency, Small Signal 0.1V Step, Large Signal 5V Step Response, Open Loop Gain Phase, CMRR and Output Voltage Swing for ±5V and ±15V supplies. LICENSE STATEMENT The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable licence to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. 0.001 0°C -40°C 0.0001 0 1 2 3 4 5 6 VP-P (V) 7 8 9 10 FIGURE 43. UNITY-GAIN THD+N vs OUTPUT VOLTAGE vs TEMPERATURE AT VS = ±5V FOR 600Ω LOAD Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: T JMAX = T MAX + θ JA xPD MAXTOTAL (EQ. 1) where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × --------------------------RL (EQ. 2) where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance 16 FN6639.1 December 8, 2010 C3 6e-12 V++ 0.7Vdc I1 240E-6 0.7Vdc DX V2 V3 D5 G1 + R9 G 22 GAIN = 33 V4 V++ DX D9 V++ 10 R5 5.5k 21 R6 5.5k 9 Vin0.4 V1 PNP_MIRROR Q7 20 11 buffer1 ++ -E buffer2 ++ -E D2 DBREAK PNP_MIRROR Q6 C1 4e-12 1.18 1 D7 R12 1e10 G3 + G Vmid GAIN = 181.819E-6 1.18 26 R13 200k V6 C4 2.5e-12 DX 23 19 C2 4e-12 EOS Vc ++ -E Vmid GAIN = 1 R11 1k 25 Vmid Vg Vg Vmid VC 12 1 DN D1 8 R2 5e11 ++ -- 7 GAIN = 1 Cin2 7.27e-40 PJ110_CASCODE Cin1 7.27e-40 4 J4 15 J3 PJ110_CASCODE DX GAIN = 33 D6 DX G GAIN = 181.819E-6 V-- V-- INPUT STAGE V+ E3 ++ -- GAIN STAGE V++ 0 L1 VCM G5 + G GAIN = 1 E GAIN = 1 L3 5.30532e-10 V++ R19 R21 DX 318.319274232055 318.319274232055 G11 G9 + + G G GAIN = 0.0031415 D11 GAIN = 0.0031415 DX C6 C8 10e-12 10e-12 D14 DX V++ D15 G 5.30532e-10 G7 + 28 G R15 0.001 GAIN = 1 31 R17 0.001 35 V8 .523 G15 Vout GAIN = 20e-3 Vout 29 Vg Vmid VC Vc ISY 33 34 37 38 2.5E-3 D12 R16 0.001 R18 0.001 + G8 + G10 DX DX 36 V9 .523 Vout Vmid C7 10e-12 G6 GAIN = 1 + - R20 318.319274232055 R22 318.319274232055 V-VCM G16 GAIN = 20e-3 V-V- V-V-E4 ++ -E GAIN = 1 COMMON MODE GAIN STAGE WITH ZERO 0 CORRECTION CURRENT OUTPUT STAGE SOURCES FIGURE 44. SPICE NET LIST + - GAIN = 1 L2 5.30532e-10 L4 5.30532e-10 DY GAIN = 0.0031415 GAIN = 0.0031415 + - 30 G12 C9 10e-12 D13 G13 G14 + + G G GAIN = 1.11e-2 GAIN = 1.11e-2 DY D16 Vout G Vout R24 50 32 + - + + - + - 17 0 13 3 NPN_CASCODE CinDif 5.87E-40 R4 IOS 250 0.3E-12 Q4 Q2 NPN_CASCODE D3 DBREAK NPN_CASCODE Q5 Q1 NPN_CASCODE R8 100 D8 1.18 V5 DX 18 17 1.18 V7 110 R1 2 E En 0 R3 5e11 5 pj110_input J1 6 14 J2 16 R7 D4 DBREAK Vin+ PJ110_INPUT 250 24 G2 5 R10 1 Vmid G4 27 C5 R14 200k 2.5e-12 E2 ++ -E GAIN = 0.5 ISL28110, ISL28210 D10 V-VCM MID SUPPLY REF V R23 50 Vout VOUT FN6639.1 December 8, 2010 ISL28110, ISL28210 * source ISL28110_210_presubckt_0 * Revision A, LaFontaine Nov 4th 2010 * Model for Noise 200nV/rtHz@0.1Hx *11nV/rtHz base band, supply current 2.5mA, *CMRR 120dB fcm=281kHz ,AVOL 125dB *fd=7Hz * SR = 20V/us, GBWP 12.6MHz, Output *voltage clamp *Copyright 2010 by Intersil Corporation *Refer to data sheet “LICENSE STATEMENT” *Use of this model indicates your acceptance *with the terms and provisions in the License *Statement. * Connections: * +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | |||| .subckt ISL28110subckt Vin+ Vin- V+ V- VOUT * source ISL28110_210_PRESUBCKT_0 * *Voltage Noise * E_En VIN+ 4 2 0 1 V_V1 1 0 0.4 D_D1 1 2 DN R_R1 2 0 110 * *Input Stage * R_R2 VIN- 3 5e11 R_R3 3 4 5e11 C_CinDif 4 VIN- 5.87E-40 C_Cin1 V-- VIN- 7.27e-40 C_Cin2 V-- 4 7.27e-40 I_IOS 4 VIN- DC 0.3E-12 R_R4 5 VIN- 250 J_J1 7 5 6 pj110_input J_J2 15 16 14 pj110_input J_J3 V-- 14 15 PJ110_CASCODE J_J4 V-- 6 7 PJ110_CASCODE Q_Q1 19 13 14 NPN_CASCODE Q_Q2 12 13 6 NPN_CASCODE Q_Q4 8 13 6 NPN_CASCODE Q_Q5 12 13 14 NPN_CASCODE Q_Q6 19 11 20 PNP_MIRROR Q_Q7 8 11 9 PNP_MIRROR V_V2 V++ 10 0.7Vdc V_V3 V++ 21 0.7Vdc R_R5 9 10 5.5k R_R6 20 21 5.5k E_buffer1 11 V++ 8 V++ 1 E_buffer2 13 V-- 12 V-- 1 D_D2 8 19 DBREAK D_D3 19 8 DBREAK I_I1 V++ 12 DC 240E-6 C_C1 19 V++ 4e-12 C_C2 V-- 19 4e-12 R_R7 16 17 250 E_EOS 17 4 VC VMID 1 * *1st Gain Stage * R_R8 18 V++ 100 D_D4 V-- 18 DBREAK D_D5 22 V++ DX D_D6 V-- 24 DX V_V4 22 23 1.18 V_V5 23 24 1.18 G_G1 V++ 23 19 8 33 G_G2 V-- 23 19 8 33 R_R9 23 V++ 1 R_R10 V-- 23 1 R_R11 25 23 1k D_D7 25 VMID DX D_D8 VMID 25 DX R_R12 25 VMID 1e10 G_G3 V++ VG 25 VMID 181.819E-6 G_G4 V-- VG 25 VMID 181.819E-6 D_D9 26 V++ DX D_D10 V-- 27 DX V_V6 26 VG 1.18 V_V7 VG 27 1.18 R_R13 VG V++ 200k R_R14 V-- VG 200k C_C3 8 VG 6e-12 C_C4 VG V++ 2.5e-12 C_C5 V-- VG 2.5e-12 * * Mid Supply Reference * E_E2 VMID V-- V++ V-- 0.5 E_E3 V++ 0 V+ 0 1 E_E4 V-- 0 V- 0 1 I_ISY V+ V- DC 2.5E-3 * *Common Mode Gain Stage 40dB/dec * G_G5 V++ 29 3 VMID 1 G_G6 V-- 29 3 VMID 1 G_G7 V++ VC 29 VMID 1 G_G8 V-- VC 29 VMID 1 L_L1 28 V++ 5.30532e-11 L_L2 30 V-- 5.30532e-11 L_L3 31 V++ 5.30532e-11 L_L4 32 V-- 5.30532e-11 R_R15 29 28 0.001 R_R16 30 29 0.001 R_R17 VC 31 0.001 R_R18 32 VC 0.001 * *Second Pole Stage 40dB/dec * G_G9 V++ 33 VG VMID 0.0031415 G_G10 V-- 33 VG VMID 0.0031415 G_G11 V++ 34 33 VMID 0.0031415 G_G12 V-- 34 33 VMID 0.0031415 R_R19 33 V++ 318.319274232055 R_R20 V-- 33 318.319274232055 R_R21 34 V++ 318.319274232055 R_R22 V-- 34 318.319274232055 C_C6 33 V++ 10e-12 C_C7 V-- 33 10e-12 C_C8 34 V++ 10e-12 C_C9 V-- 34 10e-12 * * Output Stage * D_D11 34 35 DX D_D12 36 34 DX D_D13 V-- 37 DY D_D14 V++ 37 DX D_D15 V++ 38 DX D_D16 V-- 38 DY G_G13 37 V-- VOUT 34 1.11e-2 G_G14 38 V-- 34 VOUT 1.11e-2 G_G15 VOUT V++ V++ 34 20e-3 G_G16 V-- VOUT 34 V-- 20e-3 V_V8 35 VOUT -.384 V_V9 VOUT 36 -.384 R_R23 VOUT V++ 50 R_R24 V-- VOUT 50 * * .model pj110_input pjf + vto=-1.4 + beta=0.0025 + lambda=0.03 + is=2.68e-015 + pb=0.73 + cgd=8.6e-012 + cgs=9.05e-012 + fc=0.5 kf=0 + af=1 + tnom=35 * .model NPN_CASCODE npn + is=5.02e-016 + bf=150 + va=300 + ik=0.017 + rb=0.01 + re=0.011 + rc=900 + cje=2e-013 + cjc=1.6e-028 + kf=0 + af=1 * .model PJ110_CASCODE pjf + vto=-1.4 + beta=0.000617 + lambda=0.03 + is=3.96e-016 + pb=0.73 + cgd=2.2e-012 + cgs=3e-012 + fc=0.5 + kf=0 + af=1 + tnom=35 * .model DBREAK d + bv=43 + rs=1 * .model PNP_MIRROR pnp + is=4e-015 + bf=150 + va=50 + ik=0.138 + rb=0.01 + re=0.101 + rc=180 + cje=1.34e-012 + cjc=4.4e-013 + kf=0 + af=1 * .model DN D(KF=6.69e-12 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28110subckt FIGURE 45. SPICE NET LIST 18 FN6639.1 December 8, 2010 ISL28110, ISL28210 Characterization vs Simulation Results 1000 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) VS = ±18V 1000 1000 VS = ±18V 100 INPUT NOISE VOLTAGE 100 INPUT NOISE VOLTAGE 100 10 10 1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 1 100k 10 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k FIGURE 46. CHARACTERIZED INPUT NOISE VOLTAGE FIGURE 47. SIMULATED INPUT NOISE VOLTAGE 70 60 50 GAIN (dB) 70 ACL = 1000 RF = 100kΩ, RG = 100Ω RF = 100kΩ, RG = 1kΩ GAIN (dB) 60 50 40 30 20 10 0 ACL = 1000 RF = 100kΩ, RG = 100Ω RF = 100kΩ, RG = 1kΩ 40 30 20 10 0 ACL = 100 ACL = 10 RF = 100kΩ, RG = 10kΩ ACL = 1 RF = 0, RG = ∞ 10k 100k 1M VS = ±5V & ±15V CL = 4pF RL = OPEN VOUT = 100mVP-P ACL = 100 ACL = 10 RF = 100kΩ, RG = 10kΩ ACL = 1 RF = 0, RG = ∞ 10k 100k 1M VS = ±5V & ±15V CL = 4pF RL = OPEN VOUT = 100mVP-P -10 1k 10M 100M -10 1k 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 48. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY FIGURE 49. SIMULATED CLOSED LOOP GAIN vs FREQUENCY 0.15 0.10 0.05 VOUT (V) 0.15 VS = ±15V AV = 1 RL = 2k CL = 4pF VOUT (V) VS = ±15V 0.10 AV = 1 RL = 2k CL = 4pF 0.05 0 -0.05 -0.10 -0.15 0 0 -0.05 -0.10 -0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.2 0.4 0.6 0.8 1.0 TIME (µs) TIME (µs) FIGURE 50. CHARACTERIZED SMALL SIGNAL TRANSIENT RESPONSE vs RL, VS = ±0.9V, ±2.5V FIGURE 51. SIMULATED SMALL SIGNAL TRANSIENT RESPONSE vs RL, VS = ±0.9V, ±2.5V 19 FN6639.1 December 8, 2010 ISL28110, ISL28210 Characterization vs Simulation Results (Continued) 6 4 2 VOUT (V) 6 VS = ±15V AV = 1 RL = 2k CL = 4pF VOUT (V) 4 2 0 -2 -4 -6 VS = ±15V AV = 1 RL = 2k CL = 4pF 0 -2 -4 -6 0 1 2 3 4 5 TIME (µs) 6 7 8 9 10 0 2 4 TIME (µs) 6 8 10 FIGURE 52. CHARACTERIZED LARGE SIGNAL TRANSIENT RESPONSE vs RL, VS = ±0.9V, ±2.5V FIGURE 53. SIMULATED LARGE SIGNAL TRANSIENT RESPONSE vs RL, VS = ±0.9V, ±2.5V 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL=1MΩ -100 0.1 1 10 PHASE GAIN 100 1k 10k 100k 1M 10M 100M 1G 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL=1MΩ -100 0.1 1 10 PHASE GAIN (dB) GAIN (dB) GAIN 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 54. SIMULATED (DESIGN) OPEN-LOOP GAIN, PHASE vs FREQUENCY FIGURE 55. SIMULATED (SPICE) OPEN-LOOP GAIN, PHASE vs FREQUENCY 130 120 110 100 90 80 70 60 50 40 30 20 VS = ±15V 10 SIMULATION 0 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M 130 120 110 100 90 80 70 60 50 40 30 20 VS = ±15V 10 SIMULATION 0 0.1 1 10 CMRR (dB) CMRR (dB) 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M FIGURE 56. SIMULATED (DESIGN) CMRR FIGURE 57. SIMULATED (SPICE) CMRR 20 FN6639.1 December 8, 2010 ISL28110, ISL28210 Characterization vs Simulation Results (Continued) 5.0 OUTPUT VOLTAGE SWING (V) 15V 10V 5V 0 0V -5V VS = ±5V -10V -15V 0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0 TIME (m s) TIME (m s) -5.0 FIGURE 58. SIMULATED OUTPUT VOLTAGE SWING ±5V FIGURE 59. SIMULATED OUTPUT VOLTAGE SWING ±15V 21 FN6639.1 December 8, 2010 ISL28110, ISL28210 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 11/29/10 11/23/10 REVISION FN6639.1 CHANGE Removed label on right side of characterization curve, Figure 46 (Input Noise Current). Page 1 Updated Trademark statement Page 3 Ordering Information: Removed "coming soon" from ISL28110FBZ Page 4 Electrical Specifications: Added ISL28110 IB and IOS specs @ VS=±5V. Page 5 Electrical Specifications: Changed AVOL limits fro V/mV to dB Page 5 Electrical Specifications, Dynamic Performance, Slew Rate: Added "4V Step" to conditions; changed TYP limit from 23V/µs to 20V/µs Page 6 Electrical Specifications, Dynamic Performance, Slew Rate: Added "10V Step" to conditions; changed TYP limit from 23V/µs to 20V/µs Page 6 Electrical Specifications: Added ISL28110 IB and IOS specs @ VS= ±15V. Changed AVOL limits from V/mV to dB. Changed ts, settling time to 0.1% from 0.9µs to 1.3µs and changed ts, settling time to 0.01% from 1.2µs to 1.6µs. Page 7 Replaced Elect Spec table Notes 8 & 9 (Note 8 "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested./Note 9 Limits established by characterization and are not production tested.)" With: "Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." Page 8 Characteristic Curves: Added ISL28110 IB vs Temperature (Fig 4) Page 8 Characteristic Curves: Added ISL28110 IOS vs Temperature (Fig 6) Pages 17-21: Added PSPICE model section FN6639.0 Initial Release. 9/13/10 Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28110, ISL28210 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 FN6639.1 December 8, 2010 ISL28110, ISL28210 Package Outline Drawing L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 ( 2.30) 3.00 A B ( 1.95) ( 8X 0.50) 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW PIN 1 (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN (1.50) ( 2.90 ) SEE DETAIL "X" 2X 1.950 6X 0.65 PIN #1 INDEX AREA 6 1.50 ±0.10 1 SIDE VIEW 0.75 ±0.05 0.10 C C 0.08 C 8 8X 0.30 ± 0.10 2.30 ±0.10 BOTTOM VIEW 8X 0.30 ±0.05 0.10 M C A B 4 C 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. DETAIL "X" NOTES: 1. 2. 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length. 23 FN6639.1 December 8, 2010 ISL28110, ISL28210 Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10 3.0±0.05 A 8 D 1.10 MAX 5 DETAIL "X" SIDE VIEW 2 3.0±0.05 5 4.9±0.15 0.09 - 0.20 PIN# 1 ID 1 2 B 0.65 BSC TOP VIEW 0.95 REF GAUGE PLANE 0.25 0.55 ± 0.15 H 0.85±010 DETAIL "X" C SEATING PLANE 0.25 - 0.036 0.08 M C A-B D SIDE VIEW 1 0.10 ± 0.05 0.10 C 3°±3° (5.80) (4.40) (3.00) NOTES: 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN 24 FN6639.1 December 8, 2010 ISL28110, ISL28210 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 1.27 0.43 ± 0.076 0.25 M C A B 4° ± 4° TOP VIEW SIDE VIEW “B” 1.75 MAX 1.45 ± 0.1 0.25 0.175 ± 0.075 GAUGE PLANE C SEATING PLANE 0.10 C SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. 6. The pin #1 identifier may be either a mold or mark feature. Reference to JEDEC MS-012. 2. (5.40) 3. 4. TYPICAL RECOMMENDED LAND PATTERN 25 FN6639.1 December 8, 2010