KK74LV374N

TECHNICAL DATA KK74LV374 Octal D-type transparent latch; 3-state The KK74LV374 is a low-voltage Si-gate CMOS devise and is pin and function compatible with 74HCT374. The KK74LV374 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. • • • • Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 1.2 to 3.6 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION KK74LV374N Plastic KK74LV374DW SOIC TA = -40° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT OE 01 20 D0 D1 D2 D3 D4 D5 D6 D7 CP 03 04 07 08 13 14 17 18 11 02 05 06 09 12 15 16 19 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 02 D0 03 D1 04 19 Q7 D7 D6 Q6 Q5 D5 D4 18 17 Q1 05 16 374 15 14 Q2 06 D2 07 D3 08 Q3 09 GND 10 13 12 Q4 11 CP OE 01 FUNCTION TABLE PIN 20=VCC PIN 10 = GND Inputs OE L L L L, H, Output Dn H L CP Qn H L X X Q0 Z H X X = Don’t care Z = High impedance OFF-state L = Low voltage level H= HIGH voltage level 1 KK74LV374 MAXIMUM RATINGS* Symbol VCC IIK* Io* 1 2 Parameter DC supply voltage DC input diode current DC output diode current DC output source or sink current -bus driver outputs DC VCC or GND current for types with - bus driver outputs DC VCC or GND current for types with - bus driver outputs Power dissipation per paskade, plastic DIP+ SOIC package+ Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) Value -0.5 to +5.0 ±20 ±50 ±35 ±70 ±70 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW °C °C IOK* 3 IGND ICC PD Tstg TL * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SOIC Package: : - 8 mW/°C from 70° to 125°C *1: VI < -0.5 or VI > VCC+0.5V *2: Vo < -0.5 or Vo > VCC+0.5V *3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf DC Supply Voltage DC Input Voltage, Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Parameter Min 1.2 0 -40 0 0 0 Max 3.6 VCC +125 1000 700 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74LV374 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions V , CC В 25° C Guaranteed Limit -40°C tо -40°C tо 85° C 125°C min max min max min max 0.9 1.4 2.1 2.5 1.1 1.92 2.92 3.52 2.48 0.3 0.6 0.9 1.1 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.34 0.3 0.6 0.9 1.1 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.20 0.3 0.6 0.9 1.1 В Unit VIH HIGH level input VO = VCC-0.1 В voltage 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 3.0 VIL LOW level input VO =0.1 В voltage В VOH HIGH level VI = VIH or VIL output voltage; all IO = -50 мкА outputs HIGH level VI = VIH or VIL output voltage; IO = -8.0 мА bus driver outputs В B VOL LOW-level output VI = VIH or VIL voltage; all IO = 50 мкА outputs LOW-level output VI = VIH or VIL voltage; bus IO = 8.0 мА driver outputs 1.2 2.0 3.0 3.6 3.0 - 0.09 0.09 0.09 0.09 0.33 - 0.1 0.1 0.1 0.1 0.4 - 0.1 0.1 0.1 0.1 0.5 B B IIN IOZ Input leakage current VI = VCC or GND 3.6 1.2 3.6 3.6 - ±0.1 ±0.5 - ±1.0 ±5 - ±1.0 ±10 мкА мкА 3-state output VI = VIL or VIH OFF-state current VO =VCC or GND Guiescent supply VI =VCC or 0 B current; MSI IO = 0 мкА ICC - 8.0 - 80 - 160 мкА 3 KK74LV374 AC ELECTRICAL CHARACTERISTICS (CL=50 пФ, tLH = tHL = 6.0 нс, VIL=0B, VIH=VCC) Symbol Parameter VCC V 25° C min tPHL,tPLH Propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn Output transition time Clock pulse width HING or LOW Set-up time Dn to CP Hold time Dn to CP Maxsimum clock pulse freguency Input capacitance Power dissipation capacitance per latch 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 3.0 3.0 250 18 11 45 13 8 25 5 5 27 46 7.0 max 180 45 27 160 38 25 160 38 23 75 16 10 Guaranteed Limit -40°C tо 85° C max min 350 23 14 50 17 10 25 5 5 22 37 7.0 230 56 34 200 57 36 200 48 49 100 20 13 -40°C tо 125°C min 540 28 17 100 20 12 25 5 5 18 31 7.0 pF pF max 270 68 35 240 68 43 240 58 35 120 24 15 ns Unit tPZH, tPZL tPHZ, tPLZ tTHL, tTLH tW tSU tH fc CI CPD Typical @25°C,VCC=3.0 V 34 Used to determine the no-load dynamic power consumption: PD=CPDV2CCfi + ∑(CLV2CCf0) where: fI = input freguercy in MHz; CL= output load capacity in pF; f0= output freguercy in MHz; VCC = supply voltage in V; ∑(CLV2CCf0) = sum of outputs. 4 KK74LV374 t LH 0.9 VCC VCC CP 0.1 V1 V1 V1 GND Dn tW V1 V1 V1 V1 GND 1/fc t PHL t PLH 0.9 V1 0.9 V1 0.1 CP t SU tH t SU tH VCC V1 V1 Qn 0.1 0B GND V 1 = 0.5V CC t TLH V1 = 0.5V CC t THL Figure 1. Switching Waveforms Figure 2. Switching Waveforms tLH t HL VCC 0.9 OE 0.9 V1 0.1 GND VOH V1 0.1 t PZH 0.9 t PHZ Qn V1 0B t PLZ Qn VCC V1 t PZL 0.1 VOL V1 = 0.5V CC Figure 3. Switching Waveforms EXPANDED LOGIC DIAGRAM 5 KK74LV374 N S UFFIX PLAS TIC DIP (MS - 0 0 1 AD) A Dimens ion, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING N G D 0.25 (0.010) M T K PLAN E G H H J M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 3 AC) A 20 11 Dimens ion, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0° 0.1 0.23 10 0.25 8° 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SE AT IN G PL AN E J F M G H J K M P R NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p ro tru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 6