LT3758EDDTRPBF

FEATURES n n n n n n n n n n n LT3758 High Input Voltage, Boost, Flyback, SEPIC and Inverting Controller DESCRIPTION The LT®3758 is a wide input range, current mode, DC/DC controller which is capable of generating either positive or negative output voltages. It can be configured as either a boost, flyback, SEPIC or inverting converter. The LT3758 drives a low side external N-channel power MOSFET from an internal regulated 7.2V supply. The fixed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. The operating frequency of LT3758 can be set with an external resistor over a 100kHz to 1MHz range, and can be synchronized to an external clock using the SYNC pin. A minimum operating supply voltage of 5.5V, and a low shutdown quiescent current of less than 1μA, make the LT3758 ideally suited for battery-powered systems. The LT3758 features soft-start and frequency foldback functions to limit inductor current during start-up and output short-circuit. The device is available in a small 10-lead DFN (3mm × 3mm) or MSOPE package. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents pending. Wide Input Voltage Range: 5.5V to 100V Positive or Negative Output Voltage Programming with a Single Feedback Pin Current Mode Control Provides Excellent Transient Response Programmable Operating Frequency (100kHz to 1MHz) with One External Resistor Synchronizeable to an External Clock Output Overvoltage Protection Low Shutdown Current < 1μA Internal 7.2V Low Dropout Voltage Regulator Programmable Input Undervoltage Lockout with Hysteresis Programmable Soft-Start Small 10-Lead DFN (3mm × 3mm) and MSOPE Packages APPLICATIONS n n n Automotive Telecom Industrial TYPICAL APPLICATION 12V Output Nonisolated Flyback Power Supply VIN 36V TO 72V D1 CIN 2.2μF 100V X7R 0.022μF 100V VIN SHDN/UVLO 44.2k SYNC RT SS 63.4k 200kHz 0.47μF 100pF 10k 10nF CVCC 4.7μF 10V X5R 0.030Ω 15.8k 1% COUT 47μF X5R VC VOUT 12V 1.2A 6.2k T1 1,2,3 (SERIES) DSN SW GATE SENSE FBX GND INTVCC M1 105k 1% 4,5,6 (PARALLEL) 1M LT3758 1N4148 5.1Ω 3758 TA01 3758f 1 LT3758 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN, SHDN/UVLO .....................................................100V INTVCC .................................................... VIN + 0.3V, 20V GATE .........................................................INTVCC + 0.3V SYNC ..........................................................................8V VC, SS.........................................................................3V RT ............................................................................................... 1.5V SENSE....................................................................±0.3V FBX ................................................................. –6V to 6V Operating Temperature Range (Note 2) ............................................. –40°C to 125°C Maximum Junction Temperature........................... 125°C Storage Temperature Range................... –65°C to 125°C PIN CONFIGURATION TOP VIEW VC FBX SS RT SYNC 1 2 3 4 5 11 10 VIN 9 SHDN/UVLO 8 INTVCC 7 GATE 6 SENSE TOP VIEW VC FBX SS RT SYNC 1 2 3 4 5 10 9 8 7 6 VIN SHDN/UVLO INTVCC GATE SENSE 11 DD PACKAGE 10-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 40°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LT3758EDD#PBF LT3758IDD#PBF LT3758EMSE#PBF LT3758IMSE #PBF TAPE AND REEL LT3758EDD#TRPBF LT3758IDD#TRPBF LT3758EMSE#TRPBF LT3758IMSE#TRPBF PART MARKING* LDNK LDNK LTDNM LTDNM PACKAGE DESCRIPTION 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic MSOP 10-Lead (3mm × 3mm) Plastic MSOP TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3758f 2 LT3758 ELECTRICAL CHARACTERISTICS PARAMETER VIN Operating Range VIN Shutdown IQ VIN Operating IQ VIN Operating IQ with Internal LDO Disabled SENSE Current Limit Threshold SENSE Input Bias Current Error Amplifier FBX Regulation Voltage (VFBX(REG)) FBX Overvoltage Lockout FBX Pin Input Current Transconductance gm (ΔIVC /ΔFBX) VC Output Impedance VFBX Line Regulation (ΔVFBX /[ΔVIN • VFBX(REG)]) VC Current Mode Gain (ΔVVC /ΔVSENSE) VC Source Current VC Sink Current Oscillator Switching Frequency RT = 41.2k to GND, FBX = 1.6V RT = 140k to GND, FBX = 1.6V RT = 10.5k to GND, FBX = 1.6V FBX = 1.6V 270 300 100 1000 1.2 220 220 0.4 1.5 SS = 0V, Current Out of Pin l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted. CONDITIONS SHDN/UVLO = 0V SHDN/UVLO = 1.15V VC = 0.3V, RT = 41.2k VC = 0.3V, RT = 41.2k, INTVCC = 7.5V l MIN 5.5 TYP 0.1 1.6 350 MAX 100 1 6 2.2 400 120 UNITS V μA μA mA μA mV μA 100 110 –65 Current Out of Pin FBX > 0V (Note 3) FBX < 0V (Note 3) FBX > 0V (Note 4) FBX < 0V (Note 4) FBX = 1.6V (Note 3) FBX = –0.8V (Note 3) (Note 3) (Note 3) FBX > 0V, 5.5V < VIN < 100V (Notes 3, 6) FBX < 0V, 5.5V < VIN < 100V (Notes 3, 6) VC = 1.5V FBX = 1.7V FBX = –0.85V l l 1.569 –0.816 6 7 –10 1.6 –0.800 8 11 70 230 5 0.006 0.005 5.5 –15 12 11 1.631 –0.784 10 14 100 10 V V % % nA nA μS MΩ 0.025 0.03 %/V %/V V/V μA μA μA 330 kHz kHz kHz V ns ns RT Voltage Minimum Off-Time Minimum On-Time SYNC Input Low SYNC Input High SS Pull-Up Current Low Dropout Regulator INTVCC Regulation Voltage INTVCC Undervoltage Lockout Threshold INTVCC Overvoltage Lockout Threshold INTVCC Current Limit INTVCC Load Regulation (ΔVINTVCC / VINTVCC) INTVCC Line Regulation (ΔVINTVCC / [ΔVIN • VINTVCC]) Dropout Voltage (VIN – VINTVCC) –10 7 4.3 7.2 4.5 0.5 17.5 16 50 –0.4 0.005 500 0.02 7.4 4.7 μA V V V V 22 mA mA % %/V mV Falling INTVCC UVLO Hysteresis VIN = 100V VIN = 20V 0 < IINTVCC < 10mA, VIN = 8V 8V < VIN < 100V VIN = 6V, IINTVCC = 10mA 11 –1 3758f 3 LT3758 ELECTRICAL CHARACTERISTICS PARAMETER INTVCC Current in Shutdown INTVCC Voltage to Bypass Internal LDO Logic Inputs SHDN/UVLO Threshold Voltage Falling SHDN/UVLO Input Low Voltage SHDN/UVLO Pin Bias Current Low SHDN/UVLO Pin Bias Current High Gate Driver t r Gate Driver Output Rise Time t f Gate Driver Output Fall Time Gate Output Low (VOL) Gate Output High (VOH) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3758E is guaranteed to meet performance specifications from the 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The INTVCC –0.05 CL = 3300pF (Note 5), INTVCC = 7.5V CL = 3300pF (Note 5), INTVCC = 7.5V 22 20 0.05 ns ns V V VIN = INTVCC = 8V IVIN Drops Below 1μA SHDN/UVLO = 1.15V SHDN/UVLO = 1.33V 1.7 2 10 l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted. CONDITIONS SHDN/UVLO = 0V, INTVCC = 8V MIN TYP 16 7.5 1.17 1.22 1.27 0.4 2.5 100 MAX UNITS μA V V V μA nA LT3758I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: The LT3758 is tested in a feedback loop which servos VFBX to the reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V. Note 4: FBX overvoltage lockout is measured at VFBX(OVERVOLTAGE) relative to regulated VFBX(REG). Note 5: Rise and fall times are measured at 10% and 90% levels. Note 6: SHDN/UVLO = 1.33V when VIN = 5.5V. 3758f 4 LT3758 TYPICAL PERFORMANCE CHARACTERISTICS Positive Feedback Voltage vs Temperature, VIN 1.604 1.602 1.600 1.598 VIN = 8V 1.596 1.594 VIN = INTVCC = 5.5V 1.592 1.590 –50 REGULATED FEEDBACK VOLTAGE (mV) REGULATED FEEDBACK VOLTAGE (V) VIN = 100V –792 –794 –796 –798 –800 –802 –804 –50 VIN = 24V VIN = 100V VIN = INTVCC = 5.5V VIN = 8V TA = 25°C, unless otherwise noted. Negative Feedback Voltage vs Temperature, VIN VIN = 24V –25 50 25 0 75 TEMPERATURE (°C) 100 125 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3758 G01 3758 G02 Quiescent Current vs Temperature, VIN 1.8 35 30 25 VIN = 24V 1.6 VIN = INTVCC = 5.5V 1.5 IQ(mA) 20 15 10 5 1.4 –50 0 Dynamic Quiescent Current vs Switching Frequency CGATE = 3300pF QUIESCENT CURRENT (mA) VIN = 100V 1.7 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) 3758 G04 3758 G03 RT vs Switching Frequency 1000 120 100 80 60 40 20 Normalized Switching Frequency vs FBX 100 NORMALIZED FREQUENCY (%) RT (kΩ) 10 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) 3758 G05 0 –0.8 –0.4 0 0.4 0.8 FBX VOLTAGE (V) 1.2 1.6 3758 G06 3758f 5 LT3758 TYPICAL PERFORMANCE CHARACTERISTICS Switching Frequency vs Temperature 325 320 SWITCHING FREQUENCY (kHz) 315 310 305 300 295 290 285 280 275 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 95 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 RT = 41.2k 120 TA = 25°C, unless otherwise noted. SENSE Current Limit Threshold vs Temperature SENSE THRESHOLD (mV) 115 110 105 100 3758 G07 3758 G08 SENSE Current Limit Threshold vs Duty Cycle 115 1.28 SHDN/UVLO Threshold vs Temperature SENSE THRESHOLD (mV) 110 SHDN/UVLO VOLTAGE (V) 1.26 SHDN/UVLO RISING 1.24 SHDN/UVLO FALLING 105 1.22 100 1.20 95 0 20 40 60 DUTY CYCLE (%) 80 100 3758 G09 1.18 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3758 G10 SHDN/UVLO Current vs Voltage 50 2.4 SHDN/UVLO Hysteresis Current vs Temperature SHDN/UVLO CURRENT (μA) 40 2.2 30 ISHDN /UVLO (μA) 2.0 20 10 1.8 0 0 20 40 60 80 SHDN/UVLO VOLTAGE (V) 100 3758 G11 1.6 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3758 G12 3758f 6 LT3758 TYPICAL PERFORMANCE CHARACTERISTICS INTVCC vs Temperature 7.4 45 40 7.3 INTVCC (V) INTVCC CURRENT (mA) 35 30 25 20 15 10 5 7.0 –50 0 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1 10 VIN (V) 100 3758 G14 TA = 25°C, unless otherwise noted. INTVCC Minimum Output Current vs VIN TJ = 125°C 7.2 INTVCC = 4.7V 7.1 INTVCC = 6V 3758 G13 INTVCC Load Regulation 7.3 VIN = 8V 7.2 INTVCC VOLTAGE (V) INTVCC VOLTAGE (V) 7.25 7.30 INTVCC Line Regulation 7.1 7.20 7 7.15 6.9 6.8 0 5 15 10 INTVCC LOAD (mA) 20 25 3758 G15 7.10 0 10 20 30 40 50 60 70 80 90 100 VIN (V) 3758 G16 INTVCC Dropout Voltage vs Current, Temperature 900 800 DROPOUT VOLTAGE (mV) 700 600 500 400 300 200 100 0 0 2 4 6 8 10 3758 G17 125°C 75°C 25°C 0°C –50°C INTVCC LOAD (mA) 3758f 7 LT3758 TYPICAL PERFORMANCE CHARACTERISTICS Gate Drive Rise and Fall Time vs CL 90 80 25 70 60 TIME (ns) 50 40 30 20 5 10 0 0 5 10 15 CL (nF) 3758 G18 TA = 25°C, unless otherwise noted. Gate Drive Rise and Fall Time vs INTVCC 30 CL = 3300pF RISE TIME INTVCC = 7.2V 20 TIME (ns) RISE TIME FALL TIME FALL TIME 15 10 20 25 30 0 3 6 9 INTVCC (V) 3758 G19 12 15 Typical Start-Up Waveforms VIN = 48V VOUT 20V/DIV VOUT 10V/DIV VSW 50V/DIV FBX Frequency Foldback Waveforms During Overcurrent VIN = 48V IL1A + IL1B 1A/DIV 2ms/DIV 3758 G20 IL1A + IL1B 2A/DIV 50μs/DIV 3758 G21 SEE TYPICAL APPLICATION: 18V TO 72V INPUT, 24V OUTPUT SEPIC CONVERTER SEE TYPICAL APPLICATION: 18V TO 72V INPUT, 24V OUTPUT SEPIC CONVERTER 3758f 8 LT3758 PIN FUNCTIONS VC (Pin 1): Error Amplifier Compensation Pin. Used to stabilize the voltage loop with an external RC network. FBX (Pin 2): Positive and Negative Feedback Pin. Receives the feedback voltage from the external resistor divider across the output. Also modulates the switching frequency during start-up and fault conditions when FBX is close to GND. SS (Pin 3): Soft-Start Pin. This pin modulates compensation pin voltage (VC) clamp. The soft-start interval is set with an external capacitor. The pin has a 10μA (typical) pull-up current source to an internal 2.5V rail. The softstart pin is reset to GND by an undervoltage condition at SHDN/UVLO, an INTVCC undervoltage or overvoltage condition or an internal thermal lockout. RT (Pin 4): Switching Frequency Adjustment Pin. Set the frequency using a resistor to GND. Do not leave this pin open. SYNC (Pin 5): Frequency Synchronization Pin. Used to synchronize the switching frequency to an outside clock. If this feature is used, an RT resistor should be chosen to program a switching frequency 20% slower than the SYNC pulse frequency. Tie the SYNC pin to GND if this feature is not used. SYNC is ignored when FBX is close to GND. SENSE (Pin 6): The Current Sense Input for the Control Loop. Kelvin connect this pin to the positive terminal of the switch current sense resistor in the source of the NFET. The negative terminal of the current sense resistor should be connected to GND plane close to the IC. GATE (Pin 7): N-Channel MOSFET Gate Driver Output. Switches between INTVCC and GND. Driven to GND when IC is shut down, during thermal lockout or when INTVCC is above or below the overvoltage or UV thresholds, respectively. INTVCC (Pin 8): Regulated Supply for Internal Loads and Gate Driver. Supplied from VIN and regulated to 7.2V (typical). INTVCC must be bypassed with a minimum of 4.7μF capacitor placed close to pin. INTVCC can be connected directly to VIN, if VIN is less than 17.5V. INTVCC can also be connected to a power supply whose voltage is higher than 7.5V, and lower than VIN, provided that supply does not exceed 17.5V. SHDN/UVLO (Pin 9): Shutdown and Undervoltage Detect Pin. An accurate 1.22V (nominal) falling threshold with externally programmable hysteresis detects when power is okay to enable switching. Rising hysteresis is generated by the external resistor divider and an accurate internal 2μA pull-down current. An undervoltage condition resets sort-start. Tie to 0.4V, or less, to disable the device and reduce VIN quiescent current below 1μA. VIN (Pin 10): Input Supply Pin. Must be locally bypassed with a 0.22μF or larger, capacitor placed close to the , pin. Exposed Pad (Pin 11): Ground. This pin also serves as the negative terminal of the current sense resistor. The Exposed Pad must be soldered directly to the local ground plane. 3758f 9 LT3758 BLOCK DIAGRAM L1 VIN R4 R3 CDC D1 VOUT L2 • + CIN • 9 SHDN/UVLO A10 2.5V IS3 VC 1 CC2 RC CC1 1.72V IS1 2μA 2.5V IS2 10μA Q3 G4 A11 G3 INTERNAL REGULATOR AND UVLO UVLO 10 VIN R2 + COUT1 FBX R1 COUT2 – + 1.22V + A9 – A8 17.5V CURRENT LIMIT 7.2V LDO INTVCC 8 CVCC – + – + TSD 165˚C G6 VC + – 5V UP 4.5V DOWN DRIVER SR1 GATE O S G2 7 M1 –0.88V Q2 PWM COMPARATOR A6 SLOPE RAMP RAMP GENERATOR VISENSE 1.6V FBX FBX 2 + A1 – + A2 – –0.8V FREQUENCY FOLDBACK SS 3 CSS 5 Figure 1. LT3758 Block Diagram Working as a SEPIC Converter 10 + – 1.25V A3 1.25V SYNC 4 + – A12 A7 G5 R – + 110mV SENSE + A5 – 6 GND 11 RSENSE G1 100kHz-1MHz OSCILLATOR + + – A4 FREQ PROG Q1 RT 3758 F01 RT 3758f LT3758 APPLICATIONS INFORMATION Main Control Loop The LT3758 uses a fixed frequency, current mode control scheme to provide excellent line and load regulation. Operation can be best understood by referring to the Block Diagram in Figure 1. The start of each oscillator cycle sets the SR latch (SR1) and turns on the external power MOSFET switch M1 through driver G2. The switch current flows through the external current sensing resistor RSENSE and generates a voltage proportional to the switch current. This current sense voltage VISENSE (amplified by A5) is added to a stabilizing slope compensation ramp and the resulting sum (SLOPE) is fed into the positive terminal of the PWM comparator A7. When SLOPE exceeds the level at the negative input of A7 (VC pin), SR1 is reset, turning off the power switch. The level at the negative input of A7 is set by the error amplifier A1 (or A2) and is an amplified version of the difference between the feedback voltage (FBX pin) and the reference voltage (1.6V or –0.8V, depending on the configuration). In this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. The LT3758 has a switch current limit function. The current sense voltage is input to the current limit comparator A6. If the SENSE pin voltage is higher than the sense current limit threshold VSENSE(MAX) (110mV, typical), A6 will reset SR1 and turn off M1 immediately. The LT3758 is capable of generating either positive or negative output voltage with a single FBX pin. It can be configured as a boost, flyback or SEPIC converter to generate positive output voltage, or as an inverting converter to generate negative output voltage. When configured as a SEPIC converter, as shown in Figure 1, the FBX pin is pulled up to the internal bias voltage of 1.6V by a voltage divider (R1 and R2) connected from VOUT to GND. Comparator A2 becomes inactive and comparator A1 performs the inverting amplification from FBX to VC. When the LT3758 is in an inverting configuration, the FBX pin is pulled down to –0.8V by a voltage divider connected from VOUT to GND. Comparator A1 becomes inactive and comparator A2 performs the noninverting amplification from FBX to VC. The LT3758 has overvoltage protection functions to protect the converter from excessive output voltage overshoot during start-up or recovery from a short-circuit condition. An overvoltage comparator A11 (with 20mV hysteresis) senses when the FBX pin voltage exceeds the positive regulated voltage (1.6V) by 8% and provides a reset pulse. Similarly, an overvoltage comparator A12 (with 10mV hysteresis) senses when the FBX pin voltage exceeds the negative regulated voltage (–0.8V) by 11% and provides a reset pulse. Both reset pulses are sent to the main RS latch (SR1) through G6 and G5. The power MOSFET switch M1 is actively held off for the duration of an output overvoltage condition. Programming Turn-On and Turn-Off Thresholds with the SHDN/UVLO Pin The SHDN/UVLO pin controls whether the LT3758 is enabled or is in shutdown state. A micropower 1.22V reference, a comparator A10 and a controllable current source IS1 allow the user to accurately program the supply voltage at which the IC turns on and off. The falling value can be accurately set by the resistor dividers R3 and R4. When SHDN/UVLO is above 0.7V, and below the 1.22V threshold, the small pull-down current source IS1 (typical 2μA) is active. The purpose of this current is to allow the user to program the rising hysteresis. The Block Diagram of the comparator and the external resistors is shown in Figure 1. The typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: (R3 + R4) R4 VVIN, RISING = 2µA • R3 + VIN, FALLING VVIN, FALLING = 1.22 • For applications where the SHDN/UVLO pin is only used as a logic input, the SHDN/UVLO pin can be connected directly to the input voltage VIN through a 1k resistor for always-on operation. 3758f 11 LT3758 APPLICATIONS INFORMATION INTVCC Regulator Bypassing and Operation An internal, low dropout (LDO) voltage regulator produces the 7.2V INTVCC supply which powers the gate driver, as shown in Figure 1. The LT3758 contains an undervoltage lockout comparator A8 and an overvoltage lockout comparator A9 for the INTVCC supply. The INTVCC undervoltage (UV) threshold is 4.5V (typical), with 0.5V hysteresis, to ensure that the MOSFETs have sufficient gate drive voltage before turning on. The logic circuitry within the LT3758 is also powered from the internal INTVCC supply. The INTVCC overvoltage threshold is set to be 17.5V (typical) to protect the gate of the power MOSFET. When INTVCC is below the UV threshold, or above the overvoltage threshold, the GATE pin will be forced to GND and the soft-start operation will be triggered. The INTVCC regulator must be bypassed to ground immediately adjacent to the IC pins with a minimum of 4.7μF ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate driver. In an actual application, most of the IC supply current is used to drive the gate capacitance of the power MOSFET. The on-chip power dissipation can be a significant concern when a large power MOSFET is being driven at a high frequency and the VIN voltage is high. It is important to limit the power dissipation through selection of MOSFET and/or operating frequency so the LT3758 does not exceed its maximum junction temperature rating. The junction temperature TJ can be estimated using the following equations: TJ = TA + PIC • θJA TA = ambient temperature θJA = junction-to-ambient thermal resistance PIC = IC power consumption = VIN • (IQ + IDRIVE) IQ = VIN operation IQ = 1.6mA IDRIVE = average gate drive current = f • QG f = switching frequency QG = power MOSFET total gate charge 3758f The LT3758 uses packages with an Exposed Pad for enhanced thermal conduction. With proper soldering to the Exposed Pad on the underside of the package and a full copper plane underneath the device, thermal resistance (θJA) will be about 43°C/W for the DD package and 40°C/W for the MSE package. For an ambient board temperature of TA = 70°C and maximum junction temperature of 125°C, the maximum IDRIVE (IDRIVE(MAX)) of the DD package can be calculated as: IDRIVE(MAX ) = ( TJ − T A ) 1.28 W − IQ = − 1.6mA VIN (θ JA • VIN ) The LT3758 has an internal INTVCC IDRIVE current limit function to protect the IC from excessive on-chip power dissipation. The IDRIVE current limit decreases as the VIN increases (see the INTVCC Minimum Output Current vs VIN graph in the Typical Performance Characteristics section). If IDRIVE reaches the current limit, INTVCC voltage will fall and may trigger the soft-start. Based on the preceding equation and the INTVCC Minimum Output Current vs VIN graph, the user can calculate the maximum MOSFET gate charge the LT3758 can drive at a given VIN and switch frequency. A plot of the maximum QG vs VIN at different frequencies to guarantee a minimum 4.7V INTVCC is shown in Figure 2. 140 300kHz 120 100 QG (nC) 80 60 40 20 0 1 1MHz 10 VIN (V) 100 3758 F02 Figure 2. Recommended Maximum QG vs VIN at Different Frequencies to Ensure INTVCC Higher Than 4.7V 12 LT3758 APPLICATIONS INFORMATION As illustrated in Figure 2, a trade-off between the operating frequency and the size of the power MOSFET may be needed in order to maintain a reliable IC junction temperature. Prior to lowering the operating frequency, however, be sure to check with power MOSFET manufacturers for their most recent low QG, low RDS(ON) devices. Power MOSFET manufacturing technologies are continually improving, with newer and better performance devices being introduced almost yearly. An effective approach to reduce the power consumption of the internal LDO for gate drive is to tie the INTVCC pin to an external voltage source high enough to turn off the internal LDO regulator. If the input voltage VIN does not exceed the absolute maximum rating of both the power MOSFET gate-source voltage (VGS) and the INTVCC overvoltage lockout threshold voltage (17.5V), the INTVCC pin can be shorted directly to the VIN pin. In this condition, the internal LDO will be turned off and the gate driver will be powered directly from the input voltage VIN. With the INTVCC pin shorted to VIN, however, a small current (around 16μA) will load the INTVCC in shutdown mode. For applications that require the lowest shutdown mode input supply current, do not connect the INTVCC pin to VIN. In SEPIC or flyback applications, the INTVCC pin can be connected to the output voltage VOUT through a blocking diode, as shown in Figure 3, if VOUT meets the following conditions: 1. VOUT < VIN (pin voltage) 2. VOUT < 17.5V 3. VOUT < maximum VGS rating of power MOSFET A resistor RVCC can be connected, as shown in Figure 3, to limit the inrush current from VOUT. Regardless of whether LT3758 INTVCC CVCC 4.7μF GND 3758 F03 or not the INTVCC pin is connected to an external voltage source, it is always necessary to have the driver circuitry bypassed with a 4.7μF low ESR ceramic capacitor to ground immediately adjacent to the INTVCC and GND pins. Operating Frequency and Synchronization The choice of operating frequency may be determined by on-chip power dissipation, otherwise it is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing gate drive current and MOSFET and diode switching losses. However, lower frequency operation requires a physically larger inductor. Switching frequency also has implications for loop compensation. The LT3758 uses a constant-frequency architecture that can be programmed over a 100kHz to 1000kHz range with a single external resistor from the RT pin to ground, as shown in Figure 1. The RT pin must have an external resistor to GND for proper operation of the LT3758. A table for selecting the value of RT for a given operating frequency is shown in Table 1. Table 1. Timing Resistor (RT ) Value SWITCHING FREQUENCY (kHz) 100 200 300 400 500 600 700 800 900 1000 RT (kΩ) 140 63.4 41.2 30.9 24.3 19.6 16.5 14 12.1 10.5 DVCC RVCC VOUT Figure 3. Connecting INTVCC to VOUT 3758f 13 LT3758 APPLICATIONS INFORMATION The operating frequency of the LT3758 can be synchronized to an external clock source. By providing a digital clock signal into the SYNC pin, the LT3758 will operate at the SYNC clock frequency. If this feature is used, an RT resistor should be chosen to program a switching frequency 20% slower than SYNC pulse frequency. The SYNC pulse should have a minimum pulse width of 200ns. Tie the SYNC pin to GND if this feature is not used. Duty Cycle Consideration Switching duty cycle is a key variable defining converter operation. As such, its limits must be considered. Minimum on-time is the smallest time duration that the LT3758 is capable of turning on the power MOSFET. This time is generally about 220ns (typical) (see Minimum On-Time in the Electrical Characteristics table). In each switching cycle, the LT3758 keeps the power switch off for at least 220ns (typical) (see Minimum Off-Time in the Electrical Characteristics table). The minimum on-time and minimum off-time and the switching frequency define the minimum and maximum switching duty cycles a converter is able to generate: Minimum duty cycle = minimum on-time • frequency Maximum duty cycle = 1 – (minimum off-time • frequency) Programming the Output Voltage The output voltage VOUT is set by a resistor divider, as shown in Figure 1. The positive and negative VOUT are set by the following equations: ⎛ R2 ⎞ VOUT, POSITIVE = 1.6 V • ⎜ 1+ ⎟ ⎝ R1⎠ ⎛ R2 ⎞ VOUT, NEGATIVE = –0.8 V • ⎜ 1+ ⎟ ⎝ R1⎠ The resistors R1 and R2 are typically chosen so that the error caused by the current flowing into the FBX pin during normal operation is less than 1% (this translates to a maximum value of R1 at about 158k). Soft-Start The LT3758 contains several features to limit peak switch currents and output voltage (VOUT) overshoot during start-up or recovery from a fault condition. The primary purpose of these features is to prevent damage to external components or the load. High peak switch currents during start-up may occur in switching regulators. Since VOUT is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. A large surge current may cause inductor saturation or power switch failure. The LT3758 addresses this mechanism with the SS pin. As shown in Figure 1, the SS pin reduces the power MOSFET current by pulling down the VC pin through Q2. In this way the SS allows the output capacitor to charge gradually toward its final value while limiting the start-up peak currents. The typical start-up waveforms are shown in the Typical Performance Characteristics section. The inductor current IL slewing rate is limited by the soft-start function. Besides start-up (with SHDN/UVLO), soft-start can also be triggered by the following faults: 1. INTVCC > 17.5V 2. INTVCC < 4.5V 3. Thermal lockout Any of these three faults will cause the LT3758 to stop switching immediately. The SS pin will be discharged by Q3. When all faults are cleared and the SS pin has been discharged below 0.2V, a 10μA current source IS2 starts charging the SS pin, initiating a soft-start operation. The soft-start interval is set by the soft-start capacitor selection according to the equation: TSS = CSS • 1.25V 10µA 3758f 14 LT3758 APPLICATIONS INFORMATION FBX Frequency Foldback When VOUT is very low during start-up or a GND fault on the output, the switching regulator must operate at low duty cycles to maintain the power switch current within the current limit range, since the inductor current decay rate is very low during switch off time. The minimum ontime limitation may prevent the switcher from attaining a sufficiently low duty cycle at the programmed switching frequency. So, the switch current will keep increasing through each switch cycle, exceeding the programmed current limit. To prevent the switch peak currents from exceeding the programmed value, the LT3758 contains a frequency foldback function to reduce the switching frequency when the FBX voltage is low (see the Normalized Switching Frequency vs FBX graph in the Typical Performance Characteristics section). During frequency foldback, external clock synchronization is disabled to prevent interference with frequency reducing operation. Thermal Lockout If LT3758 die temperature reaches 165°C (typical), the part will go into thermal lockout. The power switch will be turned off. A soft-start operation will be triggered. The part will be enabled again when the die temperature has dropped by 5°C (nominal). Loop Compensation Loop compensation determines the stability and transient performance. The LT3758 uses current mode control to regulate the output which simplifies loop compensation. The optimum values depend on the converter topology, the component values and the operating conditions (including VSENSE VSENSE = VSENSE(MAX) VSENSE(PEAK) t TS 3758 F04 the input voltage, load current, etc.). To compensate the feedback loop of the LT3758, a series resistor-capacitor network is usually connected from the VC pin to GND. Figure 1 shows the typical VC compensation network. For most applications, the capacitor should be in the range of 470pF to 22nF and the resistor should be in the range of , 5k to 50k. A small capacitor is often connected in parallel with the RC compensation network to attenuate the VC voltage ripple induced from the output voltage ripple through the internal error amplifier. The parallel capacitor usually ranges in value from 10pF to 100pF A practical . approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance. Stability should then be checked across all operating conditions, including load current, input voltage and temperature. SENSE Pin Programming For control and protection, the LT3758 measures the power MOSFET current by using a sense resistor (RSENSE) between GND and the MOSFET source. Figure 4 shows a typical waveform of the sense voltage (VSENSE) across the sense resistor. It is important to use Kelvin traces between the SENSE pin and RSENSE, and to place the IC GND as close as possible to the GND terminal of the RSENSE for proper operation. Due to the current limit function of the SENSE pin, RSENSE should be selected to guarantee that the peak current sense voltage VSENSE(PEAK) during steady state normal operation is lower than the SENSE current limit threshold (see the Electrical Characteristics table). Given a 20% margin, VSENSE(PEAK) is set to be 80mV. Then, the maximum VSENSE(MAX) DTS Figure 4. The Sense Voltage During a Switching Cycle 3758f 15 LT3758 APPLICATIONS INFORMATION switch ripple current percentage can be calculated using the following equation: χ= ΔVSENSE 80mV − 0.5 • ΔVSENSE APPLICATION CIRCUITS The LT3758 can be configured as different topologies. The first topology to be analyzed will be the boost converter, followed by the flyback, SEPIC and inverting converters. Boost Converter: Switch Duty Cycle and Frequency The LT3758 can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. Remember that boost converters are not short-circuit protected. Under a shorted output condition, the inductor current is limited only by the input supply capability. For applications requiring a step-up converter that is short-circuit protected, please refer to the Applications Information section covering SEPIC converters. The conversion ratio as a function of duty cycle is VOUT 1 = VIN 1− D in continuous conduction mode (CCM). For a boost converter operating in CCM, the duty cycle of the main switch can be calculated based on the output voltage (VOUT) and the input voltage (VIN). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = RSENSE χ is used in subsequent design examples to calculate inductor value. ΔVSENSE is the ripple voltage across RSENSE. The LT3758 switching controller incorporates 100ns timing interval to blank the ringing on the current sense signal immediately after M1 is turned on. This ringing is caused by the parasitic inductance and capacitance of the PCB trace, the sense resistor, the diode, and the MOSFET. The 100ns timing interval is adequate for most of the LT3758 applications. In the applications that have very large and long ringing on the current sense signal, a small RC filter can be added to filter out the excess ringing. Figure 5 shows the RC filter on the SENSE pin. It is usually sufficient to choose 22Ω for RFLT and 2.2nF to 10nF for CFLT. Keep RFLT’s resistance low. Remember that there is 65μA (typical) flowing out of the SENSE pin. Adding RFLT will affect the SENSE current limit threshold: VSENSE_ILIM = 110mV – 65μA • RFLT GATE LT3758 RFLT SENSE GND CFLT M1 VOUT − VIN(MIN) VOUT 3758 F05 Discontinuous conduction mode (DCM) provides higher conversion ratios at a given frequency at the cost of reduced efficiencies and higher switching currents. Boost Converter: Inductor and Sense Resistor Selection For the boost topology, the maximum average inductor current is: 1 IL(MAX ) = IO(MAX ) • 1− DMAX Then, the ripple current can be calculated by: ΔIL = χ • IL(MAX ) = χ • IO(MAX ) • 1 1− DMAX 3758f Figure 5. The RC Filter on the SENSE Pin 16 LT3758 APPLICATIONS INFORMATION The constant χ in the preceding equation represents the percentage peak-to-peak ripple current in the inductor, relative to IL(MAX). The inductor ripple current has a direct effect on the choice of the inductor value. Choosing smaller values of ΔIL requires large inductances and reduces the current loop gain (the converter will approach voltage mode). Accepting larger values of ΔIL provides fast transient response and allows the use of low inductances, but results in higher input current ripple and greater core losses. It is recommended that χ fall within the range of 0.2 to 0.6. Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value of the boost converter can be determined using the following equation: L= VIN(MIN) ΔIL • f • DMAX The power MOSFET will see full output voltage, plus a diode forward voltage, and any additional ringing across its drain-to-source during its off-time. It is recommended to choose a MOSFET whose BVDSS is higher than VOUT by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the MOSFET in a boost converter is: PFET = I2L(MAX) • RDS(ON) • DMAX + 2 • V2OUT • IL(MAX) • CRSS • f/1A The first term in the preceding equation represents the conduction losses in the device, and the second term, the switching loss. CRSS is the reverse transfer capacitance, which is usually specified in the MOSFET characteristics. For maximum efficiency, RDS(ON) and CRSS should be minimized. From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following equation: TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA) TJ must not exceed the MOSFET maximum junction temperature rating. It is recommended to measure the MOSFET temperature in steady state to ensure that absolute maximum ratings are not exceeded. Boost Converter: Output Diode Selection To maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desirable. The peak reverse voltage that the diode must withstand is equal to the regulator output voltage plus any additional ringing across its anode-to-cathode during the on-time. The average forward current in normal operation is equal to the output current, and the peak current is equal to: ⎛ χ⎞ ID(PEAK ) = IL(PEAK ) = ⎜ 1+ ⎟ • IL(MAX ) ⎝ 2⎠ It is recommended that the peak repetitive reverse voltage rating VRRM is higher than VOUT by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the diode is: PD = IO(MAX) • VD and the diode junction temperature is: TJ = TA + PD • RθJA 3758f The peak and RMS inductor current are: ⎛ χ⎞ IL(PEAK ) = IL(MAX ) • ⎜ 1+ ⎟ ⎝ 2⎠ χ2 IL(RMS) = IL(MAX ) • 1+ 12 Based on these equations, the user should choose the inductors having sufficient saturation and RMS current ratings. Set the sense voltage at IL(PEAK) to be the minimum of the SENSE current limit threshold with a 20% margin. The sense resistor value can then be calculated to be: RSENSE = 80 mV IL(PEAK ) Boost Converter: Power MOSFET Selection Important parameters for the power MOSFET include the drain-source voltage rating (VDS), the threshold voltage (VGS(TH)), the on-resistance (RDS(ON)), the gate to source and gate to drain charges (QGS and QGD), the maximum drain current (ID(MAX)) and the MOSFET’s thermal resistances (RθJC and RθJA). 17 LT3758 APPLICATIONS INFORMATION The RθJA to be used in this equation normally includes the RθJC for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. Boost Converter: Output Capacitor Selection Contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct output capacitors for a given output ripple voltage. The effect of these three parameters (ESR, ESL and bulk C) on the output voltage ripple waveform for a typical boost converter is illustrated in Figure 6. tON tOFF VCOUT VOUT (AC) RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) 3758 F06 The output capacitor in a boost regulator experiences high RMS ripple currents, as shown in Figure 6. The RMS ripple current rating of the output capacitor can be determined using the following equation: IRMS(COUT) ≥ IO(MAX ) • DMAX 1− DMAX Multiple capacitors are often paralleled to meet ESR requirements. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the required RMS current rating. Additional ceramic capacitors in parallel are commonly used to reduce the effect of parasitic inductance in the output capacitor, which reduces high frequency switching noise on the converter output. Boost Converter: Input Capacitor Selection The input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input, and the input current waveform is continuous. The input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10μF to 100μF A low ESR capacitor . is recommended, although it is not as critical as for the output capacitor. The RMS input capacitor ripple current for a boost converter is: IRMS(CIN) = 0.3 • ΔIL FLYBACK CONVERTER APPLICATIONS The LT3758 can be configured as a flyback converter for the applications where the converters have multiple outputs, high output voltages or isolated outputs. Figure 7 shows a simplified flyback converter. The flyback converter has a very low parts count for multiple outputs, and with prudent selection of turns ratio, can have high output/input voltage conversion ratios with a desirable duty cycle. However, it has low efficiency due to the high peak currents, high peak voltages and consequent power loss. The flyback converter is commonly used for an output power of less than 50W. 3758f VESR Figure 6. The Output Ripple Waveform of a Boost Converter The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step ΔVESR and the charging/discharging ΔVCOUT. For the purpose of simplicity, we will choose 2% for the maximum output ripple, to be divided equally between ΔVESR and ΔVCOUT. This percentage ripple will change, depending on the requirements of the application, and the following equations can easily be modified. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation: ESRCOUT ≤ 0.01• VOUT ID(PEAK ) For the bulk C component, which also contributes 1% to the total ripple: COUT ≥ IO(MAX ) 0.01• VOUT • f 18 LT3758 APPLICATIONS INFORMATION The flyback converter can be designed to operate either in continuous or discontinuous mode. Compared to continuous mode, discontinuous mode has the advantage of smaller transformer inductances and easy loop compensation, and the disadvantage of higher peak-to-average current and lower efficiency. SUGGESTED RCD SNUBBER VIN NP:NS D to the number of variables involved. The user can choose either a duty cycle or a turns ratio as the start point. The following trade-offs should be considered when selecting the switch duty cycle or turns ratio, to optimize the converter performance. A higher duty cycle affects the flyback converter in the following aspects: • Lower MOSFET RMS current ISW(RMS), but higher MOSFET VDS peak voltage + CIN VSN – + CSN RSN LP LS ID + + COUT – DSN ISW LT3758 GATE SENSE M • Lower diode peak reverse voltage, but higher diode RMS current ID(RMS) • Higher transformer turns ratio (NP/NS) The choice, D 1 = D + D2 3 (for discontinuous mode operation with a given D3) gives the power MOSFET the lowest power stress (the product of RMS current and peak voltage). The choice, D 2 = D + D2 3 (for discontinuous mode operation with a given D3) gives the diode the lowest power stress (the product of RMS current and peak voltage). An extreme high or low duty cycle results in high power stress on the MOSFET or diode, and reduces efficiency. It is recommended to choose a duty cycle between 20% and 80%. VDS + – VDS RSENSE GND 3758 F07 Figure 7. A Simplified Flyback Converter Flyback Converter: Switch Duty Cycle and Turns Ratio The flyback converter conversion ratio in the continuous mode operation is: VOUT NS D = • VIN NP 1− D Where NS/NP is the second to primary turns ratio. Figure 8 shows the waveforms of the flyback converter in discontinuous mode operation. During each switching period TS, three subintervals occur: DTS, D2TS, D3TS. During DTS, M is on, and D is reverse-biased. During D2TS, M is off, and LS is conducting current. Both LP and LS currents are zero during D3TS. The flyback converter conversion ratio in the discontinuous mode operation is: ISW ISW(MAX) ID VOUT NS D = • VIN NP D2 According to the preceding equations, the user has relative freedom in selecting the switch duty cycle or turns ratio to suit a given application. The selections of the duty cycle and the turns ratio are somewhat iterative processes, due ID(MAX) DTS D2TS TS D3TS t 3758 F08 Figure 8. Waveforms of the Flyback Converter in Discontinuous Mode Operation 3758f 19 LT3758 APPLICATIONS INFORMATION Flyback Converter: Transformer Design for Discontinuous Mode Operation The transformer design for discontinuous mode of operation is chosen as presented here. According to Figure 8, the minimum D3 (D3MIN) occurs when the the converter has the minimum VIN and the maximum output power (POUT). Choose D3MIN to be equal to or higher than 10% to guarantee the converter is always in discontinuous mode operation. Choosing higher D3 allows the use of low inductances but results in higher switch peak current. The user can choose a DMAX as the start point. Then, the maximum average primary currents can be calculated by the following equation: ILP(MAX ) = ISW(MAX ) = POUT(MAX ) DMAX • VIN(MIN) • η The primary and second inductor values of the flyback converter transformer can be determined using the following equations: LP = LS = D2MAX • V 2IN(MAX ) • η 2 • POUT(MAX ) • f D22 •( VOUT + VD) 2 • IOUT(MAX ) • f The primary to second turns ratio is: NP L =P NS LS Flyback Converter: Snubber Design Transformer leakage inductance (on either the primary or secondary) causes a voltage spike to occur after the MOSFET turn-off. This is increasingly prominent at higher load currents, where more stored energy must be dissipated. In some cases a snubber circuit will be required to avoid overvoltage breakdown at the MOSFET’s drain node. There are different snubber circuits, and Application Note 19 is a good reference on snubber design. An RCD snubber is shown in Figure 7. The snubber resistor value (RSN) can be calculated by the following equation: where η is the converter efficiency. If the flyback converter has multiple outputs, POUT(MAX) is the sum of all the output power. The maximum average secondary current is: ILS(MAX ) = ID(MAX ) = where D2 = 1 – DMAX – D3 the primary and secondary RMS currents are: ILP(RMS) = 2 • ILP(MAX ) • ILS(RMS) = 2 • ILS(MAX ) • DMAX 3 D2 3 IOUT(MAX ) D2 V 2SN − VSN • VOUT • RSN = 2 • NP NS I2SW(PEAK ) • L LK • f According to Figure 8, the primary and secondary peak currents are: ILP(PEAK) = ISW(PEAK) = 2 • ILP(MAX) ILS(PEAK) = ID(PEAK) = 2 • ILS(MAX) where VSN is the snubber capacitor voltage. A smaller VSN results in a larger snubber loss. A reasonable VSN is 2 to 2.5 times of: VOUT • NP NS 3758f 20 LT3758 APPLICATIONS INFORMATION LLK is the leakage inductance of the primary winding, which is usually specified in the transformer characteristics. LLK can be obtained by measuring the primary inductance with the secondary windings shorted. The snubber capacitor value (CCN) can be determined using the following equation: CCN = VSN ΔVSN • RCN • f From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following equation: TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA) TJ must not exceed the MOSFET maximum junction temperature rating. It is recommended to measure the MOSFET temperature in steady state to ensure that absolute maximum ratings are not exceeded. Flyback Converter: Output Diode Selection The output diode in a flyback converter is subject to large RMS current and peak reverse voltage stresses. A fast switching diode with a low forward drop and a low reverse leakage is desired. Schottky diodes are recommended if the output voltage is below 100V. Approximate the required peak repetitive reverse voltage rating VRRM using: VRRM > NS •V +V NP IN(MAX ) OUT where ΔVSN is the voltage ripple across CCN. A reasonable ΔVSN is 5% to 10% of VSN. The reverse voltage rating of DSN should be higher than the sum of VSN and VIN(MAX). Flyback Converter: Sense Resistor Selection In a flyback converter, when the power switch is turned on, the current flowing through the sense resistor (ISENSE) is: ISENSE = ILP Set the sense voltage at ILP(PEAK) to be the minimum of the SENSE current limit threshold with a 20% margin. The sense resistor value can then be calculated to be: RSENSE = 80 mV ILP(PEAK ) The power dissipated by the diode is: PD = IO(MAX) • VD and the diode junction temperature is: TJ = TA + PD • RθJA The RθJA to be used in this equation normally includes the RθJC for the device, plus the thermal resistance from the board to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. Flyback Converter: Output Capacitor Selection The output capacitor of the flyback converter has a similar operation condition as that of the boost converter. Refer to the Boost Converter: Output Capacitor Selection section for the calculation of COUT and ESRCOUT. The RMS ripple current rating of the output capacitors in discontinuous operation can be determined using the following equation: IRMS(COUT ),DISCONTINUOUS ≥ IO(MAX ) • 4 − (3 • D2) 3 • D2 3758f Flyback Converter: Power MOSFET Selection For the flyback configuration, the MOSFET is selected with a VDC rating high enough to handle the maximum VIN, the reflected secondary voltage and the voltage spike due to the leakage inductance. Approximate the required MOSFET VDC rating using: BVDSS > VDS(PEAK) where VDS(PEAK) = VIN(MAX) + VSN The power dissipated by the MOSFET in a flyback converter is: PFET = I2M(RMS) • RDS(ON) + 2 • V2DS(PEAK) • IL(MAX) • CRSS • f/1A The first term in this equation represents the conduction losses in the device, and the second term, the switching loss. CRSS is the reverse transfer capacitance, which is usually specified in the MOSFET characteristics. 21 LT3758 APPLICATIONS INFORMATION Flyback Converter: Input Capacitor Selection The input capacitor in a flyback converter is subject to a large RMS current due to the discontinuous primary current. To prevent large voltage transients, use a low ESR input capacitor sized for the maximum RMS current. The RMS ripple current rating of the input capacitors in discontinuous operation can be determined using the following equation: IRMS(CIN),DISCONTINUOUS ≥ POUT(MAX ) VIN(MIN) • η • 4 − (3 • DMAX ) 3 • DMAX The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT + VD VIN(MIN) + VOUT + VD SEPIC Converter: Inductor and Sense Resistor Selection As shown in Figure 1, the SEPIC converter contains two inductors: L1 and L2. L1 and L2 can be independent, but can also be wound on the same core, since identical voltages are applied to L1 and L2 throughout the switching cycle. For the SEPIC topology, the current through L1 is the converter input current. Based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of L1 and L2 are: IL1(MAX ) = IIN(MAX ) = IO(MAX ) • IL2(MAX ) = IO(MAX ) In a SEPIC converter, the switch current is equal to IL1 + IL2 when the power switch is on, therefore, the maximum average switch current is defined as: ISW(MAX ) = IL1(MAX ) + IL 2(MAX ) = IO(MAX ) • and the peak switch current is: ⎛ χ⎞ 1 ISW(PEAK ) = ⎜ 1+ ⎟ • IO(MAX ) • 1− DMAX ⎝ 2⎠ The constant χ in the preceding equations represents the percentage peak-to-peak ripple current in the switch, relative to ISW(MAX), as shown in Figure 9. Then, the switch ripple current ΔISW can be calculated by: ΔISW = χ • ISW(MAX) The inductor ripple currents ΔIL1 and ΔIL2 are identical: ΔIL1 = ΔIL2 = 0.5 • ΔISW The inductor ripple current has a direct effect on the choice of the inductor value. Choosing smaller values of 3758f SEPIC CONVERTER APPLICATIONS The LT3758 can be configured as a SEPIC (single-ended primary inductance converter), as shown in Figure 1. This topology allows for the input to be higher, equal, or lower than the desired output voltage. The conversion ratio as a function of duty cycle is: VOUT + VD D = VIN 1− D in continuous conduction mode (CCM). In a SEPIC converter, no DC path exists between the input and output. This is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. Compared to the flyback converter, the SEPIC converter has the advantage that both the power MOSFET and the output diode voltages are clamped by the capacitors (CIN, CDC and COUT), therefore, there is less voltage ringing across the power MOSFET and the output diodes. The SEPIC converter requires much smaller input capacitors than those of the flyback converter. This is due to the fact that, in the SEPIC converter, the inductor L1 is in series with the input, and the ripple current flowing through the input capacitor is continuous. SEPIC Converter: Switch Duty Cycle and Frequency For a SEPIC converter operating in CCM, the duty cycle of the main switch can be calculated based on the output voltage (VOUT), the input voltage (VIN) and the diode forward voltage (VD). DMAX 1− DMAX 1 1− DMAX 22 LT3758 APPLICATIONS INFORMATION ΔIL requires large inductances and reduces the current loop gain (the converter will approach voltage mode). Accepting larger values of ΔIL allows the use of low inductances, but results in higher input current ripple and greater core losses. It is recommended that χ falls in the range of 0.2 to 0.6. ISW ISW = ISW(MAX) where χL 1 = ΔIL1 IL1(MAX ) χ 2L2 IL2(RMS) = IL2(MAX ) • 1+ 12 where χL 2 = ΔIL2 IL2 (MAX ) ISW(MAX) DTS TS t 3758 F09 Based on the preceding equations, the user should choose the inductors having sufficient saturation and RMS current ratings. In a SEPIC converter, when the power switch is turned on, the current flowing through the sense resistor (ISENSE) is the switch current. Set the sense voltage at ISENSE(PEAK) to be the minimum of the SENSE current limit threshold with a 20% margin. The sense resistor value can then be calculated to be: RSENSE = 80 mV ISW(PEAK ) Figure 9. The Switch Current Waveform of the SEPIC Converter Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value (L1 and L2 are independent) of the SEPIC converter can be determined using the following equation: VIN(MIN) L1= L2 = •D 0.5 • ΔISW • f MAX For most SEPIC applications, the equal inductor values will fall in the range of 1μH to 100μH. By making L1 = L2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2L, due to mutual inductance: L= VIN(MIN) ΔISW • f • DMAX SEPIC Converter: Power MOSFET Selection For the SEPIC configuration, choose a MOSFET with a VDC rating higher than the sum of the output voltage and input voltage by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the MOSFET in a SEPIC converter is: PFET = I2SW(MAX) • RDS(ON) • DMAX + 2 • (VIN(MIN) + VOUT)2 • IL(MAX) • CRSS • f/1A The first term in this equation represents the conduction losses in the device, and the second term, the switching loss. CRSS is the reverse transfer capacitance, which is usually specified in the MOSFET characteristics. For maximum efficiency, RDS(ON) and CRSS should be minimized. From a known power dissipated in the power 3758f This maintains the same ripple current and energy storage in the inductors. The peak inductor currents are: IL1(PEAK) = IL1(MAX) + 0.5 • ΔIL1 IL2(PEAK) = IL2(MAX) + 0.5 • ΔIL2 The RMS inductor currents are: IL1(RMS) = IL1(MAX ) • 1+ χ 2L1 12 23 LT3758 APPLICATIONS INFORMATION MOSFET, its junction temperature can be obtained using the following equation: TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA) TJ must not exceed the MOSFET maximum junction temperature rating. It is recommended to measure the MOSFET temperature in steady state to ensure that absolute maximum ratings are not exceeded. SEPIC Converter: Output Diode Selection To maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable. The average forward current in normal operation is equal to the output current, and the peak current is equal to: ⎛ χ⎞ 1 ID(PEAK ) = ⎜ 1+ ⎟ • IO(MAX ) • 1− DMAX ⎝ 2⎠ It is recommended that the peak repetitive reverse voltage rating VRRM is higher than VOUT + VIN(MAX) by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the diode is: PD = IO(MAX) • VD and the diode junction temperature is: TJ = TA + PD • RθJA The RθJA used in this equation normally includes the RθJC for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. SEPIC Converter: Output and Input Capacitor Selection The selections of the output and input capacitors of the SEPIC converter are similar to those of the boost converter. Please refer to the Boost Converter: Output Capacitor Selection and Boost Converter: Input Capacitor Selection sections. SEPIC Converter: Selecting the DC Coupling Capacitor The DC voltage rating of the DC coupling capacitor (CDC, as shown in Figure 1) should be larger than the maximum input voltage: VCDC > VIN(MAX) VIN CDC has nearly a rectangular current waveform. During the switch off-time, the current through CDC is IIN, while approximately –IO flows during the on-time. The RMS rating of the coupling capacitor is determined by the following equation: VOUT + VD IRMS(CDC) > IO(MAX ) • VIN(MIN) A low ESR and ESL, X5R or X7R ceramic capacitor works well for CDC. INVERTING CONVERTER APPLICATIONS The LT3758 can be configured as a dual-inductor inverting topology, as shown in Figure 10. The VOUT to VIN ratio is: VOUT − VD D =− VIN 1− D in continuous conduction mode (CCM). L1 + CDC – L2 + CIN COUT LT3758 GATE SENSE RSENSE GND M1 D1 – + VOUT + 3758 F10 Figure 10. A Simplified Inverting Converter Inverting Converter: Switch Duty Cycle and Frequency For an inverting converter operating in CCM, the duty cycle of the main switch can be calculated based on the negative output voltage (VOUT) and the input voltage (VIN). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT − VD VOUT − VD − VIN(MIN) 3758f 24 LT3758 APPLICATIONS INFORMATION Inverting Converter: Inductor, Sense Resistor, Power MOSFET, Output Diode and Input Capacitor Selections The selections of the inductor, sense resistor, power MOSFET, output diode and input capacitor of an inverting converter are similar to those of the SEPIC converter. Please refer to the corresponding SEPIC converter sections. Inverting Converter: Output Capacitor Selection The inverting converter requires much smaller output capacitors than those of the boost, flyback and SEPIC converters for similar output ripples. This is due to the fact that, in the inverting converter, the inductor L2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. The output ripple voltage is produced by the ripple current of L2 flowing through the ESR and bulk capacitance of the output capacitor: ⎛ ⎞ 1 ΔVOUT(P – P) = ΔIL2 • ⎜ ESRCOUT + 8 • f • COUT ⎟ ⎝ ⎠ After specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. The ESR can be minimized by using high quality X5R or X7R dielectric ceramic capacitors. In many applications, ceramic capacitors are sufficient to limit the output voltage ripple. The RMS ripple current rating of the output capacitor needs to be greater than: IRMS(COUT) > 0.3 • ΔIL2 Inverting Converter: Selecting the DC Coupling Capacitor The DC voltage rating of the DC coupling capacitor (CDC, as shown in Figure 10) should be larger than the maximum input voltage minus the output voltage (negative voltage): VCDC > VIN(MAX) – VOUT CDC has nearly a rectangular current waveform. During the switch off-time, the current through CDC is IIN, while approximately –IO flows during the on-time. The RMS rating of the coupling capacitor is determined by the following equation: DMAX IRMS(CDC) > IO(MAX ) • 1− DMAX A low ESR and ESL, X5R or X7R ceramic capacitor works well for CDC. Board Layout The high speed operation of the LT3758 demands careful attention to board layout and component placement. The Exposed Pad of the package is the only GND terminal of the IC, and is important for thermal management of the IC. Therefore, it is crucial to achieve a good electrical and thermal contact between the Exposed Pad and the ground plane of the board. For the LT3758 to deliver its full output power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into a copper plane with as much area as possible. To prevent radiation and high frequency resonance problems, proper layout of the components connected to the IC is essential, especially the power paths with higher di/dt. The following high di/dt loops of different topologies should be kept as tight as possible to reduce inductive ringing: • In boost configuration, the high di/dt loop contains the output capacitor, the sensing resistor, the power MOSFET and the Schottky diode. • In flyback configuration, the high di/dt primary loop contains the input capacitor, the primary winding, the power MOSFET and the sensing resistor. The high di/dt secondary loop contains the output capacitor, the secondary winding and the output diode. • In SEPIC configuration, the high di/dt loop contains the power MOSFET, sense resistor, output capacitor, Schottky diode and the coupling capacitor. • In inverting configuration, the high di/dt loop contains power MOSFET, sense resistor, Schottky diode and the coupling capacitor. 3758f 25 LT3758 APPLICATIONS INFORMATION Check the stress on the power MOSFET by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the PC board). Beware of inductive ringing, which can exceed the maximum specified voltage rating of the MOSFET. If this ringing cannot be avoided, and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalancherated power MOSFET. The small-signal components should be placed away from high frequency switching nodes. For optimum load regulation and true remote sensing, the top of the output voltage sensing resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LT3758 in order to keep the high impedance FBX node short. Figure 11 shows the suggested layout of the 10V to 40V input, 48V output boost converter in the Typical Applications section. CIN VIN CC1 CC2 R1 R2 CSS RT RC 1 LT3758 2 3 4 5 10 9 R3 R4 L1 8 7 6 CVCC 1 2 M1 3 4 8 7 6 5 RS VIAS TO GROUND PLANE COUT2 COUT1 D1 VOUT 3758 F11 Figure 11. Suggested Layout of the 10V to 40V Input, 48V Output Boost Converter in the Typical Applications Section 3758f 26 LT3758 APPLICATIONS INFORMATION Recommended Component Manufacturers Some of the recommended component manufacturers are listed in Table 2. Table 2. Recommended Component Manufacturers VENDOR AVX BH Electronics Coilcraft Cooper Bussmann Diodes, Inc Fairchild General Semiconductor International Rectifier IRC Kemet Magnetics Inc Microsemi Murata-Erie Nichicon On Semiconductor Panasonic Pulse Sanyo Sumida Taiyo Yuden TDK Thermalloy Tokin Toko United Chemi-Con Vishay/Dale Vishay/Siliconix Würth Elektronik Vishay/Sprague Zetex COMPONENTS Capacitors Inductors, Transformers Inductors Inductors Diodes MOSFETs Diodes MOSFETs, Diodes Sense Resistors Tantalum Capacitors Toroid Cores Diodes Inductors, Capacitors Capacitors Diodes Capacitors Inductors Capacitors Inductors Capacitors Capacitors, Inductors Heat Sinks Capacitors Inductors Capacitors Resistors MOSFETs Inductors Capacitors Small-Signal Discretes TELEPHONE 207-282-5111 952-894-9590 847-639-6400 888-414-2645 805-446-4800 408-822-2126 516-847-3000 310-322-3331 361-992-7900 408-986-0424 800-245-3984 617-926-0404 770-436-1300 847-843-7500 602-244-6600 714-373-7334 858-674-8100 619-661-6835 847-956-0667 408-573-4150 562-596-1212 972-243-4321 408-432-8020 847-699-3430 847-696-2000 605-665-9301 800-554-5565 605-886-4385 207-324-4140 631-543-7100 WEB ADDRESS avx.com bhelectronics.com coilcraft.com bussmann.com diodes.com fairchildsemi.com generalsemiconductor. com irf.com irctt.com kemet.com mag-inc.com microsemi.com murata.co.jp nichicon.com onsemi.com panasonic.com pulseeng.com sanyo.co.jp sumida.com t-yuden.com component.tdk.com aavidthermalloy.com nec-tokinamerica.com tokoam.com chemi-com.com vishay.com vishay.com we-online.com vishay.com zetex.com 3758f 27 LT3758 TYPICAL APPLICATIONS 10V to 40V Input, 48V Output Boost Converter VIN 10V TO 40V CIN 4.7μF 50V X7R x2 R3 200k VIN SHDN/UVLO L1 18.7μH D1 VOUT 48V 1A R2 464k R4 32.4k SYNC RT SS LT3758 GATE SENSE FBX GND INTVCC RC 10k CC1 10nF CVCC 4.7μF 10V X5R M1 + R1 15.8k RT 41.2k 300kHz CSS 0.68μF CC2 100pF VC COUT1 100μF 63V COUT2 4.7μF 50V X7R x4 RS 0.012Ω 3758 TA02a CIN, COUT2: MURATA GRM32ER71H475KA88L COUT1: PANASONIC ECG EEV-TG1J101UP D1: VISHAY SILICONIX 30BQ060 L1: PULSE PB2020.223 M1: VISHAY SILICONIX SI7460DP Efficiency vs Output Current 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0.001 0.1 0.01 OUTPUT CURRENT (A) 1 3758 TA02b Start-Up Waveforms VIN = 24V VIN = 40V VIN = 24V VOUT 20V/DIV IL1 2A/DIV VIN = 10V 5ms/DIV 3758 TA02c 3758f 28 LT3758 TYPICAL APPLICATIONS 12V Output Nonisolated Flyback Power Supply D1 VIN 36V TO 72V CIN 2.2μF 100V X7R 1M VIN SHDN/UVLO 44.2k SYNC RT SS 63.4k 200kHz 0.47μF 100pF 10k 10nF VC DSN 0.022μF 100V 6.2k T1 1,2,3 (SERIES) SW GATE SENSE FBX GND INTVCC M1 4,5,6 (PARALLEL) VOUT 12V 1.2A LT3758 105k 1% 1N4148 5.1Ω COUT 47μF X5R CVCC 4.7μF 10V X5R 0.030Ω 15.8k 1% 3758 TA03a CIN: MURATA GRM32ER72A225KA35L T1: COILTRONICS VP2-0066 M1: VISHAY SILICONIX SI4848DY D1: ON SEMICONDUCTOR MBRS360T3G DSN: VISHAY SILICONIX ES1D COUT: MURATA GRM32ER61C476ME15L Efficiency vs Output Current 100 VIN = 48V 90 80 EFFICIENCY (%) 70 60 50 40 30 20 0.01 VOUT 5V/DIV Start-Up Waveform VIN = 48V 5ms/DIV 0.1 1 OUTPUT CURRENT (A) 10 3758 TA03b 3758 TA03c Frequency Foldback Waveforms When Output Short-Circuit VIN = 48V VOUT 5V/DIV VSW 50V/DIV 20μs/DIV 3758 TA03d 3758f 29 LT3758 TYPICAL APPLICATIONS VFD (Vacuum Fluorescent Display) Flyback Power Supply D1 COUT2 2.2μF 100V X7R VOUT 96V 80mA 4 VIN 9V TO 16V CIN 22μF 25V 178k VIN SHDN/UVLO 32.4k SYNC RT SS VC 0.47μF 63.4k 200kHz 47pF 10k 10nF T1 1, 2, 3 D2 VOUT2 64V 40mA 5 LT3758 GATE SENSE FBX GND INTVCC CVCC 4.7μF 10V X5R M1 SW 95.3k 6 COUT1 1μF 100V X7R 0.019Ω 0.5W 1.62k 3758 TA04a CIN: MURATA GRM32ER61E226KE15L COUT1: MURATA GRM31CR72A105K01L COUT2: MURATA GRM32ER72A225KA35L D1: VISHAY SILICONIX ES1D D2: VISHAY SILICONIX ES1C M1: VISHAY SILICONIX SI4848DY T1: COILTRONICS VP1-0102 (*PRIMARY = 3 WINDINGS IN PARALLEL) Start-Up Waveforms VIN = 12V VOUT1 VOUT1 1V/DIV (AC) VOUT2 1V/DIV (AC) VOUT1, VOUT2 20V/DIV 10ms/DIV 3758 TA04b Switching Waveforms VIN = 12V VOUT2 VSW 50V/DIV 2μs/DIV 3758 TA04c 3758f 30 LT3758 TYPICAL APPLICATIONS 36V to 72V Input, 3.3V Output Isolated Telecom Power Supply VIN 36V TO 72V PA1277NL 4 5 CIN 2.2μF 100V X7R 1M VIN SHDN/UVLO 44.2k SYNC INTVCC FBX RT SS 63.4k 200kHz 0.47μF GND VC 4.7μF 25V X5R 0.022μF 100V BAV21W 3 GATE SENSE 0.03Ω 4.7μF 25V X5R 1 16k 274Ω BAS516 LT4430 0.47μF 2200pF 250VAC 1μF VIN OPTO 47nF 2k GND COMP OC 0.5V FB 22.1k 3758 TA05a 5.6k 6 7 8 UPS840 COUT 100μF 6.3V x3 VOUT+ 3.3V 3A VOUT- FDC2512 10Ω BAS516 2 100pF LT3758 BAT54CWTIG 100k 47pF PS2801-1 Efficiency vs Output Current 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 0.01 VIN = 48V VIN = 36V VIN = 72V 0.1 1 OUTPUT CURRENT (A) 10 3758 TA05b 3758f 31 LT3758 TYPICAL APPLICATIONS 18V to 72V Input, 24V Output SEPIC Converter VIN 18V TO 72V CIN 2.2μF 100V X7R 232k VIN SHDN/UVLO 20k SYNC L1A CDC 2.2μF 100V X7R, x2 • D1 LT3758 GATE SENSE RT SS 0.025Ω FBX GND INTVCC 20k 1% M1 L1B VOUT 24V 1A 280k 1% • 41.2k 300kHz 0.47μF VC 10k 10nF CVCC 4.7μF 10V X5R 3757 TA06a COUT 10μF 25V X5R x4 CIN, CDC: TAIYO YUDEN HMK325B7225KN-T COUT: MURATA GRM31CR61E106KA12L L1A, L1B: COILTRONICS DRQ127-470 M1: FAIRCHILD SEMICONDUCTOR FDMS2572 D1: ON SEMICONDUCTOR MBRS3100T3G Efficiency vs Output Current 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0.001 0.1 0.01 OUTPUT CURRENT (A) 1 3757 TA06b Load Step Waveform VIN = 48V VIN = 18V VOUT 1V/DIV (AC) VIN = 48V VIN = 72V IOUT 0.8A 0.5A/DIV 0.2A 500μs/DIV 3757 TA06c Start-Up Waveform VIN = 48V VOUT 20V/DIV Frequency Foldback Waveforms When Output Short-Circuit VIN = 48V VOUT 10V/DIV VSW 50V/DIV IL1A + IL1B 1A/DIV 2ms/DIV 3757 TA06d IL1A + IL1B 2A/DIV 50μs/DIV 3757 TA06e 3758f 32 LT3758 TYPICAL APPLICATIONS 10V to 40V Input, –12V Output Inverting Converter VIN 10V TO 40V CDC 4.7μF 50V X7R, x2 CIN 4.7μF 50V X7R x2 R1 200k R2 32.4k SYNC • VIN SHDN/UVLO L1A L1B LT3758 GATE SENSE RT SS VC 0.015Ω FBX GND INTVCC 7.5k 10k CVCC 4.7μF 10V X5R M1 D1 105k VOUT -12V 2A • 41.2k 300kHz 0.47μF 6.8nF COUT 22μF 16V X5R x4 3757 TA07a CIN, CDC: MURATA GRM32ER71H475KA88L COUT: MURATA GRM32ER61C226KE20 D1: VISHAY SILICONIX 30BQ060 L1A, L1B: COILTRONICS DRQ127-150 M1: VISHAY SILICONIX SI7850DP Efficiency vs Output Current 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0.001 0.1 1 0.01 OUTPUT CURRENT (A) 10 3757 TA07b Load Step Waveforms VIN = 24V VOUT 500mV/DIV (AC) VIN = 10V VIN = 24V VIN = 40V IOUT 1.6A 1A/DIV 0.4A 500μs/DIV 3757 TA07c Start-Up Waveforms VOUT 5V/DIV VIN = 24V Frequency Foldback Waveforms When Output Short-Circuit VOUT VIN = 24V 10V/DIV VSW 20V/DIV IL1A + IL1B 2A/DIV 5ms/DIV 3757 TA07d IL1A + IL1B 5A/DIV 50μs/DIV 3757 TA07e 3758f 33 LT3758 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) R = 0.115 TYP 6 0.675 ±0.05 0.38 ± 0.10 10 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 6) 3.00 ±0.10 (4 SIDES) 1.65 ± 0.10 (2 SIDES) (DD) DFN 1103 5 0.200 REF 0.75 ±0.05 2.38 ±0.10 (2 SIDES) 1 0.25 ± 0.05 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD 3758f 34 LT3758 PACKAGE DESCRIPTION MSE Package 10-Lead Plastic MSOP Exposed Die Pad , (Reference LTC DWG # 05-08-1664 Rev C) BOTTOM VIEW OF EXPOSED PAD OPTION 2.794 (.110 0.102 .004) 0.889 (.035 0.127 .005) 1 2.06 0.102 (.081 .004) 1.83 0.102 (.072 .004) 0.29 REF 5.23 (.206) MIN 2.083 (.082 0.102 3.20 – 3.45 .004) (.126 – .136) 0.05 REF DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 0.497 0.076 (.0196 .003) REF 10 0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6 4.90 0.152 (.193 .006) 0.254 (.010) GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL “A” 0.18 (.007) SEATING PLANE 1.10 (.043) MAX DETAIL “A” 0 – 6 TYP 12345 3.00 0.102 (.118 .004) (NOTE 4) 0.86 (.034) REF 0.17 – 0.27 (.007 – .011) TYP NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.50 (.0197) BSC 0.1016 (.004 0.0508 .002) MSOP (MSE) 0908 REV C 3758f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LT3758 TYPICAL APPLICATIONS 8V to 72V Input, 12V Output SEPIC Converter VIN 8V TO 72V 100 CIN 2.2μF 100V X7R x2 Efficiency vs Output Current 90 80 EFFICIENCY (%) VOUT 12V 2A 70 60 50 40 30 20 VIN = 42V VIN = 72V 154k • VIN SHDN/UVLO L1A CDC 2.2μF 100V D1 X7R, x2 MBRS3100T3G VIN = 8V 32.4k SYNC LT3758 GATE SENSE RT SS 0.012Ω FBX GND INTVCC 15.8k 1% M1 Si7456DP L1B + 105k 1% • COUT1 47μF 20V x2 41.2k 300kHz 0.47μF VC 10k 10nF CVCC 4.7μF 10V X5R 3757 TA08a COUT2 10μF 16V X5R x4 10 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 10 3757 TA08b L1A, L1B: COILTRONICS DRQ127-220 RELATED PARTS PART NUMBER LT1619 LTC1624 LTC1871, LTC1871-1 LTC1871-7 LTC1872 LT1930 LT1931 LTC3704 LT3844 LT3757 LT3782A DESCRIPTION Current Mode PWM Controller Current Mode DC/DC Controller No RSENSE™ Boost, Flyback and SEPIC Controller No RSENSE Boost, Flyback and SEPIC Controller TSOT-23 Boost Controller 1.2MHz, SOT-23 Boost Converter Inverting 1.2MHz, SOT-23 Converter Positive-to-Negative DC/DC Controller High Voltage, Current Mode Switching Regulator Controller Boost, Flyback, SEPIC and Inverting Controller 2-Phase Step-Up DC/DC Controller COMMENTS 300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology; 1.9V ≤ VIN ≤ 18V VIN Up to 36V, 300kHz Operating Frequency; Buck, Boost, SEPIC Design, SO-8 Package 2.5V ≤ VIN ≤ 36V, Current Mode Control, Programmable Operating Frequency from 50kHz to 1MHz, 5V Gate Drive 7V Gate Drive Version of LTC1871 550kHz Fixed Frequency, Current Mode, 2.5V ≤ VIN ≤ 9.8V 2.6V ≤ VIN ≤ 16V, Up to 34V Output, 1A Switch Current Positive-to-Negative DC/DC Conversion, Miniature Design No RSENSE, Current Mode Control, 50kHz to 1MHz Wide Input Range: 4V to 60V 2.9V ≤ VIN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages 6V ≤ VIN ≤ 40V, 4A Gate Drive, 150kHz to 500kHz Wide Input Range; Flyback, Boost and SEPIC Topologies, ThinSOT™ Package VIN and VOUT Limited Only by External Components, Used in Flyback, Boost and SEPIC Topologies 1.23V ≤ VOUT ≤ 36V, 4V ≤ VIN ≤ 60V, 120μA IQ 2.75V ≤ VIN ≤ 9.8V, Current Mode Control, TSOT-23 and 2mm × 3mm DFN-8 Packages LTC3803, LTC3803-3, Constant-Frequency, Current Mode DC/DC LTC3803-5 Controller LTC3805, LTC3805-5 LT3845 LTC3872 Adjustable, Synchronizable Frequency, Current Mode DC/DC Controller Low IQ, High Voltage Single Output Synchronous Step-Down DC/DC Controller No RSENSE Boost, Flyback and SEPIC Controller No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. 3758f 36 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0709 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009