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LMA2009JC45

LMA2009JC45

  • 厂商:

    LODEV

  • 封装:

  • 描述:

    LMA2009JC45 - 12 x 12-bit Multiplier-Accumulator - LOGIC Devices Incorporated

  • 数据手册
  • 价格&库存
LMA2009JC45 数据手册
LMA 1009/2009 DEVICES INCORPORATED 12 x 12-bit Multiplier-Accumulator LMA1009/2009 DEVICES INCORPORATED 12 x 12-bit Multiplier-Accumulator DESCRIPTION Data present at the A and B input registers is latched on the rising edges of CLK A and CLK B respectively. RND, TC, ACC, and SUB controls are latched on the rising edge of the logical OR of CLK A and CLK B. TC specifies the input as two’s complement (TC HIGH) or unsigned magnitude (TC LOW). RND, when HIGH, adds ‘1’ to the most significant bit position of the least significant half of the product. SubThe LMA1009/2009 produces the 24-bit sequent truncation of the 12 least signifiproduct of two 12-bit numbers. The cant bits produces a result correctly results of a series of multiplications may rounded to 12-bit precision. be accumulated to form the sum of products. Accumulation is performed to The ACC and SUB inputs control accu27-bit precision with the multiplier prod- mulator operation. ACC HIGH results in addition of the multiplier product and uct sign extended as appropriate. the accumulator contents, with the result stored in the accumulator register on the rising edge of CLK R. ACC and SUB A 11-0 B 11-0 HIGH results in subtraction of the accu12 12 mulator contents from the multiplier A REGISTER B REGISTER product, with the result stored in the accumulator register. With ACC LOW and SUB LOW, no accumulation occurs and the next product is loaded directly into the accumulator register. ACC LOW and SUB HIGH is undefined. The LMA1009 and LMA2009 are highspeed, low power 12-bit multiplier-accumulators. They are pin-for-pin equivalent to the TRW TDC1009/TMC2009 multiplier-accumulators. The LMA1009 and LMA2009 are functionally identical; they differ only in packaging. Full ambient temperature range operation is achieved by the use of advanced CMOS technology. 24 R R+A A 27 FEATURES u 20 ns Multiply-Accumulate Time u Low Power CMOS Technology u Replaces Fairchild TDC1009/ TMC2009 u Two’s Complement or Unsigned Operands u Accumulator Performs Preload, Accumulate, and Subtract u Three-State Outputs u 68-pin PLCC, J-Lead LMA1009/2009 BLOCK DIAGRAM CLK A CLK B TC ACC SUB REGISTER RND OEX OEM OEL PREL 3 OEX OEM OEL PRELOAD CONTROL LOGIC 3 LEX LEM LEL R–A PASS R The LMA1009/2009 output register (accumulator register) is divided into three independently controlled sections. The least significant result (LSR) and most significant result (MSR) registers are 12 bits in length. The extended result register (XTR) is 3 bits long. Each output register has an independent output enable control. In addition to providing control of the three-state output buffers, when OEX, OEM, or OEL are HIGH and PREL is HIGH, data can be preloaded via the bidirectional output pins into the respective output registers. Data present on the output pins is latched on the rising edge of CLK R. The interrelation of PREL and the enable controls is summarized in Table 1. LEX 27 3 LEM 12 LEL 12 CLK R ACCUMULATOR REGISTER OEX 3 R 26-24 OEM 12 R 23-12 OEL 12 R 11-0 Multiplier-Accumulators 1 03/29/2000–LDS.10/2009-L LMA 1009/2009 DEVICES INCORPORATED 12 x 12-bit Multiplier-Accumulator FIGURE 1A. INPUT FORMATS AIN BIN Fractional Two’s Complement (TC = 1) 11 10 9 –20 2–1 2–2 (Sign) TABLE 1. PRELOAD TRUTH TABLE PREL OEX L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H OEM L L H H L L H H L L H H L L H H OEL L H L H L H L H L H L H L H L H XTR OUT OUT OUT OUT Z Z Z Z Z Z Z Z PREL PREL MSR LSR OUT OUT OUT Z Z Z OUT Z 210 2–9 2–10 2–11 11 10 9 –20 2–1 2–2 (Sign) 210 2–9 2–10 2–11 OUT OUT OUT Z Z Z Z PREL Z OUT Z Z PREL Z Integer Two’s Complement (TC = 1) 11 10 9 –211 210 29 (Sign) 210 22 21 20 11 10 9 –211 210 29 (Sign) 210 22 21 20 Unsigned Fractional (TC = 0) 11 10 9 2–1 2–2 2–3 210 2–10 2–11 2–12 11 10 9 2–1 2–2 2–3 210 2–10 2–11 2–12 PREL PREL Z Z Z PREL Z PREL PREL PREL PREL PREL Unsigned Integer (TC = 0) 11 10 9 211 210 29 210 22 21 20 11 10 9 211 210 29 210 22 21 20 PREL = Preload data to appropriate register OUT = Register available on output pins Z = High impedance state FIGURE 1B. OUTPUT FORMATS XTR MSR Fractional Two’s Complement 26 25 24 –24 23 22 (Sign) LSR 23 22 21 21 20 2–1 14 13 12 2–8 2–9 2–10 11 10 9 2–11 2–12 2–13 210 2–20 2–21 2–22 Integer Two’s Complement 26 25 24 –226 225 224 (Sign) 23 22 21 223 222 221 14 13 12 214 213 212 Unsigned Fractional 11 10 9 211 210 29 210 22 21 20 26 25 24 22 21 20 23 22 21 2–1 2–2 2–3 14 13 12 2–10 2–11 2–12 Unsigned Integer 11 10 9 2–13 2–14 2–15 210 2–22 2–23 2–24 26 25 24 226 225 224 23 22 21 223 222 221 14 13 12 214 213 212 11 10 9 211 210 29 210 22 21 20 Multiplier-Accumulators 2 03/29/2000–LDS.10/2009-L LMA 1009/2009 DEVICES INCORPORATED 12 x 12-bit Multiplier-Accumulator MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent (Note 3) Test Condition VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 8.0 mA Min 2.4 Typ Max Unit V 0.5 2.0 0.0 VCC 0.8 ±20 ±20 12 25 1.0 V V V µA µA mA mA Ground ≤ VIN ≤ VCC (Note 12) Ground ≤ VOUT ≤ VCC (Note 12) (Notes 5, 6) (Note 7) Multiplier-Accumulators 3 03/29/2000–LDS.10/2009-L 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol *includes OEX, OEM, OEL 321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321 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32109876543210987654321 32109876543210987654321 3210987654321098765432 Min 15 15 15 2 2 DEVICES INCORPORATED SWITCHING WAVEFORMS MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS tDIS tENA tD tHP tSP tH tS tPW tMC tDIS tENA tD tHP tSP tH tS tPW tMC CLK R CLK A CLK B PREL R26-0 A11-0 B11-0 OE* Parameter Parameter Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Output Delay Preload Hold Time Preload Setup Time Input Register Hold Time Input Register Setup Time Clock Pulse Width Clocked Multiply Time Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Output Delay Preload Hold Time Preload Setup Time Input Register Hold Time Input Register Setup Time Clock Pulse Width Clocked Multiply Time tSP PRELOAD tHP tPW tS tDIS 4 tH tPW HIGH IMPEDANCE tPW 12 x 12-bit Multiplier-Accumulator 95* 75* tMC Max Max 30 35 25 30 35 30 95 75 tENA Min Min 15 15 20 20 15 20 2 2 2 2 Multiplier-Accumulators LMA1009/2009– 65* 55* LMA1009/2009– 55* 45 Max Max 25 30 25 55 30 35 30 65 Min Min tD 12 15 12 15 15 15 2 2 2 2 LMA 1009/2009 Max Max 03/29/2000–LDS.10/2009-L 25 25 25 45 30 30 25 55 OUTPUT Min Min 12 10 12 10 10 2 2 2 8 2 25* 20 Max Max 20 20 20 25 18 18 18 20 LMA 1009/2009 DEVICES INCORPORATED 12 x 12-bit Multiplier-Accumulator NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. where 4 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 5 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.5V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA Multiplier-Accumulators 5 03/29/2000–LDS.10/2009-L 121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 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1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 DEVICES INCORPORATED Speed –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING 0°C to +70°C — COMMERCIAL SCREENING LMA1009 — ORDERING INFORMATION 64-pin A4 A3 A2 A1 A0 ACC SUB RND OEL R0 R1 R2 R3 R4 R5 GND R6 R7 R8 R9 R10 R11 CLK R PREL OEM R12 R13 R14 R15 R16 R17 R18 Sidebraze Hermetic DIP (D6) Discontinued Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 A5 A6 A7 A8 A9 A10 A11 CLK A CLK B B0 B1 B2 B3 B4 B5 VCC B6 B7 B8 B9 B10 B11 TC OEX R26 R25 R24 R23 R22 R21 R20 R19 6 68-pin G H D C K E B A F L J 12 x 12-bit Multiplier-Accumulator GND PREL CLK R R11 NC R9 R4 R2 R0 R7 1 OEM R13 OEL SUB R12 R10 NC R8 R6 R5 R3 R1 2 RND ACC R14 3 Ceramic Pin Grid Array (G2) Discontinued Package R16 R15 (i.e., Component Side Pinout) A0 Multiplier-Accumulators 4 Through Package R18 R17 A2 A1 5 Top View R20 R19 A4 A3 6 R22 R21 A6 A5 7 LMA 1009/2009 R24 R23 A8 A7 8 03/29/2000–LDS.10/2009-L R26 R25 A9 A10 CLK A NC 9 OEX VCC B11 A11 NC 10 B0 CLK B B9 B7 B4 B2 B10 TC 11 B8 B6 B5 B3 B1 LMA 1009/2009 DEVICES INCORPORATED 12 x 12-bit Multiplier-Accumulator LMA2009 — ORDERING INFORMATION 68-pin OEX R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 OEM TC B11 B10 B9 B8 B7 B6 VCC NC VCC B5 B4 B3 B2 B1 B0 CLK B 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 Top View 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 CLK A A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ACC SUB RND OEL Speed 0°C to +70°C — COMMERCIAL SCREENING 45 ns 20 ns LMA2009JC45 LMA2009JC20 –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT PREL CLK R R11 R10 R9 R8 R7 NC R6 GND GND R5 R4 R3 R2 R1 R0 Plastic J-Lead Chip Carrier (J2) Multiplier-Accumulators 7 03/29/2000–LDS.10/2009-L
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