MTP12N10E

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP12N10E/D ™ Data Sheet TMOS E-FET.™ Power Field Effect Transistor Designer's MTP12N10E Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate This advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Designed to Eliminate the Need for External Zener Transient Suppressor — Absorbs High Energy in the Avalanche Mode • Commutating Safe Operating Area (CSOA) Specified for Use in Half and Full Bridge Circuits • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature TMOS POWER FET 12 AMPERES 100 VOLTS RDS(on) = 0.16 OHM ® D G S CASE 221A–06, Style 5 TO–220AB MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage — Continuous Gate–Source Voltage — Single Pulse (tp ≤ 50 µs) Drain Current — Continuous Drain Current — Single Pulse (tp ≤ 10 µs) Total Power Dissipation @ TC = 25°C Derate above 25°C Operating and Storage Temperature Range Symbol VDSS VDGR VGS ID IDM PD TJ, Tstg Value 100 100 ± 20 ± 40 12 30 79 0.53 – 55 to 175 Unit Vdc Vdc Vdc Adc Watts W/°C °C UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ ≤ 175°C) Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 V, VGS = 10 V, L = 4.03 mH, RG = 25 Ω, Peak IL = 12 A) (See Figures 15, 16 and 17) EAS 290 mJ THERMAL CHARACTERISTICS Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient° Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds RθJC RθJA TL 1.9 62.5 260 °C/W °C Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV 1 © Motorola TMOS Motorola, Inc. 1996 Power MOSFET Transistor Device Data 1 MTP12N10E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (VGS = 0, ID = 250 µAdc) Temperature Coefficient (positive) Zero Gate Voltage Drain Current (VDS = 100 V, VGS = 0)° (VDS = 100 V, VGS = 0, TJ = 150°C) Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) ON CHARACTERISTICS* Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Temperature Coefficient (negative)µ Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 6.0 Adc) Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 12 Adc)° (ID = 6.0 Adc, TJ = 150°C) Forward Transconductance (VDS ≥ 15 V, ID = 6.0 A) DYNAMIC CHARACTERISTICS Input Capacitance Reverse Transfer Capacitance Output Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) See Figure 14 Ciss Crss Coss — — — 600 70 230 — — — pF VGS(th) 2.0 — RDS(on) VDS(on) — — gFS 4.0 1.5 1.4 5.0 2.4 1.92 — mhos — 3.0 6.0 0.125 4.0 — 0.16 Vdc mV/°C Ohm Vdc V(BR)DSS 100 — IDSS — — IGSSF IGSSR — — — — — — 10 100 100 100 nAdc nAdc — 110 — — Vdc mV/°C µA Symbol Min Typ Max Unit SWITCHING CHARACTERISTICS (TJ = 100°C) Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time Gate Charge (VDS = 80 V, ID = 12 A, VGS = 10 Vdc) See Figures 5 and 6 (VDD = 50 V, ID = 12 A, VGS = 10 V, RG = 12 Ω) See Figure 7 td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE–DRAIN DIODE CHARACTERISTICS* Forward On–Voltage (IS = 12 A, VGS = 0) (IS = 12 A, VGS = 0, TJ = 150°C) (IS = 12 A, VGS = 0, dIS/dt = 100 A/µs, VR = 50 V) VSD — — trr — 1.0 0.83 110 2.5 — — ns Vdc — — — — — — — — 10 64 21 30 18 4.0 10 8.0 — — — — 26 — — — nC ns Reverse Recovery Time INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die)″ (Measured from the drain lead 0.25″ from package to center of die) Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) * Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%. Ld — — Ls — 3.5 4.5 7.5 — — — nH 2 Motorola TMOS Power MOSFET Transistor Device Data MTP12N10E TYPICAL ELECTRICAL CHARACTERISTICS 24 TJ = 25°C I D, DRAIN CURRENT (AMPS) 20 8V 16 7V 12 8 4 0 0 2 3 4 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 1 5 6V 5V VGS = 10 V 9V I D, DRAIN CURRENT (AMPS) 20 25°C 16 12 8 4 0 0 2 4 6 8 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 10 100°C 24 VDS ≥ 15 V TJ = –55°C Figure 1. On–Region Characteristics RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) Figure 2. Transfer Characteristics VGS = 10 V 0.5 0.4 0.3 0.2 0.1 0 0 3 6 9 12 15 18 ID, DRAIN CURRENT (AMPS) 21 24 TJ = 100°C 25°C –55°C RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 0.6 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 –50 –25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 175 VGS = 10 V ID = 6 A Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance Variation with Temperature +18 V VDD 1 mA SAME DEVICE TYPE AS DUT 16 VDS ID = 12 A VDS = 80 V TJ = 25°C 80 47 k Vin 15 V 2N3904 100 k 47 k 10 V 100 k 0.1 µF FERRITE BEAD 12 QT 8 Q1 VGS Q3 0 0 5 10 15 Qg, TOTAL GATE CHARGE (nC) 20 Q2 60 2N3904 40 100 DUT 4 20 Vin = 15 Vpk; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%. 0 25 Figure 5. Gate Charge Test Circuit Figure 6. Gate–To–Source and Drain–To–Source Voltage versus Gate Charge Motorola TMOS Power MOSFET Transistor Device Data 3 VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 20 100 MTP12N10E SAFE OPERATING AREA INFORMATION FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum drain–to–source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25°C and a maximum junction temperature of 175°C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, “Transient Thermal Resistance–General Data and Its Use” provides detailed instructions. SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) of Figure 9 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, I DM and the breakdown voltage, BVDSS. The switching SOA shown in Figure 9 is applicable for both turn– on and turn–off of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than: TJ(max) – TC RθJC 1000 VDD = 50 V ID = 12 A VGS = 10 V TJ = 25°C tr tf td(off) td(on) 100 t, TIME (ns) 10 1 10 100 RG, GATE RESISTANCE (OHMS) 1000 Figure 7. Resistive Switching Time versus Gate Resistance 40 I D, DRAIN CURRENT (AMPS) 1000 I D, DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25°C 100 µs 1 ms 100 OPERATION LIMITED IN THIS AREA BY RDS(on) 30 10 10 ms dc 20 TJ ≤ 175°C 10 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 100 0.1 0 0 20 40 60 80 100 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 120 Figure 8. Maximum Rated Forward Biased Safe Operating Area 1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 0.5 0.3 0.2 0.1 0.05 0.05 0.03 0.02 SINGLE PULSE 0.01 0.01 0.02 0.05 0.1 0.2 0.5 1 0.01 0.02 D = 0.5 Figure 9. Maximum Rated Switching Safe Operating Area 0.2 0.1 P(pk) RθJC(t) = r(t) RθJC RθJC = 1.9°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 50 100 200 500 1000 t2 DUTY CYCLE, D = t1/t2 2 t, TIME (ms) 5 10 20 t1 Figure 10. Thermal Response 4 Motorola TMOS Power MOSFET Transistor Device Data MTP12N10E COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure 12 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the source-drain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure 11 are present. Full or half-bridge PWM DC motor controllers are common applications requiring CSOA data. Device stresses increase with increasing rate of change of source current so dIs/dt is specified with a maximum value. Higher values of dIs/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIs/dt is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak drain–to–source voltage that the device must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of commutation. VR is specified at rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances in Motorola’s test circuit are assumed to be practical minimums. 15 V VGS 0 IFM 90% IS 10% ton IRM 0.25 IRM VDS(pk) VR VDS dVDS/dt VdsL MAX. CSOA STRESS AREA dls/dt trr Vf Figure 11. Commutating Waveforms 15 IS , SOURCE–TO–DRAIN CURRENT (AMPS) RGS TJ ≤ 175°C IS = 12 A dIs/dt ≤ 100 A/µs VR ≤ 100 V DUT 12 – VR + IFM + 20 V – IS VDS Li 9 6 3 VGS 0 0 20 40 60 80 100 120 140 160 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 180 200 VR = 80% OF RATED BVDSS VdsL = Vf + Li ⋅ dls/dt Figure 12. Commutating Safe Operating Area (CSOA) Figure 13. Commutating Safe Operating Area Test Circuit Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. 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Motorola TMOS Power MOSFET Transistor Device Data 5 MTP12N10E 2000 VDS = 0 V 1500 C, CAPACITANCE (pF) VGS = 0 V EAS , SINGLE PULSE AVALANCHE ENERGY (mJ) 300 250 200 PEAK IL = 12 A VDD = 25 V 1000 Ciss 500 Coss Crss 0 15 0 15 30 45 60 VGS VDS GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) 150 100 50 0 25 75 100 125 150 50 TJ, STARTING JUNCTION TEMPERATURE (°C) 175 Figure 14. Capacitance Variation Figure 15. Maximum Avalanche Energy versus Starting Junction Temperature BVDSS L VDS IL IL(t) VDD t RG VDD tP t, (TIME) Figure 16. Unclamped Inductive Switching Test Circuit Figure 17. Unclamped Inductive Switching Waveforms PACKAGE DIMENSIONS –T– B 4 SEATING PLANE DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ––– ––– 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ––– ––– 2.04 F T S C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. Q 123 A U K H Z L V G D N R J STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN CASE 221A–06 TO–220AB ISSUE Y How to reach us: USA / EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 6 ◊ Motorola TMOS Power MOSFET Transistor Device Data MTP12N10E/D *MTP12N10E/D*