MTP12P10G

MTP12P10 Preferred Device Power MOSFET 12 Amps, 100 Volts P−Channel TO−220 This Power MOSFET is designed for medium voltage, high speed power switching applications such as switching regulators, converters, solenoid and relay drivers. http://onsemi.com 12 AMPERES, 100 VOLTS RDS(on) = 300 mW Features • Silicon Gate for Fast Switching Speeds − Switching Times Specified • • • • P−Channel at 100°C Designer’s Data − IDSS, VDS(on), VGS(th) and SOA Specified at Elevated Temperature Rugged − SOA is Power Dissipation Limited Source−to−Drain Diode Characterized for Use With Inductive Loads Pb−Free Package is Available* D G S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−Source Voltage VDSS 100 Vdc Drain−Gate Voltage (RGS = 1.0 MW) VDGR 100 Vdc Gate−Source Voltage − Continuous − Non−repetitive (tp ≤ 50 ms) ± 20 ± 40 Vdc Vpk Drain Current − Continuous Drain Current − Pulsed ID IDM 12 28 Adc Total Power Dissipation Derate above 25°C PD 75 0.6 W W/°C TJ, Tstg −65 to 150 °C Thermal Resistance − Junction−to−Case − Junction−to−Ambient° Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds 4 Drain 4 VGS VGSM Operating and Storage Temperature Range MARKING DIAGRAM AND PIN ASSIGNMENT °C/W RqJC RqJA 1.67 62.5 TL 260 TO−220AB CASE 221A STYLE 5 1 2 MTP12P10G AYWW 3 1 Gate °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. MTP12P10 A Y WW G 2 Drain 3 Source = Device Code = Location Code = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 4 1 Package Shipping MTP12P10 TO−220AB 50 Units/Rail MTP12P10G TO−220AB (Pb−Free) 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MTP12P10/D MTP12P10 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)DSS 100 − Vdc − − 10 100 OFF CHARACTERISTICS Drain−Source Breakdown Voltage (VGS = 0, ID = 0.25 mA) mAdc Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0) (VDS = Rated VDSS, VGS = 0, TJ = 125°C) IDSS Gate−Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF − 100 nAdc Gate−Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR − 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) TJ = 100°C VGS(th) 2.0 1.5 4.5 4.0 Vdc Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 6.0 Adc) RDS(on) − 0.3 W Drain−Source On−Voltage (VGS = 10 V) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 100°C) VDS(on) − − 4.2 3.8 gFS 2.0 − mhos Ciss − 920 pF Coss − 575 Crss − 200 td(on) − 50 tr − 150 td(off) − 150 tf − 150 Qg 33 (Typ) 50 Qgs 16 (Typ) − Qgd 17 (Typ) − VSD 4.0 (Typ) 5.5 ON CHARACTERISTICS (Note 1) Forward Transconductance (VDS = 15 V, ID = 6.0 A) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) See Figure 10 Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 1) (TJ = 100°C) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 25 V, ID = 0.5 Rated ID, RG = 50 W) See Figures 12 and 13 Fall Time Total Gate Charge Gate−Source Charge (VDS = 0.8 Rated VDSS, ID = Rated ID, VGS = 10 V) See Figure 11 Gate−Drain Charge ns nC SOURCE−DRAIN DIODE CHARACTERISTICS (Note 1) Forward On−Voltage Forward Turn−On Time Vdc ton Limited by stray inductance trr 300 (Typ) − ns Internal Drain Inductance, (Measured from the contact screw on the header closer to the source pin and the center of the die) Ld 5.0 (Typ) − nH Internal Source Inductance (Measured from the source pin, 0.25″ from the package to the source bond pad) Ls 12.5 (Typ) − 3.5 (Typ) 4.5 (Typ) − − 7.5 (Typ) − (IS = Rated ID, VGS = 0) Reverse Recovery Time INTERNAL PACKAGE INDUCTANCE (TO−204) INTERNAL PACKAGE INDUCTANCE (TO−220) Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) Ld Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) Ls 1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. http://onsemi.com 2 nH MTP12P10 20 VGS = −20 V −I D, DRAIN CURRENT (AMPS) 18 16 VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED) TYPICAL ELECTRICAL CHARACTERISTICS 10 V TJ = 25°C 8V 14 12 7V 10 8 6V 6 4 5V 2 0 0 1 2 3 4 5 6 7 8 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 9 10 1.2 1 0.9 0.8 −50 I D, DRAIN CURRENT (AMPS) 25°C 16 TJ = −55°C 100°C 12 8 VDS = 20 V 4 0 0 4 8 12 16 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 20 1.6 RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) TJ = 100°C 25°C −55°C 0.1 0 0 4 8 12 16 20 24 28 32 VGS = 0 ID = 0.25 mA 1.2 0.8 0.4 0 −50 −75 0 25 50 75 100 125 150 Figure 4. Normalized Breakdown Voltage versus Temperature 0.4 0.2 125 TJ, JUNCTION TEMPERATURE (°C) 0.5 0.3 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 2 Figure 3. Transfer Characteristics VGS = 15 V −25 Figure 2. Gate−Threshold Voltage Variation With Temperature VBR(DSS), DRAIN−TO−SOURCE BREAKDOWN VOLTAGE (NORMALIZED) Figure 1. On−Region Characteristics 20 VDS = VGS ID = 1 mA 1.1 36 1.8 1.4 1.2 1 0.8 0.6 0.4 0.2 0 −50 40 VGS = 10 V ID = 6 A 1.6 −25 0 25 50 75 100 125 150 ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance versus Drain Current Figure 6. On−Resistance Variation With Temperature http://onsemi.com 3 150 MTP12P10 SAFE OPERATING AREA INFORMATION 50 1 ms 10 I D, DRAIN CURRENT (AMPS) I D, DRAIN CURRENT (AMPS) 10 ms 0.1 ms 10 ms VGS = 20 V SINGLE PULSE TC = 25°C dc MTM/MTP12P06 RDS(on) LIMIT PACKAGE LIMIT THERMAL LIMIT MTM/MTP12P10 1 40 30 20 MTM/MTP12P06 10 MTM/MTP12P10 0 10 1 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0 Figure 7. Maximum Rated Forward Biased Safe Operating Area 10 30 50 70 20 40 60 80 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 90 100 Figure 8. Maximum Rated Switching Safe Operating Area FORWARD BIASED SAFE OPERATING AREA SWITCHING SAFE OPERATING AREA The FBSOA curves define the maximum drain−to−source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, “Transient Thermal Resistance−General Data and Its Use” provides detailed instructions. The switching safe operating area (SOA) of Figure 8 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn−on and turn−off of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than: TJ(max) − TC RqJC r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.5 0.3 0.2 0.2 0.1 0.1 P(pk) 0.05 0.05 0.02 0.03 t1 0.02 t2 DUTY CYCLE, D = t1/t2 0.01 SINGLE PULSE 0.01 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 t, TIME (ms) 10 Figure 9. Thermal Response http://onsemi.com 4 20 RqJC(t) = r(t) RqJC RqJC = 1.67°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 50 100 200 500 1000 MTP12P10 0 VGS, GATE SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) 1600 TC = 25°C VGS = 0 f = 1 MHz 1200 Ciss 800 Coss 400 Crss 0 0 10 30 20 VDS, SOURCE−TO−DRAIN VOLTAGE (VOLTS) −4 −6 −8 −10 VDS = 30 V −12 50 V −14 −16 40 TJ = 25°C ID = 12 A −2 80 V 0 5 10 15 20 25 30 35 40 45 Qg, TOTAL GATE CHARGE (nC) Figure 10. Capacitance Variation Figure 11. Gate Charge versus Gate−To−Source Voltage RESISTIVE SWITCHING VDD ton toff td(on) RL tr Vin Rgen 50 W 90% OUTPUT, Vout DUT z = 50 W tf 90% Vout PULSE GENERATOR td(off) 10% 90% 50 W INPUT, Vin INVERTED Figure 12. Switching Test Circuit 50% 50% 10% PULSE WIDTH Figure 13. Switching Waveforms http://onsemi.com 5 50 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220 CASE 221A ISSUE AK DATE 13 JAN 2022 SCALE 1:1 STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. BASE EMITTER COLLECTOR EMITTER STYLE 3: PIN 1. 2. 3. 4. CATHODE ANODE GATE ANODE STYLE 4: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE MAIN TERMINAL 2 STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 6: PIN 1. 2. 3. 4. ANODE CATHODE ANODE CATHODE STYLE 7: PIN 1. 2. 3. 4. CATHODE ANODE CATHODE ANODE STYLE 8: PIN 1. 2. 3. 4. CATHODE ANODE EXTERNAL TRIP/DELAY ANODE STYLE 9: PIN 1. 2. 3. 4. GATE COLLECTOR EMITTER COLLECTOR STYLE 10: PIN 1. 2. 3. 4. GATE SOURCE DRAIN SOURCE STYLE 11: PIN 1. 2. 3. 4. DRAIN SOURCE GATE SOURCE STYLE 12: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE NOT CONNECTED DOCUMENT NUMBER: DESCRIPTION: 98ASB42148B TO−220 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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