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N-Channel PowerTrench® MOSFET
150V, 29A, 54mΩ
Features
Applications
• r DS(ON) = 45mΩ (Typ.), VGS = 10V, ID = 9A
• DC/DC converters and Off-Line UPS
• Qg(tot) = 26nC (Typ.), VGS = 10V
• Distributed Power Architectures and VRMs
• Low Miller Charge
• Primary Switch for 24V and 48V Systems
• Low QRR Body Diode
• UIS Capability (Single Pulse and Repetitive Pulse)
• High Voltage Synchronous Rectifier
Formerly developmental type 82860
D
DRAIN
(FLANGE)
GATE
SOURCE
G
TO-263AB
FDB SERIES
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
150
Units
V
VGS
Gate to Source Voltage
±20
V
Continuous (TC = 25oC, VGS = 10V)
29
A
Continuous (TC = 100oC, VGS = 10V)
20
A
4
A
Drain Current
ID
Continuous (Tamb = 25oC, VGS = 10V, R θJA = 43oC/W)
Pulsed
E AS
PD
TJ, TSTG
Figure 4
A
Single Pulse Avalanche Energy (Note 1)
36
mJ
Power dissipation
135
W
Derate above 25oC
0.9
W/oC
Operating and Storage Temperature
o
-55 to 175
C
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case, TO-263
RθJA
Thermal Resistance Junction to Ambient , TO-263
RθJA
(Note 2)
2
Thermal Resistance Junction to Ambient TO-263, 1in copper pad area
©2012 Fairchild Semiconductor Corporation
1.11
o
C/W
62
o
C/W
43
o
C/W
FDB2572 Rev. C
FDB2572
January 2012
FDB2572
Device Marking
FDB2572
Device
FDB2572
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
150
-
-
V
-
-
1
-
-
250
µA
VGS = ±20V
-
-
±100
nA
V GS = VDS, ID = 250µA
2
-
4
V
ID=9A, VGS=10V
-
0.045
0.054
ID = 4A, VGS = 6V,
-
0.050
0.075
ID=9A, VGS=10V, TC=175oC
-
0.126
0.146
-
1770
-
-
183
-
pF
-
40
-
pF
nC
VDS = 120V
VGS = 0V
TC = 150o
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
VDS = 25V, VGS = 0V,
f = 1MHz
pF
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
-
26
34
Qg(TH)
Threshold Gate Charge
VGS = 0V to 2V
-
3.3
4.3
nC
Qgs
Gate to Source Gate Charge
-
8
-
nC
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
VDD = 75V
ID = 9A
Ig = 1.0mA
-
5
-
nC
-
6
-
nC
ns
Resistive Switching Characteristics (VGS = 10V)
tON
Turn-On Time
-
-
36
td(ON)
Turn-On Delay Time
-
11
-
ns
tr
Rise Time
-
14
-
ns
td(OFF)
Turn-Off Delay Time
-
31
-
ns
tf
Fall Time
-
14
-
ns
tOFF
Turn-Off Time
-
-
66
ns
VDD = 75V, ID = 9A
VGS = 10V, RGS = 11.0Ω
Drain-Source Diode Characteristics
ISD = 9A
-
-
1.25
V
ISD = 4A
-
-
1.0
V
Reverse Recovery Time
ISD = 9A, dISD/dt =100A/µs
-
-
74
ns
Reverse Recovered Charge
ISD = 9A, dISD/dt =100A/µs
-
-
169
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting TJ = 25°C, L = 0.2mH, IAS = 19A.
2: Pulse Width = 100s
©2012 Fairchild Semiconductor Corporation
FDB2572 Rev. C
FDB2572
Package Marking and Ordering Information
FDB2572
Typical Characteristics TC = 25°C unless otherwise noted
40
VGS = 10V
35
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
30
25
20
15
10
0.2
5
0
0
25
50
75
100
150
125
175
0
25
TC , CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
50
75
100
125
TC, CASE TEMPERATURE (oC)
150
175
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2.0
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1.0
PDM
0.1
SINGLE PULSE
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5
10-4
10-3
10-2
10-1
t , RECTANGULAR PULSE DURATION (s)
100
101
Figure 3. Normalized Maximum Transient Thermal Impedance
500
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
175 - TC
I = I25
150
100
VGS = 10V
20
10-5
10-4
10-3
10-2
t , PULSE WIDTH (s)
10-1
100
101
Figure 4. Peak Current Capability
©2012 Fairchild Semiconductor Corporation
FDB2572 Rev. C
FDB2572
Typical Characteristics TC = 25°C unless otherwise noted
100
1000
STARTING TJ = 25oC
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
10µs
100
100µs
1ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
1
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
DC
STARTING TJ = 150oC
1
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0.1
0.1
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
0.001
200
1
Figure 6. Unclamped Inductive Switching
Capability
60
60
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TC = 25oC
40
TJ = 175o C
30
TJ = 25o C
20
VGS = 10V
50
ID, DRAIN CURRENT (A)
50
TJ = -55oC
10
40
VGS = 7V
VGS = 6V
30
VGS = 5V
20
10
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VGS , GATE TO SOURCE VOLTAGE (V)
0
6.5
Figure 7. Transfer Characteristics
1
2
3
4
VDS , DRAIN TO SOURCE VOLTAGE (V)
5
Figure 8. Saturation Characteristics
3.0
60
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE (m Ω)
0.01
0.1
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Forward Bias Safe Operating Area
ID , DRAIN CURRENT (A)
10
VGS = 6V
55
50
VGS = 10V
45
40
2.5
2.0
1.5
1.0
0.5
VGS = 10V, ID =9A
0
0
10
20
30
ID, DRAIN CURRENT (A)
Figure 9. Drain to Source On Resistance vs Drain
Current
©2012 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
FDB2572 Rev. C
FDB2572
Typical Characteristics TC = 25°C unless otherwise noted
1.2
1.4
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
1.0
0.8
0.6
0.4
1.1
1.0
0.9
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
200
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
1000
10
1000
C, CAPACITANCE (pF)
VGS , GATE TO SOURCE VOLTAGE (V)
VDD = 75V
CISS = CGS + CGD
COSS ≅ CDS + C GD
CRSS = CGD
100
VGS = 0V, f = 1MHz
10
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 9A
ID = 4A
2
0
0.1
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source
Voltage
©2012 Fairchild Semiconductor Corporation
150
0
5
10
15
20
Qg , GATE CHARGE (nC)
25
30
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
FDB2572 Rev. C
FDB2572
Test Circuits and Waveforms
BVDSS
VDS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
+
RG
REQUIRED PEAK IAS
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS = 10V
VGS
+
VDD
VGS
-
VGS = 2V
DUT
Qgs2
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2012 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
FDB2572 Rev. C
FDB2572
Thermal Resistance vs. Mounting Pad Area
(T
–T )
JM
A
P D M = ----------------------------R θ JA
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P DM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
80
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA = 26.51+ 128/(1.69+Area) EQ.3
60
RθJA (oC/W)
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
40
20
0.1
1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2)
(64.5)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
R
θ JA
19.84
( 0.262 + Area )
= 26.51 + -------------------------------------
(EQ. 2)
Area in Inches Squared
R
θ JA
128
( 1.69 + Area )
= 26.51 + ----------------------------------
(EQ. 3)
Area in Centimeters Squared
©2012 Fairchild Semiconductor Corporation
FDB2572 Rev. C
rev April 2002
LDRAIN
DPLCAP
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RSLC2
5
51
EVTHRES
+ 19 8
+
LGATE
GATE
1
ESLC
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
Lgate 1 9 9.56e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 7.71e-9
RLDRAIN
RSLC1
51
Ebreak 11 7 17 18 160
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
DRAIN
2
5
EVTEMP
RGATE +
18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
7
RSOURCE
RLgate 1 9 95.6
RLdrain 2 5 10
RLsource 3 7 77.1
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
13
8
S1B
CA
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 35e-3
Rgate 9 20 1.6
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 3.0e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
17
18
RVTEMP
S2B
13
CB
6
8
5
8
EDS
-
19
VBAT
+
IT
14
+
+
EGS
RLSOURCE
RBREAK
15
14
13
SOURCE
3
-
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*52),3))}
.MODEL DbodyMOD D (IS=6.0E-11 N=1.14 RS=3.9e-3 TRS1=3.5e-3 TRS2=3.0e-6
+ CJO=1.1e-9 M=0.63 TT=6.2e-8 XTI=4.5)
.MODEL DbreakMOD D (RS=10 TRS1=5.0e-3 TRS2=-5.0e-6)
.MODEL DplcapMOD D (CJO=3.5e-10 IS=1.0e-30 N=10 M=0.65)
.MODEL MmedMOD NMOS (VTO=3.55 KP=3 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=1.6)
.MODEL MstroMOD NMOS (VTO=4.0 KP=25 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.95 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=16 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.15e-3 TC2=-9.5e-7)
.MODEL RdrainMOD RES (TC1=9.0e-3 TC2=2.5e-5)
.MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.5e-6)
.MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6)
.MODEL RvthresMOD RES (TC1=-4.1e-3 TC2=-1.0e-5)
.MODEL RvtempMOD RES (TC1=-4.0e-3 TC2=1.0e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-3.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-5.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2012 Fairchild Semiconductor Corporation
FDB2572 Rev. C
FDB2572
PSPICE Electrical Model
.SUBCKT FDB2572 2 1 3 ;
CA 12 8 5.5e-10
Cb 15 14 7.4e-10
Cin 6 8 1.7e-9
EVTHRES
+ 19 8
+
LGATE
spe.ebreak n11 n7 n17 n18 = 160 GATE
1
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RDRAIN
6
8
ESG
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
8
LSOURCE
SOURCE
3
7
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
12
l.lgate n1 n9 = 9.56e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 7.71e-9
S2A
S1B
CA
res.rlgate n1 n9 = 95.6
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 77.1
15
14
13
13
8
RBREAK
17
18
RVTEMP
S2B
13
CB
+
-
IT
14
+
6
8
EGS
19
VBAT
5
8
EDS
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.15e-3,tc2=-9.5e-7
res.rdrain n50 n16 = 35e-3, tc1=9.0e-3,tc2=2.5e-5
res.rgate n9 n20 = 1.6
res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=2.5e-6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7 = 3.0e-3, tc1=4.0e-3,tc2=1.0e-6
res.rvthres n22 n8 = 1, tc1=-4.1e-3,tc2=-1.0e-5
res.rvtemp n18 n19 = 1, tc1=-4.0e-3,tc2=1.0e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/52))** 3))}
}
©2012 Fairchild Semiconductor Corporation
FDB2572 Rev. C
FDB2572
SABER Electrical Model
REV April 2002
ttemplate FDB2572 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=6.0e-11,nl=1.14,rs=3.9e-3,trs1=3.5e-3,trs2=3.0e-6,cjo=1.1e-9,m=0.63,tt=6.2e-8,xti=4.5)
dp..model dbreakmod = (rs=10,trs1=5.0e-3,trs2=-5.0e-6)
dp..model dplcapmod = (cjo=3.5e-10,isl=10.0e-30,nl=10,m=0.65)
m..model mmedmod = (type=_n,vto=3.55,kp=3,is=1e-40, tox=1)
m..model mstrongmod = (type=_n,vto=4.0,kp=25,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.95,kp=0.05,is=1e-30, tox=1,rs=0.1)
LDRAIN
DPLCAP 5
DRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5.0,voff=-3.5)
2
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-5.0) 10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.3)
RLDRAIN
RSLC1
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.5)
51
c.ca n12 n8 = 5.5e-10
RSLC2
c.cb n15 n14 = 7.4e-10
ISCL
c.cin n6 n8 = 1.7e-9
th
FDB2572
SPICE Thermal Model
JUNCTION
REV 26 April 2002
FDB2572
CTHERM1 TH 6 3.8e-3
CTHERM2 6 5 4.0e-3
CTHERM3 5 4 4.2e-3
CTHERM4 4 3 4.3e-3
CTHERM5 3 2 8.5e-3
CTHERM6 2 TL 3.0e-2
CTHERM1
RTHERM1
6
RTHERM1 TH 6 5.5e-4
RTHERM2 6 5 5.0e-3
RTHERM3 5 4 4.5e-2
RTHERM4 4 3 10.5e-2
RTHERM5 3 2 3.7e-1
RTHERM6 2 TL 3.8e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDB2572
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3.8e-3
ctherm.ctherm2 6 5 =4.0e-3
ctherm.ctherm3 5 4 =4.2e-3
ctherm.ctherm4 4 3 =4.3e-3
ctherm.ctherm5 3 2 =8.5e-3
ctherm.ctherm6 2 tl =3.0e-2
rtherm.rtherm1 th 6 =5.5e-4
rtherm.rtherm2 6 5 =5.0e-3
rtherm.rtherm3 5 4 =4.5e-2
rtherm.rtherm4 4 3 =10.5e-2
rtherm.rtherm5 3 2 =3.7e-1
rtherm.rtherm6 2 tl =3.8e-1
}
CTHERM3
RTHERM3
4
CTHERM4
RTHERM4
3
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
tl
©2012 Fairchild Semiconductor Corporation
CASE
FDB2572 Rev. C
FDB2572
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Rev. I61
©2012 Fairchild Semiconductor Corporation
FDB2572 Rev. C
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