MM54HC190

MM54HC190 MM74HC190 MM54HC191 MM74HC191 January 1988 MM54HC190 MM74HC190 Synchronous Decade Up Down Counters with Mode Control MM54HC191 MM74HC191 Synchronous Binary Up Down Counters with Mode Control General Description These high speed synchronous counters utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power consumption of CMOS technology along with the speeds of low power Schottky TTL These circuits are synchronous reversible up down counters The MM54HC191 MM74HC191 are 4-bit binary counters and the MM54HC190 MM74HC190 are BCD counters Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously when so instructed by the steering logic This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters The outputs of the four master-slave flip-flops are triggered on a low-to-high level transition of the clock input if the enable input is low A high at the enable input inhibits counting The direction of the count is determined by the level of the down up input When low the counter counts up and when high it counts down These counters are fully programmable that is the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs The output will change independent of the level of the clock input This feature allows the counters to be used as moduloN dividers by simply modifying the count length with the preset inputs Two outputs have been made available to perform the cascading function ripple clock and maximum minimum count The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used or to the clock input if parallel enabling is used The maximum minimum count output can be used to accomplish look-ahead for high-speed operation Features Y Y Y Y Level changes on Enable or Down Up can be made regardless of the level of the clock input Wide power supply range 2 – 6V Low quiescent supply current 80 mA maximum (74HC Series) Low input current 1 mA maximum Connection Diagram Dual-In-Line Package Load H H L H Enable G L L X H Down Up L H X X Clock Function Count Up Count Down Load No Change u u X X Asynchronous inputs Low input to load sets QA e A QB e B QC e C and QD e D Order Number MM54HC190 191 or MM74HC190 191 TL F 5322 – 1 Top View C1995 National Semiconductor Corporation TL F 5322 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) b 0 5 to a 7 0V b 1 5 to VCC a 1 5V DC Input Voltage (VIN) b 0 5 to VCC a 0 5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK IOK) g 25 mA DC Output Current per pin (IOUT) g 50 mA DC VCC or GND Current per pin (ICC) b 65 C to a 150 C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S O Package only 500 mW Lead Temp (TL) (Soldering 10 seconds) 260 C Operating Conditions Supply Voltage (VCC) DC Input or Output Voltage (VIN VOUT) Operating Temp Range (TA) MM74HC MM54HC Input Rise or Fall Times VCC e 2 0V (tr tf) VCC e 4 5V VCC e 6 0V Min 2 0 Max 6 VCC Units V V b 40 b 55 a 85 a 125 C C ns ns ns 1000 500 400 DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC V V V V V V VIN e VIH or VIL lIOUTl s mA V V V V V V V V V V V V g g g TA e 25 C Typ 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units Guaranteed Limits V V V V V V V V V V V V V V V V mA mA VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VIL VOH VIN e VIH or VIL lIOUTl s mA lIOUTl s mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s mA VIN e VIH or VIL lIOUTl s mA lIOUTl s mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN e VCC or GND VIN e VCC or GND IOUT e mA Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b 12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b 12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89 2 AC Electrical Characteristics TA e 25 C Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tW Parameter Maximum Clock Frequency Maximum Propagation Delay Time Maximum Propagation Delay Time Maximum Propagation Delay Time Maximum Propagation Delay Time Maximum Propagation Delay Time Maximum Propagation Delay Time Maximum Propagation Delay Time Maximum Propagation Delay Time Minimum Clock Clear or Load Input Pulse Width VCC e 5 0V tr e tf e 6 ns CL e 15 pF (unless otherwise specified) From (Input) To (Output) Typ Units MHz Load Data A BCD Clock Clock Clock Down Up Down Up Enable QA QB QC QD QA QB QC QD Ripple Clock QA QB QC QD Max Min Ripple Clock Max Min Ripple Clock ns ns ns ns ns ns ns ns ns AC Electrical Characteristics VCC e 2 0V to 6 0V Symbol Parameter From (Input) To (Output) VCC CL e 50 pF tr e tf e 6 ns (unless otherwise specified) 74HC TA e b40 to 85 C 54HC TA eb55 to 125 C Units TA e 25 C Typ Guaranteed Limits MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns fMAX Maximum Clock Frequency Maximum Propagation Delay Time Maximum Propagation Delay Time Maximum Propagation Delay Time Maximum Propagation Delay Time Load QA QB QC QD QA QB QC QD Ripple Clock QA QB QC QD V V V V V V V V V V V V V V V tPLH tPHL tPLH tPHL Data A BCD Clock tPLH tPHL tPLH tPHL Clock 3 AC Electrical Characteristics (Continued) Symbol Parameter From (Input) Clock 74HC 54HC TA e 25 C To Conditions VCC TA eb40 to 85 C TA eb55 to 125 C Units (Output) Typ Guaranteed Limits Max Min V V V V V V V V V V V V V V V Data Load V V V Vb Vb Vb V V V Vb Vb Vb V V V Vb Vb Vb V V V V V V V V V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns pF pF tPLH tPHL Maximum Propagation Delay Time tPLH tPHL Maximum Propagation Delay Time tPLH tPHL Maximum Propagation Delay Time tPHL tPLH Maximum Propagation Delay Time tW Minimum Clock Load or Clear Input Pulse Width Minimum Setup Time Down Up Ripple Clock Down Up Max Min Enable Ripple Clock tS tH Data Hold Time Load Data tS Minimum Setup Time Down Up Clock tH Minimum Hold Time Clock Down Up tS Minimum Setup Time Enable Clock tH Minimum Hold Time Clock Enable trem Minimum Removal Time Load Clock tTHL tTLH Maximum Output Rise and Fall Time tW Minimum Load Pulse Width Input Capacitance Power Dissipation Capacitance Note CIN CPD Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC 4 Logic Diagrams ’HC190 Decade Counters Pin (16) e VCC Pin (8) e GND TL F 5322 – 2 5 Logic Diagrams (Continued) ’HC191 Binary Counters TL F 5322 – 3 Pin (16) e VCC Pin (8) e GND 6 Timing Diagrams ’HC190 Synchronous Decade Counters Typical Load Count and Inhibit Sequences TL F 5322 – 4 Sequence (1) Load (preset) to BCD seven (2) Count up to eight nine zero one and two (3) Inhibit (4) Count down to one zero nine eight and seven ’HC191 Synchronous Binary Counters Typical Load Count and Inhibit Sequence TL F 5322 – 5 Sequence (1) Load (preset) to binary thirteen (2) Count up to fourteen fifteen zero one and two (3) Inhibit (4) Count down to one zero fifteen fourteen and thirteen 7 MM54HC190 MM74HC190 MM54HC191 MM74HC191 Physical Dimensions inches (millimeters) Order Number MM54HC190J MM54HC191J MM74HC190J or MM74HC191J NS Package J16A Order Number MM74HC190N or MM74HC191N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications