74LVC1GU04GV

74LVC1GU04 Inverter Rev. 08 — 12 June 2007 Product data sheet 1. General description The 74LVC1GU04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. The 74LVC1GU04 provides the inverting single state unbuffered function. 2. Features I I I I I I I I Wide supply voltage range from 1.65 V to 5.5 V High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Input accepts voltages up to 5 V Multiple package options ESD protection: N HBM JESD22-A114-D exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range 74LVC1GU04GW 74LVC1GU04GV 74LVC1GU04GM 74LVC1GU04GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name TSSOP5 SC-74A XSON6 XSON6 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm plastic surface-mounted package; 5 leads plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1 × 0.5 mm Version SOT353-1 SOT753 SOT886 SOT891 Type number NXP Semiconductors 74LVC1GU04 Inverter 4. Marking Table 2. Marking codes Marking VD VU4 VD VD Type number 74LVC1GU04GW 74LVC1GU04GV 74LVC1GU04GM 74LVC1GU04GF 5. Functional diagram VCC VCC 100 Ω A 2 A Y 4 2 1 4 Y mna108 mna109 mna636 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74LVC1GU04 74LVC1GU04 n.c. A 1 2 GND GND 3 001aab666 n.c. 5 VCC 1 6 VCC n.c. A 74LVC1GU04 1 2 3 6 5 4 VCC n.c. Y A 2 5 n.c. 3 4 Y GND 4 Y 001aab667 001aaf411 Transparent top view Transparent top view Fig 4. Pin configuration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 2 of 15 NXP Semiconductors 74LVC1GU04 Inverter 6.2 Pin description Table 3. Symbol n.c. A GND Y n.c. VCC Pin description Pin SOT353-1/SOT753 1 2 3 4 5 SOT886/SOT891 1 2 3 4 5 6 not connected data input A ground (0 V) data output Y not connected supply voltage Description 7. Functional description Table 4. Input (A) L H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output (Y) H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Ptot Tstg [1] [2] [3] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current total power dissipation storage temperature Conditions VI < 0 V [1] Min −0.5 −0.5 [1][2] Max +6.5 −50 +6.5 ±50 VCC + 0.5 ±50 +100 −100 250 +150 Unit V mA V mA V mA mA mA mW °C VO > VCC or VO < 0 V Active mode VO = 0 V to VCC −0.5 - Tamb = −40 °C to +125 °C [3] −65 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 3 of 15 NXP Semiconductors 74LVC1GU04 Inverter 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V Active mode Conditions Min 1.65 0 0 −40 0 0 Typ Max 5.5 5.5 VCC +125 20 10 Unit V V V °C ns/V ns/V 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage VCC = 1.65 V to 5.5 V VCC = 1.65 V to 5.5 V IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II ICC CI input leakage current supply current input capacitance VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V VCC = 3.3 V; VI = GND to VCC ±0.1 0.1 6 0.1 0.45 0.3 0.4 0.55 0.55 ±5 10 V V V V V V µA µA pF 0.75 × VCC VCC − 0.1 1.2 1.9 2.2 2.3 3.8 0.25 × VCC V V V V V V V V Conditions Min Typ[1] Max Unit HIGH-level output voltage VI = VIH or VIL 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 4 of 15 NXP Semiconductors 74LVC1GU04 Inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage VCC = 1.65 V to 5.5 V VCC = 1.65 V to 5.5 V IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II ICC input leakage current supply current VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V ±0.1 0.1 0.7 0.45 0.6 0.80 0.80 ±5 200 V V V V V V µA µA 0.8 × VCC VCC − 0.1 0.95 1.7 1.9 2.0 3.4 0.2 × VCC V V V V V V V V Conditions Min Typ[1] Max Unit HIGH-level output voltage VI = VIH or VIL [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10. Symbol Parameter tpd Conditions [2] −40 °C to +85 °C Min Typ[1] 1.7 1.3 1.7 1.6 1.3 Max 5.0 4.0 5.0 3.7 3.0 −40 °C to +125 °C Unit Min 0.3 0.3 0.5 0.5 0.5 Max 6.5 5.5 6.5 5.0 4.0 ns ns ns ns ns propagation delay A to Y; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 0.3 0.3 0.5 0.5 0.5 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 5 of 15 NXP Semiconductors 74LVC1GU04 Inverter Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10. Symbol Parameter CPD power dissipation capacitance Conditions VI = GND to VCC; VCC = 3.3 V [3] −40 °C to +85 °C Min Typ[1] 14.9 Max - −40 °C to +125 °C Unit Min Max pF [1] [2] [3] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 12. Waveforms VI A input GND t PHL VOH Y output VOL VM mna637 VM t PLH Measurement points are given in Table 9. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The input A to output Y propagation delay times Table 9. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC Output VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC Supply voltage 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 6 of 15 NXP Semiconductors 74LVC1GU04 Inverter 120 Gfs (mA/V) 100 mna639 Rbias = 560 kΩ VCC 80 60 0.47 µF VI input output 100 µF 40 A IO mna638 20 0 0 2 4 VCC (V) 6 Tamb = 25 °C. ∆I o G fs = -------∆V i fi = 1 kHz at VO is constant Fig 8. Typical forward transconductance as a function of supply voltage Fig 9. Test set-up for measuring forward transconductance VEXT VCC PULSE GENERATOR VI DUT RT CL RL RL VO mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 10. Load circuitry for switching times Table 10. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V Test data Input VI VCC VCC tr = t f ≤ 2.0 ns ≤ 2.0 ns Load CL 30 pF 30 pF RL 1 kΩ 500 Ω VEXT tPLH, tPHL open open Supply voltage 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 7 of 15 NXP Semiconductors 74LVC1GU04 Inverter Table 10. VCC 2.7 V Test data …continued Input VI 2.7 V 2.7 V VCC tr = t f ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 50 pF 50 pF 50 pF RL 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open Supply voltage 3.0 V to 3.6 V 4.5 V to 5.5 V 13. Application information Some applications are: • Linear amplifier (see Figure 11) • In crystal oscillator design (see Figure 12) Remark: All values given are typical unless otherwise specified. R2 R1 VCC 1 µF R2 R1 U04 ZL U04 C1 C2 out mna052 mna053 Vo(p-p) = VCC − 1.5 V centered at 0.5VCC. C1 = 47 pF (typ.) C2 = 22 pF (typ.) R1 = 1 MΩ to 10 MΩ (typ.) R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC is typically 2 mA at VCC = 3.3 V and f = 10 MHz). A OL A u = – ----------------------------------------R1 1 + ------ ( 1 + A OL ) R2 AOL = open loop amplification. Au = voltage amplification. R1 ≥ 3 kΩ, R2 ≤ 1 MΩ ZL > 10 kΩ; AOL = 20 (typ.) Typical unity gain bandwidth product is 5 MHz. Fig 11. Used as a linear amplifier Fig 12. Crystal oscillator configuration 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 8 of 15 NXP Semiconductors 74LVC1GU04 Inverter 14. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 D E A X c y HE vMA Z 5 4 A2 A1 (A3) θ A 1 e e1 bp 3 wM detail X Lp L 0 1.5 scale 3 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.1 0 A2 1.0 0.8 A3 0.15 bp 0.30 0.15 c 0.25 0.08 D(1) 2.25 1.85 E(1) 1.35 1.15 e 0.65 e1 1.3 HE 2.25 2.0 L 0.425 Lp 0.46 0.21 v 0.3 w 0.1 y 0.1 Z(1) 0.60 0.15 θ 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC MO-203 JEITA SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 13. Package outline SOT353-1 (TSSOP5) 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 9 of 15 NXP Semiconductors 74LVC1GU04 Inverter Plastic surface-mounted package; 5 leads SOT753 D B E A X y HE vMA 5 4 Q A A1 c 1 2 3 detail X Lp e bp wM B 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.100 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT753 REFERENCES IEC JEDEC JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Fig 14. Package outline SOT753 (SC-74A) 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 10 of 15 NXP Semiconductors 74LVC1GU04 Inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 15. Package outline SOT886 (XSON6) 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 11 of 15 NXP Semiconductors 74LVC1GU04 Inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 4× (1) L1 e L 6 e1 5 e1 4 6× (1) A A1 D E terminal 1 index area 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 2 mm Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 Fig 16. Package outline SOT891 (XSON6) 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 12 of 15 NXP Semiconductors 74LVC1GU04 Inverter 15. Abbreviations Table 11. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 16. Revision history Table 12. Revision history Release date 20070612 Data sheet status Product data sheet Product data sheet Change notice Supersedes 74LVC1GU04_7 74LVC1GU04_6 Document ID 74LVC1GU04_8 Modifications: 74LVC1GU04_7 Modifications: • • • • The general description has been changed. The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74LVC1GU04GF (XSON6/SOT891 package). Product specification Product specification Product specification Product specification Product specification Product specification 74LVC1GU04_5 74LVC1GU04_4 74LVC1GU04_3 74LVC1GU04_2 74LVC1GU04_1 - 20061006 74LVC1GU04_6 74LVC1GU04_5 74LVC1GU04_4 74LVC1GU04_3 74LVC1GU04_2 74LVC1GU04_1 20040921 20040628 20030630 20030212 20010406 20001212 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 13 of 15 NXP Semiconductors 74LVC1GU04 Inverter 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVC1GU04_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 12 June 2007 14 of 15 NXP Semiconductors 74LVC1GU04 Inverter 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 June 2007 Document identifier: 74LVC1GU04_8