BUK7605-30A

Philips Semiconductors Product specification TrenchMOS™ transistor Standard level FET GENERAL DESCRIPTION N-channel enhancement mode standard level field-effect power transistor in a plastic envelope suitable for surface mounting. Using ’trench’ technology the device features very low on-state resistance. It is intended for use in automotive and general purpose switching applications. BUK7605-30A QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 10 V MAX. 30 75 230 175 5 UNIT V A W ˚C mΩ PINNING - SOT404 PIN 1 2 3 mb gate drain (no connection possible) source drain DESCRIPTION PIN CONFIGURATION mb SYMBOL d g 2 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 30 30 20 75 75 400 230 175 UNIT V V V A A A W ˚C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS Minimum footprint, FR4 board TYP. 50 MAX. 0.65 UNIT K/W K/W August 1999 1 Rev 1.100 Philips Semiconductors Product specification TrenchMOS™ transistor Standard level FET STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C VDS = 30 V; VGS = 0 V; VGS = ±20 V; VDS = 0 V VGS = 10 V; ID = 25 A Tj = 175˚C Tj = 175˚C MIN. 30 27 2 1 - BUK7605-30A TYP. 3.0 0.05 2 4.3 - MAX. 4.0 4.4 10 500 100 5 9.3 UNIT V V V V V µA µA nA mΩ mΩ DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL Ciss Coss Crss td on tr td off tf Ld Ls PARAMETER Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance CONDITIONS VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. TYP. 4500 1500 960 35 130 155 150 2.5 7.5 MAX. 6000 1800 1300 55 200 230 220 UNIT pF pF pF ns ns ns ns nH nH VDD = 30 V; Rload =1.2Ω; VGS = 10 V; RG = 10 Ω Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V IF = 75 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V TYP. 0.85 1.1 400 1.0 MAX. 75 240 1.2 UNIT A A V V ns µC AVALANCHE LIMITING VALUE SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 75 A; VDD ≤ 25 V; VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C MIN. TYP. MAX. 500 UNIT mJ August 1999 2 Rev 1.100 Philips Semiconductors Product specification TrenchMOS™ transistor Standard level FET BUK7605-30A 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 1 D= 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0 Zth / (K/W) P D tp D= tp T t T 0 20 40 60 80 100 Tmb / C 120 140 160 180 0.001 0.00001 0.001 t/S 0.1 10 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 400 20.0 ID/A 14.0 12.0 300 8.0 7.5 200 7.0 6.5 100 6.0 5.5 5.0 4.5 0 2 4 VDS/V 6 8 10 120 110 100 90 80 70 60 50 40 30 20 10 0 ID% Normalised Current Derating 10.0 9.5 9.0 VGS/V = 8.5 0 20 40 60 80 100 Tmb / C 120 140 160 180 0 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS RDS(ON)/mOhm VGS/V = 1000 ID/A RDS(ON) = VDS/ID 100 tp = 100uS 11 10 9 8 1mS 10mS 10 DC 100mS 7 6 5 4 5.5 6.0 6.5 7.0 8.0 10.0 1 3 1 10 VDS/V 100 0 20 40 ID/A 60 80 100 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS August 1999 3 Rev 1.100 Philips Semiconductors Product specification TrenchMOS™ transistor Standard level FET BUK7605-30A 7.5 7 6.5 6 5.5 RDS(ON)/mOhm a 2 30V TrenchMOS 1.5 1 5 4.5 0.5 4 3.5 3 5 10 VGS/V 15 20 0 -100 -50 0 50 Tj / C 100 150 200 Fig.7. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(VGS); conditions ID = 25 A; 100 ID/A Fig.10. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V VGS(TO) / V max. BUK759-60 5 80 4 typ. 60 3 min. 40 Tj/C = 20 175 25 2 1 0 0 1 2 3 VGS/V 4 5 6 7 0 -100 -50 0 50 Tj / C 100 150 200 Fig.8. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj 90 gfs/S 80 70 60 50 40 30 20 10 0 0 20 40 ID/A 60 80 100 Fig.11. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Sub-Threshold Conduction 1E-01 1E-02 2% typ 98% 1E-03 1E-04 1E-05 1E-06 0 1 2 3 4 5 Fig.9. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V Fig.12. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS August 1999 4 Rev 1.100 Philips Semiconductors Product specification TrenchMOS™ transistor Standard level FET BUK7605-30A 10 9 8 7 Thousands pF 6 5 4 3 2 1 0 0.01 0.1 1 VDS/V 10 Coss Crss 100 Ciss 120 110 100 90 80 70 60 50 40 30 20 10 0 WDSS% 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.13. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 12 VGS/V 10 Fig.16. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A + L VDS VDS = 14V 24V VDD 8 6 VGS 0 RGS 0 20 40 60 QG/nC 80 100 120 140 -ID/100 T.U.T. R 01 shunt 4 2 0 Fig.14. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 50 A; parameter VDS 100 ID/A 80 Fig.17. Avalanche energy test circuit. 2 WDSS = 0.5 ⋅ LID ⋅ BVDSS /(BVDSS − VDD ) + RD VDS Tj/C = 175 25 VDD 60 VGS 0 RG T.U.T. - 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VSDS/V 0.8 0.9 1 1.1 Fig.15. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj Fig.18. Switching test circuit. August 1999 5 Rev 1.100 Philips Semiconductors Product specification TrenchMOS™ transistor Standard level FET MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) BUK7605-30A SOT404 A E A1 mounting base D1 D HD 2 Lp 1 3 b c Q e e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.40 14.80 Q 2.60 2.20 OUTLINE VERSION SOT404 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 Fig.19. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". August 1999 6 Rev 1.100 Philips Semiconductors Product specification TrenchMOS™ transistor Standard level FET MOUNTING INSTRUCTIONS Dimensions in mm 11.5 BUK7605-30A 9.0 17.5 2.0 3.8 5.08 Fig.20. SOT404 : soldering pattern for surface mounting. DEFINITIONS Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. © Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1999 7 Rev 1.100