BUK9MGP-55PTS

BUK9MGP-55PTS Dual TrenchPLUS logic level FET Rev. 01 — 14 May 2009 Product data sheet 1. Product profile 1.1 General description Dual N-channel enhancement mode field-effect power transistor in SO20. Device is manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring very low on-state resistance, integrated current sensing transistors and over temperature protection diodes. 1.2 Features and benefits Integrated current sensors Integrated temperature sensors 1.3 Applications Lamp switching Motor drive systems Power distribution Solenoid drivers 1.4 Quick reference data Table 1. Quick reference Conditions VGS = 5 V; ID = 10 A; Tj = 25 °C; see Figure 23; see Figure 25 Tj = 25 °C; VGS = 5 V; see Figure 27 VGS = 0 V; ID = 250 µA; Tj = 25 °C VGS = 5 V; ID = 5 A; Tj = 25 °C; see Figure 24; see Figure 26 Tj = 25 °C; VGS = 5 V; see Figure 28 VGS = 0 V; ID = 250 µA; Tj = 25 °C Min Typ 8.6 Max 10 Unit mΩ Symbol Parameter Static characteristics, FET1 RDSon drain-source on-state resistance ratio of drain current to sense current ID/Isense 8100 55 9000 - 9900 - A/A V V(BR)DSS drain-source breakdown voltage Static characteristics, FET2 RDSon drain-source on-state resistance ratio of drain current to sense current - 21.3 25 mΩ ID/Isense 5910 55 6570 - 7227 - A/A V V(BR)DSS drain-source breakdown voltage NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 2. Pinning information Table 2. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pinning information Symbol G1 IS1 D1 A1 C1 G2 IS2 D2 A2 C2 D2 KS2 S2 S2 D2 D1 KS1 S1 S1 D1 Description gate 1 current sense 1 drain 1 anode 1 cathode 1 gate 2 current sense 2 drain 2 anode 2 cathode 2 drain 2 Kelvin source 2 source 2 source 2 drain 2 drain 1 Kelvin source 1 source 1 source 1 drain 1 1 10 20 11 D1 A1 D2 A2 Simplified outline Graphic symbol FET1 FET2 SOT163-1 (SO20) G1 IS1 S1 KS1 C1 G2 IS2 S2 KS2 C2 003aaa745 3. Ordering information Table 3. Ordering information Package Name BUK9MGP-55PTS SO20 Description plastic small outline package; 20 leads; body width 7.5 mm Version SOT163-1 Type number BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 2 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 4. Limiting values Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature Tsp = 25 °C; VGS = 5 V; see Figure 3; see Figure 7; [1][2] Tsp = 100 °C; VGS = 5 V; see Figure 3; Tsp = 25 °C; tp ≤ 10 µs; pulsed; see Figure 7 Tsp = 25 °C; see Figure 1 [1][2] Conditions 25 °C < Tj < 150 °C RGS = 20 kΩ; 25 °C < Tj < 150 °C Min -15 -55 -55 Max 55 55 15 16.9 10.7 349 5.2 150 150 100 Unit V V V A A A W °C °C V In accordance with the Absolute Maximum Rating System (IEC 60134). Limiting values, FET1 Visol(FET-TSD) FET to temperature sense diode isolation voltage Limiting values, FET2 VDS VDGR VGS ID IDM Ptot Tstg Tj drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature Tsp = 25 °C; VGS = 5 V; see Figure 4; see Figure 8; [1][2] Tsp = 100 °C; VGS = 5 V; see Figure 4; Tsp = 25 °C; tp ≤ 10 µs; pulsed; see Figure 8 Tsp = 25 °C; see Figure 2 [1][2] 25 °C < Tj < 150 °C RGS = 20 kΩ; 25 °C < Tj < 150 °C -15 -55 -55 - 55 55 15 9.16 5.8 148 3.9 150 150 100 V V V A A A W °C °C V Visol(FET-TSD) FET to temperature sense diode isolation voltage Source-drain diode, FET1 IS ISM IS ISM EDS(AL)S source current peak source current source current peak source current Tsp = 25 °C; tp ≤ 10 µs; pulsed; Tsp = 25 °C Tsp = 25 °C; tp ≤ 10 µs; pulsed; Tsp = 25 °C [3][4] [5] [1][2] [1][2] - 7.3 349 5.5 148 929 A A A A mJ Source-drain diode, FET2 Avalanche ruggedness, FET1 non-repetitive ID = 16.9 A; Vsup ≤ 55 V; VGS = 5 V; Tj(init) = 25 °C; drain-source avalanche unclamped; see Figure 5; energy non-repetitive ID = 9.16 A; Vsup ≤ 55 V; VGS = 5 V; Tj(init) = 25 °C; drain-source avalanche unclamped; see Figure 6; energy Avalanche ruggedness, FET2 EDS(AL)S [3][4] [5] 360 mJ BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 3 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET Table 4. Symbol VESD Limiting values …continued Parameter electrostatic discharge voltage Conditions HBM; C = 100 pF; R = 1.5 kΩ; pins 3, 16 and 20 to pins 1, 2, 17, 18 and 19 shorted HBM; C = 100 pF; R = 1.5 kΩ; all pins Min Max 4 0.15 4 0.15 Unit kV kV kV kV In accordance with the Absolute Maximum Rating System (IEC 60134). Electrostatic discharge, FET1 Electrostatic discharge, FET2 VESD electrostatic discharge voltage HBM; C = 100 pF; R = 1.5 kΩ; pins 8, 11 and 15 to pins 6, 7, 12, 13 and 14 shorted HBM; C = 100 pF; R = 1.5 kΩ; all pins [1] [2] [3] [4] [5] Single device conducting. Current is limited by chip power dissipation rating. Single-pulse avalanche rating limited by maximum junction temperature of 150 °C. Repetitive rating defined in avalanche rating figure. Refer to application note AN10273 for further information. 120 Pder (%) 80 003aab388 120 Pder (%) 80 003aab388 40 40 0 0 50 100 150 200 Tsp (°C) 0 0 50 100 150 200 Tsp (°C) Fig 1. Normalized total power dissipation as a function of solder point temperature, FET1 Fig 2. Normalized total power dissipation as a function of solder point temperature, FET2 BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 4 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 20 ID (A) 16 003aac532 12 ID (A) 003aac533 8 12 8 4 4 0 0 50 100 150 Tsp (°C) 200 0 0 50 100 150 Tsp (°C) 200 Fig 3. Continuous drain current as a function of solder point temperature, FET1. 003aac527 Fig 4. Continuous drain current as a function of solder point temperature, FET2. 003aac528 102 IAL (A) 102 IAL (A) 10 (1) 10 (1) (2) (2) 1 1 (3) (3) 10-1 10-3 10-2 10-1 1 tAL (ms) 10 10-1 10-3 10-2 10-1 1 tAL (ms) 10 Fig 5. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 Fig 6. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET2 BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 5 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 103 ID (A) 2 10 003aac362 Limit R DS on = VDS / ID tp = 1 0 ms 100 ms 10 1 ms 10 ms 1 100 ms DC 10-1 10-2 10-1 1 10 VDS (V) 102 Fig 7. 103 ID (A) 2 10 Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1. 003aac375 Limit R DS on = VDS / ID tp = 1 0 ms 100 ms 1 ms 10 1 DC 10-1 10 ms 100 ms 10-2 10-1 1 10 VDS (V) 102 Fig 8. Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET2 BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 6 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 5. Thermal characteristics Table 5. Symbol Rth(j-sp) Rth(j-a) Thermal characteristics Parameter Conditions Min Typ 73 Max 24 32 Unit K/W K/W K/W thermal resistance from FET1 junction to solder point FET2 thermal resistance from mounted on printed-circuit board; Both junction to ambient channel conducting; zero heat sink area; see Figure 9; see Figure 10 mounted on printed-circuit board; Both channel conducting; 200 mm2 copper heat sink area; see Figure 9; see Figure 11 mounted on printed-circuit board; Both channel conducting; 400 mm2 copper heat sink area; see Figure 9; see Figure 12 mounted on printed-circuit board; One channel conducting; zero heat sink area; see Figure 9; see Figure 10 mounted on printed-circuit board; One channel conducting; 200 mm2 copper heat sink area; see Figure 9; see Figure 11 mounted on printed-circuit board; One channel conducting; 400 mm2 copper heat sink area; see Figure 9; see Figure 12 - 60 - K/W - 51 - K/W - 105 - K/W - 90 - K/W - 78 - K/W 120 Rth(j-a) (K/W) (1) 80 (2) 003aac472 40 001aae478 Fig 10. PCB used for thermal tests; zero heat sink area 0 0 100 200 300 A (mm2) 400 Fig 9. Thermal resistance from junction to ambient as a function of printed-circuit board (PCB) heat sink area BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 7 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 001aae479 001aae480 Fig 11. PCB used for thermal tests; heat sink area 200 mm2 102 Zth(j-mb) (K/W) 10 δ = 0.5 0.2 0.1 0.05 Fig 12. PCB used for thermal tests; heat sink area 400 mm2 003aad208 1 0.02 10-1 P δ= tp T 10-2 single shot tp T t 10-3 10-6 10-5 10-4 10-3 10-2 10-1 1 10 102 103 4 tp (s) 10 Fig 13. Transient thermal impedance from junction to ambient as a function of pulse duration, FET1 (PCB used for thermal tests; heat sink area 400mm2) 102 Zth(j-mb) (K/W) 10 003aad209 δ = 0.5 0.2 0.1 0.05 0.02 1 P δ= tp T 10-1 tp single shot t T 10-2 10-6 10-5 10-4 10-3 10-2 10-1 1 10 102 103 4 tp (s) 10 Fig 14. Transient thermal impedance from junction to ambient as a function of pulse duration, FET2 (PCB used for thermal tests; heat sink area 400mm2) BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 8 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 6. Characteristics Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 250 µA; VGS = 0 V; Tj = 25 °C ID = 250 µA; VGS = 0 V; Tj = -55 °C ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 21; see Figure 22 ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 21; see Figure 22 ID = 1 mA; VDS = VGS; Tj = 150 °C; see Figure 21; see Figure 22 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 40 V; VGS = 0 V; Tj = 25 °C VDS = 40 V; VGS = 0 V; Tj = 150 °C VDS = 0 V; VGS = 15 V; Tj = 25 °C VGS = 5 V; ID = 10 A; Tj = 25 °C; see Figure 23; see Figure 25 VGS = 5 V; ID = 10 A; Tj = 150 °C; see Figure 25; see Figure 23 VGS = 4.5 V; ID = 10 A; Tj = 25 °C; see Figure 23; see Figure 25 VGS = 10 V; ID = 10 A; Tj = 25 °C; see Figure 23; see Figure 25 ID/Isense SF(TSD) ratio of drain current to sense current temperature sense diode temperature coefficient temperature sense diode forward voltage drain-source breakdown voltage gate-source threshold voltage Tj = 25 °C; VGS = 5 V; see Figure 27 IF = 250 µA; 25 °C < Tj < 150 °C; see Figure 29 IF = 250 µA; Tj = 25 °C; see Figure 29 Min 55 50 1 0.5 8100 -5.4 Typ 1.5 0.02 2 8.6 9.4 8.1 9000 -5.7 Max 2 2.3 3 125 300 10 18 11.1 9 9900 -6 Unit V V V V V µA µA nA mΩ mΩ mΩ mΩ A/A mV/K Static characteristics, FET1 VF(TSD) 2.855 2.9 2.945 V Static characteristics, FET2 V(BR)DSS VGS(th) ID = 250 µA; VGS = 0 V; Tj = 25 °C ID = 250 µA; VGS = 0 V; Tj = -55 °C ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 21; see Figure 22 ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 21; see Figure 22 ID = 1 mA; VDS = VGS; Tj = 150 °C; see Figure 21; see Figure 22 IDSS IGSS drain leakage current gate leakage current VDS = 40 V; VGS = 0 V; Tj = 25 °C VDS = 40 V; VGS = 0 V; Tj = 150 °C VDS = 0 V; VGS = 15 V; Tj = 25 °C 55 50 1 0.5 1.5 0.02 2 2 2.3 3 125 300 V V V V V µA µA nA BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 9 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET Table 6. Symbol RDSon Characteristics …continued Parameter drain-source on-state resistance Conditions VGS = 5 V; ID = 5 A; Tj = 25 °C; see Figure 24; see Figure 26 VGS = 5 V; ID = 5 A; Tj = 150 °C; see Figure 24; see Figure 26 VGS = 4.5 V; ID = 5 A; Tj = 25 °C; see Figure 24; see Figure 26 VGS = 10 V; ID = 5 A; Tj = 25 °C; see Figure 24; see Figure 26 Min 5910 -5.4 Typ 21.3 23.7 20.3 6570 -5.7 Max 25 46.8 27.9 22.6 7227 -6 Unit mΩ mΩ mΩ mΩ A/A mV/K ID/Isense SF(TSD) ratio of drain current to sense current temperature sense diode temperature coefficient temperature sense diode forward voltage total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time internal drain inductance internal source inductance total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time Tj = 25 °C; VGS = 5 V; see Figure 28 IF = 250 µA; 25 °C < Tj < 150 °C; see Figure 29 IF = 250 µA; Tj = 25 °C; see Figure 29 VF(TSD) 2.855 2.9 2.945 V Dynamic characteristics, FET1 QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf LD LS ID = 10 A; VDS = 44 V; VGS = 5 V; see Figure 30 VGS = 0 V; VDS = 25 V; f = 1 MHz; Tj = 25 °C; see Figure 32 VDS = 30 V; RL = 3 Ω; VGS = 5 V; RG(ext) = 10 Ω From pin to centre of die From source lead to source bonding pad 54 9.4 21.5 3884 540 247 41 94 184 98 0.85 1.9 5178 648 338 nC nC nC pF pF pF ns ns ns ns nH nH Dynamic characteristics, FET2 QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf ID = 5 A; VDS = 44 V; VGS = 0 V; see Figure 31 VGS = 0 V; VDS = 25 V; f = 1 MHz; Tj = 25 °C; see Figure 33 VDS = 30 V; RL = 6 Ω; VGS = 5 V; RG(ext) = 10 Ω 23 3.4 9 1736 244 119 29 44 91 46 2315 293 163 nC nC nC pF pF pF ns ns ns ns BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 10 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET Table 6. Symbol LD LS Characteristics …continued Parameter internal drain inductance internal source inductance source-drain voltage reverse recovery time recovered charge source-drain voltage reverse recovery time recovered charge Conditions From pin to centre of die From source lead to source bonding pad Min Typ 0.85 2 Max Unit nH nH Source-drain diode, FET1 VSD trr Qr VSD trr Qr [1] xsa IS = 10 A; VGS = 0 V; Tj = 25 °C; see Figure 34 IS = 5 A; dIS/dt = -100 A/µs; VGS = -10 V; VDS = 30 V; [1] - 0.85 66.4 126 0.85 44 69 1.2 1.2 - V ns nC V ns nC Source-drain diode, FET2 IS = 5 A; VGS = 0 V; Tj = 25 °C; see Figure 35 IS = 5 A; dIS/dt = -100 A/µs; VGS = -10 V; VDS = 30 V 200 ID (A) 10 150 003aac358 100 ID (A) 5 4.5 4 003aac369 5 4.5 4 80 10 60 3.5 100 40 3 50 VGS (V) =2.5 V 20 3.5 3 VGS (V) =2.5 V 0 0 2 4 6 8 VDS (V) 10 0 0 2 4 6 8 VDS (V) 10 Fig 15. Output characteristics: drain current as a function of drain-source voltage; typical values, FET1 Fig 16. Output characteristics: drain current as a function of drain-source voltage; typical values, FET2 BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 11 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 30 RDS on (mΩ) 25 003aac361 003aac372 40 RDS on (mΩ) 20 30 15 10 20 5 0 2 4 6 8 VGS (V) 10 10 2 4 6 8 VGS (V) 10 Fig 17. Drain-source on-state resistance as a function of gate-source voltage; typical values, FET1 003aac357 Fig 18. Drain-source on-state resistance as a function of gate-source voltage; typical values, FET2 40 gfs (S ) 30 003aac368 80 gfs (S ) 60 40 20 20 10 0 0 6 12 18 24 I D (A) 30 0 0 5 10 15 20 25 30 I D (A) Fig 19. Forward transconductance as a function of drain current; typical values, FET1 Fig 20. Forward transconductance as a function of drain current; typical values, FET2 BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 12 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 10−1 ID (A) 10−2 min 10−3 typ max 003aac894 2.5 VGS(th) (V) 2.0 max 003aac895 1.5 typ 10−4 1.0 min 10−5 0.5 10−6 0 1 2 VGS (V) 3 0 −60 0 60 120 Tj (°C) 180 Fig 21. Sub-threshold drain current as a function of gate-source voltage, FET1 and FET2 50 RDS on (mΩ) 40 4 4.5 5 3.5 30 2.5 3 003aac360 Fig 22. Gate-source threshold voltage as a function of junction temperature, FET1 and FET2 003aac371 50 RDS on (mΩ) 40 2.5 3 3.5 4 30 4.5 20 5 20 10 VGS (V) = 10 0 0 40 80 120 160 I D (A) 200 10 0 20 40 60 80 I D (A) 100 VGS (V) = 10 Fig 23. Drain-source on-state resistance as a function of drain current; typical values, FET1 Fig 24. Drain-source on-state resistance as a function of drain current; typical values, FET2 BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 13 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 2.0 a 001aae823 2.0 a 001aae823 1.5 1.5 1.0 1.0 0.5 0.5 0 −60 0 60 120 Tj (°C) 180 0 −60 0 60 120 Tj (°C) 180 Fig 25. Normalized drain-source on-state resistance factor as a function of junction temperature, FET1 12000 I D/I sense 11000 003aac355 Fig 26. Normalized drain-source on-state resistance factor as a function of junction temperature, FET2 14000 I D/I sense 12000 003aac367 10000 10000 8000 9000 6000 8000 2 4 6 8 VGS (V) 10 4000 2 4 6 8 VGS (V) 10 Fig 27. Ratio of drain current to sense current as a function of gate-source voltage; typical values, FET1 Fig 28. Ratio of drain current to sense current as a function of gate-source voltage; typical values, FET2 BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 14 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 3.0 VF(TSD) (V) 2.5 001aae485 2.0 1.5 0 40 80 120 Tj (°C) 160 Fig 29. Temperature sense diode forward voltage as a function of junction temperature; typical values, FET1 and FET2 5 VGS (V) 4 003aac359 5 VGS (V) 003a ac370 VDS = 1 4 V 4 VDS = 1 4 V 3 VDS = 4 4 V 3 VDS = 4 4 V 2 2 1 1 0 0 20 40 60 QG (nC) 80 0 0 10 20 QG (nC) 30 Fig 30. Gate-source voltage as a function of turn-on gate charge; typical values, FET1 Fig 31. Gate-source voltage as a function of turn-on gate charge; typical values, FET2 BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 15 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 104 C (pF) 103 003a ac356 104 C (pF) 003a ac366 Cis s Cis s 103 Cos s Crs s 102 102 Cos s Crs s 10 10-1 1 10 VDS (V) 102 10 10-1 1 10 VDS (V) 102 Fig 32. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values, FET1 60 IS (A) 40 003aac364 Fig 33. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values, FET2 50 IS (A) 40 003aac374 30 150 °C 20 Tj = 2 5 °C 20 Tj = 2 5 °C 10 150 °C 0 0.2 0 0.4 0.6 0.8 1 1.2 VS D (V) 0 0.5 1 1.5 VS D (V) 2 Fig 34. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values, FET1 Fig 35. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values, FET2 BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 16 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 7. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 8o o 0 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 36. Package outline SOT163-1 BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 17 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 8. Revision history Table 7. Revision history Release date 20090514 Data sheet status Product data sheet Change notice Supersedes Document ID BUK9MGP-55PTS_1 BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 18 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 9. Legal information 9.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com BUK9MGP-55PTS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 19 of 20 NXP Semiconductors BUK9MGP-55PTS Dual TrenchPLUS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .18 Legal information. . . . . . . . . . . . . . . . . . . . . . . .19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Contact information. . . . . . . . . . . . . . . . . . . . . .19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 May 2009 Document identifier: BUK9MGP-55PTS_1