1N6374G

1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45) 1500 Watt Peak Power Mosorbt Zener Transient Voltage Suppressors Unidirectional* Mosorb devices are designed to protect voltage sensitive components from high voltage, high−energy transients. They have excellent clamping capability, high surge capability, low zener impedance and fast response time. These devices are ON Semiconductor’s exclusive, cost-effective, highly reliable Surmetict axial leaded package and are ideally-suited for use in communication systems, numerical controls, process controls, medical equipment, business machines, power supplies and many other industrial/consumer applications, to protect CMOS, MOS and Bipolar integrated circuits. Specification Features http://onsemi.com Cathode Anode AXIAL LEAD CASE 41A PLASTIC MARKING DIAGRAMS A MPTE −xx 1N 63xx YYWWG G A ICTE −xx YYWWG G A = Assembly Location MPTE−xx = ON Device Code 1N63xx = JEDEC Device Code ICTE−xx = ON Device Code YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) • • • • • • • Working Peak Reverse Voltage Range − 5.0 V to 45 V Peak Power − 1500 Watts @ 1 ms ESD Rating of Class 3 (>16 KV) per Human Body Model Maximum Clamp Voltage @ Peak Pulse Current Low Leakage < 5 mA Above 10 V Response Time is Typically < 1 ns Pb−Free Packages are Available* Mechanical Characteristics CASE: Void-free, transfer-molded, thermosetting plastic FINISH: All external surfaces are corrosion resistant and leads are readily solderable MAXIMUM LEAD TEMPERATURE FOR SOLDERING PURPOSES: 230°C, 1/16″ from the case for 10 seconds POLARITY: Cathode indicated by polarity band MOUNTING POSITION: Any ORDERING INFORMATION Device MPTE−xx, G MPTE−xxRL4, G ICTE−xx, G ICTE−xxRL4, G 1N63xx, G Package Axial Lead (Pb−Free) Axial Lead (Pb−Free) Axial Lead (Pb−Free) Axial Lead (Pb−Free) Axial Lead (Pb−Free) Axial Lead (Pb−Free) Shipping† 500 Units/Box 1500/Tape & Reel 500 Units/Box 1500/Tape & Reel 500 Units/Box 1500/Tape & Reel *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 1N63xxRL4, G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2005 1 December, 2005 − Rev. 4 Publication Order Number: 1N6373/D 1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45) MAXIMUM RATINGS Rating Peak Power Dissipation (Note 1) @ TL ≤ 25°C Steady State Power Dissipation @ TL ≤ 75°C, Lead Length = 3/8″ Derated above TL = 75°C Thermal Resistance, Junction−to−Lead Forward Surge Current (Note 2) @ TA = 25°C Operating and Storage Temperature Range Symbol PPK PD RqJL IFSM TJ, Tstg Value 1500 5.0 20 20 200 − 65 to +175 Unit W W mW/°C °C/W A °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Nonrepetitive current pulse per Figure 5 and derated above TA = 25°C per Figure 2. 2. 1/2 sine wave (or equivalent square wave), PW = 8.3 ms, duty cycle = 4 pulses per minute maximum. *Please see 1N6382 – 1N6389 (ICTE−10C − ICTE−36C, MPTE−8C − MPTE−45C) for Bidirectional Devices. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 3.5 V Max. @ IF (Note 3) = 100 A) Symbol IPP VC VRWM IR VBR IT QVBR IF VF Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current Maximum Temperature Variation of VBR Forward Current Forward Voltage @ IF VC VBR VRWM IF I IR VF IT V IPP Uni−Directional TVS http://onsemi.com 2 1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45) ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 3.5 V Max. @ IF (Note 3) = 100 A) JEDEC Device† (ON Device) 1N6373, G (MPTE−5, G) 1N6374, G (MPTE−8, G) 1N6375, G (MPTE−10,G) 1N6376, G (MPTE−12, G) 1N6377, G (MPTE−15, G) 1N6379, G (MPTE−22, G) 1N6380, G (MPTE−36, G) 1N6381, G (MPTE−45, G) ICTE−5, G ICTE−10, G ICTE−12, G VRWM (Note 4) (Volts) 5.0 8.0 10 12 15 22 36 45 5.0 10 12 IR @ VRWM (mA) 300 25 2.0 2.0 2.0 2.0 2.0 2.0 300 2.0 2.0 Breakdown Voltage VBR (Note Min 6.0 9.4 11.7 14.1 17.6 25.9 42.4 52.9 6.0 11.7 14.1 5) (Volts) Max − − − − − − − − − − − @ IT (mA) 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 VC @ IPP (Note 6) VC (Volts) 9.4 15 16.7 21.2 25 37.5 65.2 78.9 9.4 16.7 21.2 IPP (A) 160 100 90 70 60 40 23 19 160 90 70 VC (Volts) (Note 6) @ IPP = 1A 7.1 11.3 13.7 16.1 20.1 29.8 50.6 63.3 7.1 13.7 16.1 @ IPP = 10 A 7.5 11.5 14.1 16.5 20.6 32 54.3 70 7.5 14.1 16.5 QVBR (mV/°C) 4.0 8.0 12 14 18 26 50 60 4.0 8.0 12 Device Marking 1N6373 MPTE−5 1N6374 MPTE−8 1N6375 MPTE−10 1N6376 MPTE−12 1N6377 MPTE−15 1N6379 MPTE−22 1N6380 MPTE−36 1N6381 MPTE−45 ICTE−5 ICTE−10 ICTE−12 Nom − − − − − − − − − − − ICTE−15, G ICTE−15 15 2.0 17.6 − − 1.0 25 60 20.1 20.6 14 ICTE−18, G ICTE−18 18 2.0 21.2 − − 1.0 30 50 24.2 25.2 18 ICTE−22, G ICTE−22 22 2.0 25.9 − − 1.0 37.5 40 29.8 32 21 ICTE−36, G ICTE−36 36 2.0 42.4 − − 1.0 65.2 23 50.6 54.3 26 3. Square waveform, PW = 8.3 ms, non−repetitive duty cycle. 4. A transient suppressor is normally selected according to the maximum working peak reverse voltage (VRWM), which should be equal to or greater than the dc or continuous peak operating voltage level. 5. VBR measured at pulse test current IT at an ambient temperature of 25°C and minimum voltage in VBR is to be controlled. 6. Surge current waveform per Figure 5 and derate per Figures 1 and 2. †The “G’’ suffix indicates Pb−Free package available. http://onsemi.com 3 1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45) PEAK PULSE DERATING IN % OF PEAK POWER OR CURRENT @ TA = 25°C 100 NONREPETITIVE PULSE WAVEFORM SHOWN IN FIGURE 5 PPK , PEAK POWER (kW) 100 80 60 40 20 0 0 25 50 75 100 125 150 175 200 TA, AMBIENT TEMPERATURE (°C) 10 1 0.1 ms 1 ms 10 ms 100 ms 1 ms 10 ms tP, PULSE WIDTH Figure 1. Pulse Rating Curve Figure 2. Pulse Derating Curve 1N6373, ICTE-5, MPTE-5, through 1N6389, ICTE-45, C, MPTE-45, C 10,000 MEASURED @ ZERO BIAS C, CAPACITANCE (pF) 1000 MEASURED @ VRWM 100 10 1 10 100 1000 VBR, BREAKDOWN VOLTAGE (VOLTS) Figure 3. Capacitance versus Breakdown Voltage PD , STEADY STATE POWER DISSIPATION (WATTS) 3/8″ 5 4 3 2 1 0 0 25 50 75 100 125 150 175 TL, LEAD TEMPERATURE (°C) 200 0 0 IPP, VALUE (%) 3/8″ 100 tr ≤ 10 ms PEAK VALUE − IPP PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAYS TO 50% OF IPP. HALF VALUE − 50 tP IPP 2 1 2 t, TIME (ms) 3 4 Figure 4. Steady State Power Derating Figure 5. Pulse Waveform http://onsemi.com 4 1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45) 1N6373, ICTE-5, MPTE-5, through 1N6389, ICTE-45, C, MPTE-45, C 1000 500 IT , TEST CURRENT (AMPS) 200 100 50 20 10 5 2 1 0.3 0.5 0.7 1 2 3 5 7 10 20 30 DVBR, INSTANTANEOUS INCREASE IN VBR ABOVE VBR(NOM) (VOLTS) TL = 25°C tP = 10 ms VBR(MIN) = 6.0 to 11.7 V 19 V 42.4 V 21.2 V 1000 500 IT , TEST CURRENT (AMPS) 200 100 50 20 10 5 2 1 0.3 0.5 0.7 1 2 3 5 7 10 20 30 DVBR, INSTANTANEOUS INCREASE IN VBR ABOVE VBR(NOM) (VOLTS) 180 V 120 V TL = 25°C tP = 10 ms 1.5KE6.8CA through 1.5KE200CA VBR(NOM) = 6.8 to 13 V 20 V 24 V 43 V 75 V Figure 6. Dynamic Impedance 1 0.7 0.5 0.3 DERATING FACTOR 0.2 0.1 0.07 0.05 0.03 0.02 10 ms 0.01 0.1 0.2 0.5 1 2 5 10 D, DUTY CYCLE (%) 20 50 100 PULSE WIDTH 10 ms 1 ms 100 ms Figure 7. Typical Derating Factor for Duty Cycle http://onsemi.com 5 1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45) APPLICATION NOTES RESPONSE TIME In most applications, the transient suppressor device is placed in parallel with the equipment or component to be protected. In this situation, there is a time delay associated with the capacitance of the device and an overshoot condition associated with the inductance of the device and the inductance of the connection method. The capacitance effect is of minor importance in the parallel protection scheme because it only produces a time delay in the transition from the operating voltage to the clamp voltage as shown in Figure 8. The inductive effects in the device are due to actual turn-on time (time required for the device to go from zero current to full current) and lead inductance. This inductive effect produces an overshoot in the voltage across the equipment or component being protected as shown in Figure 9. Minimizing this overshoot is very important in the application, since the main purpose for adding a transient suppressor is to clamp voltage spikes. These devices have excellent response time, typically in the picosecond range and negligible inductance. However, external inductive effects could produce unacceptable overshoot. Proper circuit layout, minimum lead lengths and placing the suppressor device as close as possible to the equipment or components to be protected will minimize this overshoot. Some input impedance represented by Zin is essential to prevent overstress of the protection device. This impedance should be as high as possible, without restricting the circuit operation. DUTY CYCLE DERATING The data of Figure 1 applies for non-repetitive conditions and at a lead temperature of 25°C. If the duty cycle increases, the peak power must be reduced as indicated by the curves of Figure 7. Average power must be derated as the lead or ambient temperature rises above 25°C. The average power derating curve normally given on data sheets may be normalized and used for this purpose. At first glance the derating curves of Figure 7 appear to be in error as the 10 ms pulse has a higher derating factor than the 10 ms pulse. However, when the derating factor for a given pulse of Figure 7 is multiplied by the peak power value of Figure 1 for the same pulse, the results follow the expected trend. TYPICAL PROTECTION CIRCUIT Zin Vin LOAD VL V Vin (TRANSIENT) VL V OVERSHOOT DUE TO INDUCTIVE EFFECTS Vin (TRANSIENT) VL Vin td tD = TIME DELAY DUE TO CAPACITIVE EFFECT t t Figure 8. Figure 9. http://onsemi.com 6 1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45) MOSORB CASE 41A−04 ISSUE D B D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. LEAD FINISH AND DIAMETER UNCONTROLLED IN DIMENSION P. 4. 041A−01 THRU 041A−03 OBSOLETE, NEW STANDARD 041A−04. INCHES MIN MAX 0.335 0.374 0.189 0.209 0.038 0.042 1.000 −−− −−− 0.050 MILLIMETERS MIN MAX 8.50 9.50 4.80 5.30 0.96 1.06 25.40 −−− −−− 1.27 K P P A DIM A B D K P K http://onsemi.com 7 1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45) Mosorb and Surmetic are trademarks of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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