ADP3210MNR2G

ADP3210 7-Bit, Programmable, Multiphase Mobile CPU Synchronous Buck Controller The ADP3210 is a high efficiency, multiphase, synchronous, buck−switching regulator controller optimized for converting notebook battery voltage into the core supply voltage of high performance Intel processors. The part uses an internal 7−bit DAC to read Voltage Identification (VID) code directly from the processor that sets the output voltage. The phase relationship of the output signals can be configured for 1−, 2−, or 3−phase operation, with interleaved switching. The ADP3210 uses a multi−mode architecture to drive the logic−level PWM outputs at a switching frequency selected by the user depending on the output current requirement. The part switches between multiphase and single−phase operation according to a system signal provided by the CPU. Shedding phases as function of the load maximizes power conversion efficiency under different load conditions. In addition, the ADP3210 supports programmable load−line resistance adjustment. As a result, the output voltage is always optimally positioned for a load transient. The chip also provides accurate and reliable short−circuit protection with adjustable current limit threshold and a delayed power−good output that is masked during On−The−Fly (OTF) output voltage changes to eliminate false alarm. The ADP3210 performance is specified over the extended commercial temperature range of −10°C to 100°C. The chip is available in a 40−lead QFN package. http://onsemi.com 1 40 MARKING DIAGRAM 1 ADP3210 AWLYYWWG A WL YY WW G Features • • • • • • • • EN PWRGD IMON CLKEN FBRTN FB COMP NC TRDET DPRSLP 1 40 ADP3210 (top view) TTSN VRTT DCM1 OD PWM1 PWM2 PWM3 SW1 SW2 SW3 ORDERING INFORMATION Applications • Notebook Power Supplies for Next Generation Intel® Processors November, 2011 − Rev. 2 VID0 VID1 VID2 VID3 VID4 VID5 VID6 PSI NC VCC PIN ASSIGNMENT 1−, 2−, or 3−Phase Operation at Up to 1 MHz per Phase Input Voltage Range of 3.3 V to 22 V ±6 mV Worst−Case Differential Sensing Error Overtemperature Interleaved PWM Outputs for Driving External High Power MOSFET Drivers Automatic Power−Saving Modes Maximize Efficiency During Light Load and Deeper Sleep Operation Active Current Balancing Between Output Phases Independent Current Limit and Load Line Setting Inputs for Additional Design Flexibility 7−Bit Digitally Programmable 0 V to 1.5 V Output Overload and Short−Circuit Protection with Latchoff Delay Built−In Clock Enable Output for Delaying CPU Clock Synchronization Until CPU Supply Voltage Stabilizes Output Current Monitor This is a Pb−Free Device © Semiconductor Components Industries, LLC, 2011 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ILIM IREF RPM RT RAMP LLINE CSREF CSSUM CSCOMP GND • • • • QFN40 MN SUFFIX CASE 488AR 1 See detailed ordering and shipping information in the package dimensions section on page 31 of this data sheet. Publication Order Number: ADP3210/D ADP3210 GND RPM COMP Oscillator VEA FB Current Balancing Circuit - ΣΣ + OVP - PSI PWM3 DCM1 OD SW1 1.55 V DPRSLP SW2 PSI and DPRSLP Logic DAC + 200 mV SW3 OCP Shutdown Delay + Current Monitor DAC - 300 mV PWRGD Startup Delay PWRGD Open Drain Delay Disable CLKEN Startup Delay Precision Reference FBRTN CSCOMP ILIM Thermal Throttle Control TTSENSE VRTT REF IREF VID0 VID1 VID2 VID3 VID4 DAC VID5 CSSUM Soft-Start and Soft Transient Control VID DAC VID6 CSREF Soft Transient Delay CLKEN Open Drain CLKEN IMON Current Limit Circuit + - CSREF PWRGD PWM2 Driver Logic - LLINE + + CSREF + Σ Σ + REF RAMP PWM1 UVLO Shutdown and Bias TRDET Generator RT + TRDET VCC EN Figure 1. Functional Block Diagram ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit VCC −0.3 to +6.0 V FBRTN −0.3 to +0.3 V SW1 to SW3 DC t < 200 ns −1.0 to +22 −6.0 to +28 RAMPADJ (in Shutdown) V −0.3 to +22 V All Other Inputs and Outputs −0.3 to VCC to +22 V Storage Temperature Range −65 to +150 °C Operating Ambient Temperature Range −10 to 100 °C Operating Junction Temperature 125 °C Thermal Impedance (qJA) 98 °C/W Lead Temperature Soldering (10 sec) Infrared (15 sec) 300 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. http://onsemi.com 2 ADP3210 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. 2 PWRGD Power−Good Output. Open drain output that signals when the output voltage is outside of the proper operating range. The pull−high voltage on this pin cannot be higher than VCC. 3 IMON 4 CLKEN Clock Enable Output. The pull−high voltage on this pin cannot be higher than VCC. 5 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. 6 FB 7 COMP 8 NC 9 TRDET 10 DPRSLP 11 ILIM Current Limit Set−point. An external resistor from this pin to CSCOMP sets the current limit threshold of the converter. 12 IREF This pin sets the internal bias currents. A 80kW resistor is connected from this pin to ground. 13 RPM RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn−on threshold voltage. 14 RT 15 RAMP PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. 16 LLINE Output Load Line Programming Input. The center point of a resistor divider between CSREF and CSCOMP is connected to this pin to set the load line slope. 17 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power−good and crowbar functions. This pin should be connected to the common point of the output inductors. 18 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the inductor currents together to measure the total output current. 19 CSCOMP Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to FBRTN sets the current monitor gain. Feedback Input. Error amplifier input for remote sensing of the output voltage. Error Amplifier Output and Compensation Point. Not Connected. Transient Detect Output. This pin is pulled low when a load release transient is detected. A capacitor to ground is connected to TRDET pin and a resistor from FB pin to TRDET is connected. During repetitive load transients at high frequencies, this circuit optimally positions the maximum and minimum output voltage into a specified load−line window. Deeper Sleep Control Input. Multiphase Frequency Setting Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device when operating in multiphase PWM mode. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of the current sense amplifier and the positioning loop response time. 20 GND 21 to 23 SW3 to SW1 Ground. All internal biasing and the logic output signals of the device are referenced to this ground. 24 to 26 PWM3 to PWM1 27 OD 28 DCM1 Discontinuous Current Mode Enable Output 1. This pin actively pulled low when the single−phase inductor current crosses zero. 29 VRTT Voltage Regulator Thermal Throttling Logic Output. This pin goes high if the temperature at the monitoring point connected to TTSN exceeds the programmed VRTT temperature threshold. 30 TTSN Thermal Throttling Sense Input. The center point of a resistor divider (where the lower resistor is an NTC thermistor) between VCC and GND is connected to this pin to remotely sense the temperature at the desired thermal monitoring point. Connect TTSN to VCC if this function is not used. 31 VCC Supply Voltage for the Device. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. Logic−Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3419. Connecting the PWM2 and/or PWM3 outputs to VCC causes that phase to turn off, allowing the ADP3210 to operate as a 1−, 2−, or 3−phase controller. Multiphase Output Disable Logic Output. This pin is actively pulled low when the ADP3210 enters single−phase mode or during shutdown. Connect this pin to the SD inputs of the Phase−2 and Phase−3 MOSFET drivers. 32 NC Not Connected. 33 PSI Power State Indicator Input. Pulling this pin to GND forces the ADP3210 to operate in single−phase mode. 34 to 40 VID6 to VID0 Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.3 V to 1.5 V. http://onsemi.com 3 ADP3210 ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 1.20 V to 1.500 V, PSI = 1.1 V, DPRSLP = GND, LLINE = CSREF, Current going into pin is positive. TA = −10°C to 100°C, unless otherwise noted. (Note 1) RREF = 80 kW Parameter Symbol Conditions Min Typ Max Units VOLTAGE CONTROL − Voltage Error Amplifier (VEAMP) FB, LLINE Voltage Range (Note 2) VFB, VLLINE Relative to CSREF = VDAC −200 +200 mV FB, LLINE Offset Voltage (Note 2) VOSVEA Relative to CSREF = VDAC −0.5 +0.5 mV FB Bias Current IFB −1.0 1.0 mA LLINE Bias Current ILL −50 50 nA −78 mV 4.0 V LLINE Positioning Accuracy VFB − VVID Measured on FB relative to VVID, LLINE forced 80 mV below CSREF −82 −80 COMP Voltage Range (Note 2) VCOMP COMP Current (Note 2) ICOMP COMP = 2.0 V, CSREF = VDAC FB forced 80 mV below CSREF FB forced 80 mV above CSREF −0.75 10 SRCOMP CCOMP = 10 pF, CSREF = VDAC FB forced 200 mV below CSREF FB forced 200 mV above CSREF 15 −20 Inverting unit gain configuration, R = 1 kW 20 COMP Slew Rate (Note 2) Gain Bandwidth (Note 2) GBW 0.85 mA V/ms MHz VID DAC VOLTAGE REFERENCE VDAC Voltage Range (Note 2) VDAC Accuracy See VID Code Table VFB − VVID Measured on FB (includes offset), relative to VVID: VVID = 0.3000 V to 1.2000 V VVID = 1.2125 V to 1.5000 V VDAC Differential Non−linearity (Note 2) VDAC Line Regulation (Note 2) VDAC Boot Voltage Soft−Start Delay Boot Delay DVFB VBOOTFB tSS tBOOT VDAC Slew Rate FBRTN Current 0 1.5 −6.0 −7.0 +6.0 +7.0 −1.0 +1.0 VCC = 4.75 V to 5.25 V 0.05 Measured during boot delay period V mV LSB % 1.100 V Measured from EN pos edge to FB settles to VBOOT = 1.1 V within 5% 1.4 ms Measured from FB settling to VBOOT = 1.1 V within 5% to CLKEN neg edge 100 ms 0.0625 1.0 0.4 LSB/ms Soft−Start Non−LSB VID step DVID transition (LSB VID step) IFBRTN −90 200 mA VOLTAGE MONITORING AND PROTECTION − Power Good CSREF Undervoltage Threshold VUVCSREF Relative to nominal DAC Voltage −360 −300 −240 mV CSREF Overvoltage Threshold VOVCSREF Relative to nominal DAC Voltage 135 200 250 mV CSREF Crowbar Voltage Threshold VCBCSREF Relative to FBRTN 1.5 1.55 1.6 V CSREF Reverse Voltage Threshold VRVCSREF Relative to FBRTN CSREF Falling CSREF Rising −350 −300 −75 −10 85 250 PWRGD Low Voltage VPWRGD IPWRGD(SINK) = 4 mA PWRGD Leakage Current IPWRGD VPWRDG = 5.0 V mV 1.0 mV mA PWRGD Startup Delay TSSPWRGD Measured from CLKEN neg edge to PWRGD Pos Edge 8.0 ms PWRGD Propagation Delay (Note 2) TPDPWRGD Measured from Out−off−Good−Window event to PWRGD neg edge 200 ns 1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested. http://onsemi.com 4 ADP3210 ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 1.20 V to 1.500 V, PSI = 1.1 V, DPRSLP = GND, LLINE = CSREF, Current going into pin is positive. TA = −10°C to 100°C, unless otherwise noted. (Note 1) RREF = 80 kW Parameter Symbol Conditions Min Typ Max Units VOLTAGE MONITORING AND PROTECTION − Power Good PWRGD Masking Time Triggered by any VID change or OCP event 100 ms CSREF Soft−Stop Resistance EN = L or Latchoff condition 50 W CURRENT CONTROL − Current Sense Amplifier (CSAMP) CSSUM, CSREF Common−Mode Range (Note 2) CSREF − CSSUM, TA = 25°C TA = −10°C to 85°C 0.05 3.5 V −0.3 −1.2 +0.3 +1.2 mV −50 +50 nA −1.0 +1.0 mA 2.0 V CSSUM, CSREF Offset Voltage VOSCSA CSSUM Bias Current IBCSSUM CSREF Bias Current IBCSREF 0.05 CSCOMP Voltage Range (Note NO TAG) CSCOMP Current ICSCOMPsource ICSCOMPsink CSCOMP Slew Rate (Note 2) Gain Bandwidth (Note 2) GBWCSA CSCOMP = 2.0 V CSSUM forced 200 mV below CSREF CSSUM forced 200 mV above CSREF −660 1.0 CCSCOMP = 10 pF CSSUM forced 200 mV below CSREF CSSUM forced 200 mV above CSREF 10 −10 Inverting unit gain configuration R = 1 kW 20 mA mA V/ms MHz CURRENT MONITORING AND PROTECTION Current Reference IREF Voltage Current Limiter (OCP) Current Limit Threshold VREF VLIMTH RREF = 80 kW to set IREF = 20 mA CSCOMP relative to CSREF, RLIM = 4.5 kW, 3−ph configuration, PSI = H 3−ph configuration, PSI = L 2−ph configuration, PSI = H 2−ph configuration, PSI = L 1−ph configuration 1.55 1.6 1.65 V mV −70 −15 −70 −30 −70 Current Limit Latchoff Delay −90 −30 −90 −45 −90 −110 −50 −110 −65 −110 8.0 ms CURRENT MONITOR Current Gain Accuracy IMON/ILIM Measured from ILIM to IMON ILIM = −20 mA ILIM = −10 mA ILIM = −5 mA (Note 2) 9.4 9.1 8.9 IMON Clamp Voltage VMAXMON Relative to FBRTN, ILIM = −30 mA 1.0 RT = 125 kW, VVID = 1.4000 V See also VRT(VVID) formula 1.08 10 10 10 10.7 11.0 11.4 − 1.15 V 1.32 V 3.0 MHz PULSE WIDTH MODULATOR − Clock Oscillator RT Voltage VRT PWM Clock Frequency Range (Note 2) fCLK PWM Clock Frequency fCLK 1.2 0.3 TA = +25°C, VVID = 1.2000 V RT = 73 kW (Note 2) RT = 125 kW (Note 2) RT = 180 kW kHz 1000 700 500 1300 800 600 1600 900 780 1.0 VIN 1.1 V RAMP GENERATOR RAMP Voltage VRAMP EN = High, IRAMP = 60 mA EN = Low 0.9 RAMP Current Range (Note 2) IRAMP EN = High EN = Low, RAMP = 19 V 1.0 −0.5 100 +0.5 mA VOSRPM = VRAMP − VCOMP −3.0 3.0 mV PWM COMPARATOR PWM Comparator Offset (Note 2) VOSRPM 1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested. http://onsemi.com 5 ADP3210 ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 1.20 V to 1.500 V, PSI = 1.1 V, DPRSLP = GND, LLINE = CSREF, Current going into pin is positive. TA = −10°C to 100°C, unless otherwise noted. (Note 1) RREF = 80 kW Parameter Symbol Conditions Min Typ Max Units RPM COMPARATOR RPM Current RPM Comparator Offset (Note 2) IRPM VOSRPM 6.1 VVID = 1.2 V, RT = 180 kW See also IRPM(RT) formula VOSRPM = VCOMP − (1 +VRPMTH) −3.0 mA 3.0 mV CLOCK SYNC Trigger Threshold (Note 2) Relative to COMP sampled TCLK earlier 3−phase configuration 2−phase configuration 1−phase configuration 350 400 450 Relative to COMP sampled TCLK earlier 3−phase configuration 2−phase configuration 1−phase configuration −450 −500 −600 mV TRDET Trigger Threshold (Note 2) TRDET Low Voltage (Note 2) VLTRDET Logic Low, ICLKENsink = 4 mA TRDET Leakage Current (Note 2) VHTRDET Logic High, VTRDET = VCC 30 mV 300 mV 3.0 mA +200 mV 50 kW SWITCH AMPLIFIER SW Common Mode Range (Note 2) SW Input Resistance VSW(X)CM RSW(X) −600 SWX = 0 V 20 35 ZERO CURRENT SWITCHING COMPARATOR SW ZCS Threshold VDCM(SW1) DCM mode, DPRSLP = 3.3 V −6.0 mV Masked Off Time tOFFMSKD Measured from PWM neg edge to Pos Edge 650 ns SYSTEM I/O BUFFERS VID[6:0], DPRSLP, PSI INPUTS Input Voltage Refers to input (driving) signal level Logic Low, Isink w 1 mA Logic High, Isource v −5 mA Input Current V = 0.2 V VID[6:0], DPRSLP (active pulldown to GND) PSI (active pullup to VCC) VID Delay Time (Note 2) VID any edge to FB change 10% 0.3 0.7 V mA −1.0 +2.0 200 ns EN INPUT Input Voltage Input Current Refers to input (driving) signal level Logic Low, Isink w 1 mA Logic High, Isource v −5 mA 0.3 1.8 EN = L or EN = H (Static) 0.8 V < EN < 1.6 V (During Transition) 10 70 Output Low Voltage Logic Low, Isink = 4 mA 10 Output High, Leakage Current Logic High, VCLKEN = VCC V nA mA CLKEN OUTPUT 200 mV 1.0 mA 100 mV V 0.6 V PWM, OD, AND DCM1 OUTPUT Output Low Voltage Logic Low, ISINK = 400 mA Logic High, ISOURCE = −400 mA 4.05 Phase Protection Threshold Logic Low during first 3 CLK = Phase active Logic High during first 3 CLK = Phase active 3.0 Phase Protection Current PWM = 0.2 V or higher 10 5.0 50 mA THERMAL MONITORING AND PROTECTION TTSENSE Voltage Range (Note 2) 0 1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested. http://onsemi.com 6 5.0 V ADP3210 ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 1.20 V to 1.500 V, PSI = 1.1 V, DPRSLP = GND, LLINE = CSREF, Current going into pin is positive. TA = −10°C to 100°C, unless otherwise noted. (Note 1) RREF = 80 kW Parameter Symbol Conditions Min Typ Max Units VCC = 5.0 V, TTSNS is falling 2.45 2.5 2.55 V 50 95 TTSENSE = 2.6 V −2.0 Logic Low, IVRTT(SINK) = 400 mA Logic High, IVRTT(SOURCE) = −400 mA 4.0 THERMAL MONITORING AND PROTECTION TTSENSE Threshold TTSENSE Hysteresis TTSENSE Bias Current VRTT Output Voltage VVRTT 10 5.0 mV 2.0 mA 100 mV V SUPPLY Supply Voltage Range VCC Supply Current VCC OK Threshold VCC UVLO Threshold 4.5 EN = H EN = 0 V VCCOK VCC is Rising VCCUVLO VCC is Falling 4.0 VCC Hysteresis (Note 2) 5.5 V 8.0 10 11 50 mA mA 4.4 4.5 V 4.15 V 150 mV 1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested. http://onsemi.com 7 ADP3210 TEST CIRCUITS 7−BIT CODE 5.0 V 3.3 V VCC VID6 PSI NC VID5 VID4 VID3 VID2 1 VID1 VID0 40 EN TTSN PWRGD VRTT IMON DCM1 CLKEN OD FBRTN PWM2 SW2 SW3 GND CSCOMP CSSUM RT RPM IREF ILIM DPRSLP CSREF PWM3 SW1 LLINE COMP NC TRDET RAMP 1 kW PWM1 ADP3210 FB 80 kW 20 kW 100 nF Figure 2. Closed−Loop Output Voltage Accuracy ADP3210 5.0 V 31 VCC 31 VCC 39 kW 100 nF 19 ADP3210 5.0 V CSCOMP 7 COMP 10 kW 18 1 kW 17 CSSUM CSREF 6 − − + + 1.0 V 16 DV CSCOMP * 1.0 V + − 20 GND V OS + FB 17 40 V 1.0 V Figure 3. Current Sense Amplifier VOS LLINE + − CSREF VID DAC + − 20 GND DV FB + FB DV + DV * FB DV+0 mV Figure 4. Positioning Accuracy http://onsemi.com 8 ADP3210 TYPICAL CHARACTERISTICS 400 1000 SWITCHING FREQUENCY (kHz) VID = 1.4125 V 350 FREQUENCY (kHz) 1.2125 V 1.1 V 0.8125 V 0.6125 V 300 250 200 2−Phase Configuration 100 10 100 150 1000 0 0.2 0.4 Figure 5. Master Clock Frequency vs. RT 0.8 1.0 1.2 1.4 Figure 6. Master Clock vs. VID 1.26 OUTPUT VOLTAGE (V) 0.6 VID (V) RT, RESISTANCE (kW) OUTPUT VOLTAGE 1.22 1.18 1 ENABLE 1.14 1.1 2 1.06 3 1.02 0 10 20 30 40 50 60 CLKEN PWRGD 4 70 1: 500 mV / div 3: 5.0 V / div 2 ms / div 2: 5.0 V / div 4: 5.0 V / div LOAD CURRENT (A) Figure 7. Load Line Accuracy Figure 8. Startup Waveforms OUTPUT VOLTAGE 3 OUTPUT VOLTAGE 3 PHASE 1 SWITCH NODE PHASE 1 SWITCH NODE 1 1 PHASE 2 SWITCH NODE PHASE 2 SWITCH NODE 2 2 1: 10 V / div 2: 10 V / div 3: 50 mV / div 1m s / div Input = 12 V, Output = 1.0 V 15 A to 50 A Load Step 1: 10 V / div 2: 10 V / div 3: 50 mV / div 1m s / div Input = 12 V, Output = 1.0 V 50 A to 15 A Load Step Figure 9. Load Transient with 2−Phases Figure 10. Load Transient with 2−Phases http://onsemi.com 9 ADP3210 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE OUTPUT VOLTAGE 1 1 PHASE 1 SWITCH NODE PHASE 1 SWITCH NODE 2 2 1: 50 mV / div 2: 10 V / div 4 ms / div Input = 12 V, Output = 1.0 V 3.0 A to 15 A Load Step 1: 50 mV / div 2: 10 V / div 4 ms / div Input = 12 V, Output = 1.0 V 15 A to 3.0 A Load Step Figure 11. Load Transient with 1−Phase Figure 12. Load Transient with 1−Phase OUTPUT VOLTAGE OUTPUT VOLTAGE CSCOMP TO CSREF CSCOMP TO CSREF COMP COMP PHASE 1 SWITCH NODE PHASE 1 SWITCH NODE 1: 10 V / div 3: 20 mV / div 1m s / div 2: 0.5 V / div 4: 5.0 mV / div Input = 12 V, Output = 1.0 V 2−Phase 1: 10 V / div 3: 20 mV / div 4ms / div 2: 0.5 V / div 4: 5.0 mV / div Input = 12 V, Output = 1.0 V Single−Phase DCM, 1.0 A Figure 13. Switching Waveforms Figure 14. Switching Waveforms OUTPUT VOLTAGE 3 OUTPUT VOLTAGE 4 PHASE 1 SWITCH NODE PWRGD 2 3 PHASE 1 and 2 LS GATE PHASE 2 SWITCH NODE 1 1.2 1: 5.0 V / div 3: 2.0 V / div 40ms / div 2: 5.0 V / div 4: 0.5 V / div Input = 12 V, Output = 1.0 V FB shortened to GND 1: 10 V / div 2: 10 V / div 3: 200 mV / div 100ms / div Input = 12 V, Output = 0.5 A 1.2 V to 0.7 V VID Step PSI = High, DPRSLP = High Figure 15. OVP and RVP Test Figure 16. VID Step http://onsemi.com 10 ADP3210 TYPICAL CHARACTERISTICS 3 OUTPUT VOLTAGE 3 OUTPUT VOLTAGE PHASE 1 SWITCH NODE PHASE 1 SWITCH NODE 2 2 PHASE 2 SWITCH NODE PHASE 2 SWITCH NODE 1 1 1: 10 V / div 2: 10 V / div 3: 200 mV / div 100ms / div Input = 12 V, Output = 0.5 A 0.7 V to 1.2 V VID Step PSI = High, DPRSLP = High 1: 10 V / div 2: 10 V / div 3: 200 mV / div 100ms / div Input = 12 V, Output = 0.5 A 1.2 V to 0.7 V VID Step PSI = High, DPRSLP = Low Figure 17. VID Step Figure 18. VID Step 3 OUTPUT VOLTAGE PHASE 1 SWITCH NODE 2 PHASE 2 SWITCH NODE 1 1: 10 V / div 2: 10 V / div 3: 200 mV / div 100ms / div Input = 12 V, Output = 0.5 A 0.7 V to 1.2 V VID Step PSI = High, DPRSLP = Low Figure 19. VID Step http://onsemi.com 11 ADP3210 Theory of Operation The PWM outputs are 5.0 V logic−level signals intended for driving external gate drivers such as the ADP3611. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can operate at a time to allow overlapping phases. The ADP3210 combines a multi−mode PWM Ramp Pulse Modulated (RPM) control with multiphase logic outputs for use in 1−, 2−, and 3−phase synchronous buck CPU core supply power converters. The internal 7−bit VID DAC conforms to Intel IMVP−6.5 specifications. Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling high currents in a single−phase converter puts high thermal stress on the system components such as the inductors and MOSFETs. The multi−mode control of the ADP3210 ensures a stable high performance topology for: • Balancing currents and thermals between phases • High speed response at the lowest possible switching frequency and minimal output decoupling • Minimizing thermal switching losses due to lower frequency operation • Tight load line regulation and accuracy • High current output by supporting up to 3−phase operation • Reduced output ripple due to multiphase ripple cancellation • High power conversion efficiency both at heavy load and light load • PC board layout noise immunity • Ease of use and design due to independent component selection • Flexibility in operation by allowing optimization of design for low cost or high performance Operation Modes For ADP3210, the number of phases can be selected by the user as described in the Number of Phases section, or they can dynamically change based on system signals to optimize the power conversion efficiency at heavy and light CPU loads. During a VID transient or at a heavy load condition, indicated by DPRSLP going low and PSI going high, the ADP3210 runs in full−phase mode. All user selected phases operate in interleaved PWM mode that results in minimal VCORE ripple and best transient performance. While in light load mode, indicated by either PSI going low or DPRSLP going high, only Phase 1 of ADP3210 is in operation to maximize power conversion efficiency. In addition to the change of phase number, the ADP3210 dynamically changes operation modes. In multiphase operation, the ADP3210 runs in PWM mode, with switching frequency controlled by the master clock. In single−phase mode based on PSI signal, the ADP3210 switches to RPM mode, where the switching frequency is no longer controlled by the master clock, but by the ripple voltage appearing on the COMP pin. The PWM1 pin is set to high each time the COMP pin voltage rises to a limit determined by the VID voltage and programmed by the external resistor connected from Pin RPM to ground. In single−phase mode based on the DPRSLP signal, the ADP3210 runs in RPM mode, with the synchronous rectifier (low−side) MOSFETs of Phase 1 being controlled by the DCM1 pin to prevent any reverse inductor current. Thus, the switch frequency varies with the load current, resulting in maximum power conversion efficiency in deeper sleep mode of CPU operation. In addition, during any VID transient, system transient (entry/exit of deeper sleep), or current limit, the ADP3210 goes into full phase mode, regardless of DPRSLP and PSI signals, eliminating current stress to Phase 1. Table 1 summarizes how the ADP3210 dynamically changes phase number and operation modes based on system signals and operating conditions. Number of Phases The number of operational phases and their phase relationship is determined by internal circuitry that monitors the PWM outputs. Normally, the ADP3210 operates as a 3−phase controller. For 2−phase operation, the PWM3 pin is connected to VCC 5.0 V, and for 1−phase operation, the PWM3 and PWM2 pins are connected to VCC 5.0 V. When the ADP3210 is initially enabled, the controller sinks 50 mA on the PWM2 and PWM3 pins. An internal comparator checks the voltage of each pin against a high threshold of 3.0 V. If the pin voltage is high due to pullup to the VCC 5.0 V rail, then the phase is disabled. The phase detection is made during the first three clock cycles of the internal oscillator. After phase detection, the 50 mA current sink is removed. The pins that are not connected to the VCC 5.0 V rail function as normal PWM outputs. The pins that are connected to VCC enter into high impedance state. http://onsemi.com 12 ADP3210 Table 1. Phase Number and Operation Modes PSI DPRSLP VID Transient Period (Note 1) Hit Current Limit No. of Phases Selected by User No. of Phases in Operation Operation Mode DNC DNC Yes DNC N 3, 2, or 1 N PWM, CCM Only 1 0 No DNC N 3, 2, or 1 N PWM, CCM Only 0 0 No No DNC Phase 1 only RPM, CCM Only 0 0 No Yes DNC N PWM, CCM Only DNC 1 No No DNC Phase 1 only RPM, Automatic CCM / DCM DNC 1 No Yes DNC N PWM, CCM Only 1. VID transient period is the time following any VID change, including entrance and exit of deeper sleep mode. The duration of VID transient period is the same as that of PWRGD masking time. 2. DNC = Do Not Care. 3. CCM = Continuous Conduction Mode. 4. DCM = Discontinuous Conduction Mode. VRMP FLIP−FLOP IR = AR x IRAMP S Q VCC GATE DRIVER RD DRVH PWM1 FLIP−FLOP 400 ns Q 1.0 V S DCM1 Q Q IN SW RI L RI L DRVLSD DRVL LOAD CR SW1 RD R2 R1 VCC GATE DRIVER PWM2 R2 30 mV R1 5.0 V 1.0 V CSREF VCS RA CA CFB SD DRVL SW2 VDC FB DRVH SW OD COMP IN CSSUM FBRTN LLINE CSCOMP CB RCS RPH CCS RPH RB Figure 20. Single−Phase RPM Mode Operation http://onsemi.com 13 ADP3210 VCC GATE DRIVER IR = AR x IRAMP DRVH FLIP−FLOP CLOCK OSCILLATOR S PWM1 Q IN SW RI L RI L LOAD DRVL RD CR SW1 AD 0.2 V VCC GATE DRIVER IR = AR x IRAMP DRVH FLIP−FLOP CLOCK OSCILLATOR S PWM2 Q IN SW DRVL RD CR SW2 AD VCC 0.2 V VDC CSREF VCS RAMP COMP FB RA CA CFB CSSUM FBRTN LLINE CB CSCOMP RCS RPH CCS RPH RB Figure 21. Dual−Phase PWM Mode Operation Switch Frequency Setting PWM1 pin is high, an internal ramp signal rises at a slew rate programmed by the current flowing into the RAMP pin. Once this internal ramp signal hits the COMP pin voltage, the PWM1 pin is reset to low. In continuous current mode, the switching frequency of RPM operation is maintained almost constantly. While in discontinuous current mode, the switching frequency reduces with the load current. Master Clock Frequency for PWM Mode The clock frequency of the ADP3210 is set by an external resistor connected from the RT pin to ground. The frequency varies with the VID voltage: the lower the VID voltage, the lower the clock frequency. The variation of clock frequency with VID voltage makes VCORE ripple remain constant and improves power conversion efficiency at a lower VID voltage. Figure 5 shows the relationship between clock frequency and VID voltage, parametrized by RT resistance. To determine the switching frequency per phase, the clock is divided by the number of phases in use. If PWM3 is pulled up to VCC, then the master clock is divided by 2 for the frequency of the remaining phases. If PWM2 and PWM3 are pulled up to VCC, then the switching frequency of a Phase 1 equals the master clock frequency. If all phases are in use, divide by 3. Output Voltage Differential Sensing The ADP3210 combines differential sensing with a high accuracy, VID DAC, precision REF output and a low offset error amplifier to meet the rigorous accuracy requirement of the Intel IMVP−6.5 specification. In steady−state, the VID DAC and error amplifier meet the worst−case error specification of ±10 mV over the full operating output voltage and temperature range. The CPU core output voltage is sensed between the FB and FBRTN pins. Connect FB through a resistor to the positive regulation point, usually the VCC remote sense pin of the microprocessor. Connect FBRTN directly to the negative remote sense point, the VSS sense point of the CPU. The internal VID DAC and precision voltage reference are referenced to FBRTN, and have a maximum current of 200 mA to guarantee accurate remote sensing. Switching Frequency for RPM Mode–Phase 1 When ADP3210 operates in single−phase RPM mode, its switching frequency is not controlled by the master clock, but by the ripple voltage on the COMP pin. The PWM1 pin is set high each time the COMP pin voltage rises to a voltage limit determined by the VID voltage and the external resistance connected from Pin RPM to ground. Whenever http://onsemi.com 14 ADP3210 Output Current Sensing Current Control Mode and Thermal Balance The ADP3210 provides a dedicated Current Sense Amplifier (CSA) to monitor the total output current of the converter for proper voltage positioning vs. load current, and for current limit detection. Sensing the load current being delivered to the load is inherently more accurate than detecting peak current or sampling the current across a sense element, such as the low−side MOSFET. The CSA can be configured several ways depending on system requirements. • Output inductor DCR sensing without use of a thermistor for lowest cost • Output inductor DCR sensing with use of a thermistor that tracks inductor temperature to improve accuracy • Discrete resistor sensing for highest accuracy The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. At the negative input CSSUM pin of the CSA, signals from the sensing element (that is, in case of inductor DCR sensing, signals from the switch node side of the output inductors) are summed together by using series summing resistors. The feedback resistor between CSCOMP and CSSUM sets the gain of the current sense amplifier, and a filter capacitor is placed in parallel with this resistor. The current information is then given as the voltage difference between CSREF and CSCOMP. This signal is used internally as a differential input for the current limit comparator. An additional resistor divider connected between CSREF and CSCOMP with the midpoint connected to LLINE can be used to set the load line required by the microprocessor specification. The current information for load line setting is then given as the voltage difference of CSREF − LLINE. The configuration in the previous paragraph makes it possible for the load line slope to be set independently of the current limit threshold. In the event that the current limit threshold and load line do not have to be independent, the resistor divider between CSREF and CSCOMP can be omitted and the CSCOMP pin can be connected directly to LLINE. To disable voltage positioning entirely (that is, to set no load line), tie LLINE to CSREF. To provide the best accuracy for current sensing, the CSA is designed to have a low offset input voltage. In addition, the sensing gain is set by an external resistor ratio. The ADP3210 has individual inputs for monitoring the current in each phase. The phase current information is combined with an internal ramp to create a current balancing feedback system that is optimized for initial current accuracy and dynamic thermal balance. The current balance information is independent of the total inductor current information used for voltage positioning described in the Active Impedance Control Mode section. The magnitude of the internal ramp can be set so the transient response of the system becomes optimal. The ADP3210 also monitors the supply voltage to achieve feed−forward control whenever the supply voltage changes. A resistor connected from the power input voltage rail to the RAMP pin determines the slope of the internal PWM ramp. Detailed information about programming the ramp is given in the Ramp Resistor Selection section. External resistors are placed in series with the SW1, SW2 and SW3 pins to create an intentional current imbalance, if desired. Such a condition can exist when one phase has better cooling and supports higher currents than the other phase. Resistor RSW2 and Resistor RSW3 (see the Typical Application Circuit in Figure 24.) can be used to adjust thermal balance. It is recommended to add these resistors during the initial design to make sure placeholders are provided in the layout. To increase the current in any given phase, users should make RSW for that phase larger (that is, make RSW = 1 kW for the hottest phase and do not change it during balance optimization). Increasing RSW to 1.5 kW makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve thermal balance starting with the coolest phase. If adjusting current balance between phases is not needed, switch resistors should be 1 kW for all phases. Voltage Control Mode A high gain bandwidth error amplifier is used for the voltage−mode control loop. The non−inverting input voltage is set via the 7−bit VID DAC. The VID codes are listed in Table 2. The non−inverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. The output of the error amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input, FB, is tied to the output sense location through a resistor, RB, for sensing and controlling the output voltage at the remote sense point. The main loop compensation is incorporated in the feedback network connected between FB and COMP. Active Impedance Control Mode To control the dynamic output voltage droop as a function of the output current, the signal proportional to the total output current is converted to a voltage that appears between CSREF and LLINE. This voltage can be scaled to equal the droop voltage, which is calculated by multiplying the droop impedance of the regulator with the output current. The droop voltage is then used as the control voltage of the PWM regulator. The droop voltage is subtracted from the DAC reference output voltage and determines the voltage positioning set−point. The setup results in an enhanced feed−forward response. Power−Good Monitoring The power−good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open drain output that can be pulled up through an external resistor to a voltage rail that is not necessarily the same VCC voltage rail of the http://onsemi.com 15 ADP3210 controller. Logic high level indicates that the output voltage is within the voltage limits defined by a window around the VID voltage setting. PWRGD goes low when the output voltage is outside of that window. Following the IMVP−6.5 specification, PWRGD window is defined as −300 mV below and +200 mV above the actual VID DAC output voltage. For any DAC voltage below 300 mV, only the upper limit of the PWRGD window is monitored. To prevent false alarm, the power−good circuit is masked during various system transitions, including any VID change and entrance/exit out of deeper sleep. The duration of the PWRGD mask time is set by an internal clock to approximately 100 ms. During a VID change, the PWRGD signal is masked to prevent false PWRGD glitches. The PWRGD is masked for approximately 100 ms after a VID change. from one VID code to another. This reducing the inrush current and helps decrease the acoustic noise generated by the MLCC input capacitors and inductors. The ADP3210 also offers soft transient control for large VID step changes. When the VID is changed, the ADP3210 changes the output voltage 1 LSB every 1 ms. The output voltage slew rate is controlled to 12.5 mV/ms. Current Limit, Short−Circuit, and Latchoff Protection The ADP3210 compares the differential output of a current sense amplifier to a programmable current limit set−point to provide current limiting function. The current limit set point is set with a resistor connected from ILIM pin to CSCOMP pin. This is the RLIM resistor. During normal operation, the voltage on the ILIM pin is equal to the CSREF pin. The voltage across RLIM is equal to the voltage across the current sense amplifier (from CSREF pin to CSCOMP pin). This voltage is proportional to output current. The current through RLIM is proportional to the output inductor current. The current through RLIM is compared with an internal reference current. When the RLIM current goes above the internal reference current, the ADP3210 goes into current limit. The current limit circuit is shown in Figure 23. In 3 phase configuration with all 3 phase switching, current limit occurs when the current in the RLIM resistor is 20 mA. In 3 phase configuration with only phase 1 switching, current limit occurs when the current in the RLIM resistor is 6.7 mA. In 2 phase configuration with both phases switching, current limit occurs when the current in the RLIM resistor is 20 mA. In 2 phase configuration with only phase 1 switching, current limit occurs when the current in the RLIM resistor is 10 mA. In single phase configuration, current limit occurs when the current in the RLIM resistor is 20 mA. Powerup Sequence and Soft−Start The power−on ramp−up time of the output voltage is set internally. During startup, the ADP3210 steps sequentially through each VID code until it reaches the boot voltage. The whole powerup sequence, including soft−start, is illustrated in Figure 22. After EN is asserted high, the soft−start sequence starts. The core voltage ramps up linearly to the boot voltage. The ADP3210 regulates at the boot voltage for 100 ms. After the boot time is completed, CLKEN is asserted low. After CLKEN is asserted low for 9 ms, PWRGD is asserted high. In VCC UVLO or in shutdown, a small MOSFET turns on connecting the CSREF to GND. The MOSFET on the CSREF pin has a resistance of approximately 100 W. When VCC ramps above the upper UVLO threshold and EN is asserted high, the ADP3210 enables internal bias and starts a reset cycle that lasts about 50 ms to 60 ms. Next, when initial reset is over, the chip detects the number of phases set by the user, and gives a go signal to start soft−start. The ADP3210 reads the VID codes provided by the CPU on VID0 to VID6 input pins after CLKEN is asserted low. 20 mA CLA VI CONV − ILIM ILIM + − + CSA VCC − ILIM EN CCS t BOOT CSSUM L RPH DCR CBULK Figure 23. Current Limit Circuit During startup when the output voltage is below 200 mV, a secondary current limit is activated. This is necessary because the voltage swing on CSCOMP cannot extend below ground. The secondary current limit circuit clamps the internal COMP voltage and sets the internal compensation ramp termination voltage at 1.5 V level. The clamp actually limits voltage drop across the low side MOSFETs through the current balance circuitry. CLKEN t CPU_PWRGD PWRGD CSREF CSCOMP RCS VCORE + Figure 22. Powerup Sequence Soft Transient The IMVP−6.5 specification requires the CPU to step through the VID codes in 12.5mV steps when transitioning http://onsemi.com 16 ADP3210 An inherent per phase current limit protects individual phases in case one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal−mode COMP voltage. After 9 ms in current limit, the ADP3210 will latchoff. The latchoff can be reset by removing and reapplying VCC, or by recycling the EN pin low and high for a short time. turned off. The reverse inductor current can be quickly reset to zero by dumping the energy built up in the inductor into the input dc voltage source via the forward−biased body diode of the high−side MOSFETs. The RVP function is terminated when the CSREF pin voltage returns above −100 mV. Occasionally, overvoltage crowbar protection results in negative VCORE voltage, because turn−on of all low−side MOSFETs leads to very large reverse inductor current. To prevent damage of the CPU by negative voltage, ADP3210 keeps its RVP monitoring function alive even after OVP latchoff. During OVP latchoff, if the CSREF pin voltage drops below −300mV, then all low−side MOSFETs are turned off by setting both DCM1 and OD low. DCM1 and OD pins are set high again when CSREF voltage recovers above −100 mV. Changing VID OTF The ADP3210 is designed to track dynamically changing VID code. As a result, the converter output voltage, that is, the CPU VCC voltage, can change without the need to reset either the controller or the CPU. This concept is commonly referred to as VID OTF transient. A VID OTF can occur either under light load or heavy load conditions. The processor signals the controller by changing the VID inputs in LSB incremental steps from the start code to the finish code. The change can be either upwards or downwards steps. When a VID input changes state, the ADP3210 detects the change but ignores the new code for a minimum of time of 400 ns. This keep out is required to prevent reaction to false code that can occur by a skew in the VID code while the 7−bit VID input code is in transition. Additionally, the VID change triggers a PWRGD masking timer to prevent a PWRGD failure. Each VID change resets and re−triggers the internal PWRGD masking timer. As listed in Table 2, during any VID transient, the ADP3210 forces a multiphase PWM mode regardless of system input signals. Output Enable and UVLO The VCC supply voltage to the controller must be higher than the UVLO upper threshold, and the EN pin must be higher than its logic threshold so the ADP3210 can begin switching. If the VCC voltage is less than the UVLO threshold, or the EN pin is logic low, then the ADP3210 is in shutdown. In shutdown, the controller holds the PWM outputs at ground, shorts the SS pin and PGDELAY pin capacitors to ground, and drives DCM1 and OD pins low. Proper power supply sequencing during startup and shutdown of the ADP3210 must be adhered to. All input pins must be at ground prior to applying or removing VCC. All output pins should be left in high impedance state while VCC is off. Output Crowbar To protect the CPU load and output components of the converter, the PWM outputs are driven low, DCM1 and OD are driven high (that is, commanded to turn on the low−side MOSFETs of all phases) when the output voltage exceeds an OVP threshold of 1.55 V as specified by IMVP−6.5. Turning on the low−side MOSFETs discharges the output capacitor as soon as reverse current builds up in the inductors. If the output overvoltage is due to a short of the high−side MOSFET, then this crowbar action current limits the input supply or causes the input rail fuse to blow, protecting the microprocessor from destruction. Once overvoltage protection (OVP) is triggered, the ADP3210 is latched off. The latchoff function can be reset by removing and reapplying VCC, or by recycling EN low and high for a short time. Output Current Monitor The ADP3210 has an output current monitor. The IMON pin sources a current proportional to the inductor current. A resistor from IMON pin to FBRTN sets the gain. A 0.1 mF is added in parallel with RMON to filter the inductor ripple. The IMON pin is clamped to prevent it from going above 1.15 V. Thermal Throttling Control The ADP3210 includes a thermal monitoring circuit to detect if the temperature of the variable resistor (VR) has exceeded a user−defined thermal throttling threshold. The thermal monitoring circuit requires an external resistor divider connected between the VCC pin and GND. The divider consists of an NTC thermistor and a resistor. To generate a voltage that is proportional to temperature, the midpoint of the divider is connected to the TTSN pin. Whenever the temperature trips the set alarm threshold, an internal comparator circuit compares the TTSN voltage to a half VCC threshold and outputs a logic level signal at the VRTT output. The VRTT output is designed to drive an external transistor that, in turn, provides the high current, open drain VRTT signal that is required by the IMVP−6.5 specification. When the temperature is around the set alarm point, the internal VRTT comparator has a hysteresis of about 100 mV to prevent high frequency oscillation of VRTT. Reverse Voltage Protection Very large reverse currents in inductors can cause negative VCORE voltage, which is harmful to the CPU and other output components. ADP3210 provides Reverse Voltage Protection (RVP) function without additional system cost. The VCORE voltage is monitored through the CSREF pin. Any time the CSREF pin voltage is below −300 mV, the ADP3210 triggers its RVP function by disabling all PWM outputs and setting both DCM1 and OD pins low. Thus, all the MOSFETs are http://onsemi.com 17 ADP3210 Table 2. VID Code Table VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output (V) 0 0 0 0 0 0 0 1.5000 0 0 0 0 0 0 1 1.4875 0 0 0 0 0 1 0 1.4750 0 0 0 0 0 1 1 1.4625 0 0 0 0 1 0 0 1.4500 0 0 0 0 1 0 1 1.4375 0 0 0 0 1 1 0 1.4250 0 0 0 0 1 1 1 1.4125 0 0 0 1 0 0 0 1.4000 0 0 0 1 0 0 1 1.3875 0 0 0 1 0 1 0 1.3750 0 0 0 1 0 1 1 1.3625 0 0 0 1 1 0 0 1.3500 0 0 0 1 1 0 1 1.3375 0 0 0 1 1 1 0 1.3250 0 0 0 1 1 1 1 1.3125 0 0 1 0 0 0 0 1.3000 0 0 1 0 0 0 1 1.2875 0 0 1 0 0 1 0 1.2750 0 0 1 0 0 1 1 1.2625 0 0 1 0 1 0 0 1.2500 0 0 1 0 1 0 1 1.2375 0 0 1 0 1 1 0 1.2250 0 0 1 0 1 1 1 1.2125 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.0750 0 1 0 0 0 1 1 1.0625 0 1 0 0 1 0 0 1.0500 0 1 0 0 1 0 1 1.0375 0 1 0 0 1 1 0 1.0250 0 1 0 0 1 1 1 1.0125 0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 http://onsemi.com 18 ADP3210 Table 2. VID Code Table VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output (V) 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.9000 0 1 1 0 0 0 1 0.8875 0 1 1 0 0 1 0 0.8750 0 1 1 0 0 1 1 0.8625 0 1 1 0 1 0 0 0.8500 0 1 1 0 1 0 1 0.8375 0 1 1 0 1 1 0 0.8250 0 1 1 0 1 1 1 0.8125 0 1 1 1 0 0 0 0.8000 0 1 1 1 0 0 1 0.7875 0 1 1 1 0 1 0 0.7750 0 1 1 1 0 1 1 0.7625 0 1 1 1 1 0 0 0.7500 0 1 1 1 1 0 1 0.7375 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.7125 1 0 0 0 0 0 0 0.7000 1 0 0 0 0 0 1 0.6875 1 0 0 0 0 1 0 0.6750 1 0 0 0 0 1 1 0.6625 1 0 0 0 1 0 0 0.6500 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.4625 1 0 1 0 1 0 0 0.4500 1 0 1 0 1 0 1 0.4375 1 0 1 0 1 1 0 0.4250 1 0 1 0 1 1 1 0.4125 http://onsemi.com 19 ADP3210 Table 2. VID Code Table VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output (V) 1 0 1 1 0 0 0 0.4000 1 0 1 1 0 0 1 0.3875 1 0 1 1 0 1 0 0.3750 1 0 1 1 0 1 1 0.3625 1 0 1 1 1 0 0 0.3500 1 0 1 1 1 0 1 0.3375 1 0 1 1 1 1 0 0.3250 1 0 1 1 1 1 1 0.3125 1 1 0 0 0 0 0 0.3000 1 1 0 0 0 0 1 0.2875 1 1 0 0 0 1 0 0.2750 1 1 0 0 0 1 1 0.2625 1 1 0 0 1 0 0 0.2500 1 1 0 0 1 0 1 0.2375 1 1 0 0 1 1 0 0.2250 1 1 0 0 1 1 1 0.2125 1 1 0 1 0 0 0 0.2000 1 1 0 1 0 0 1 0.1875 1 1 0 1 0 1 0 0.1750 1 1 0 1 0 1 1 0.1625 1 1 0 1 1 0 0 0.1500 1 1 0 1 1 0 1 0.1375 1 1 0 1 1 1 0 0.1250 1 1 0 1 1 1 1 0.1125 1 1 1 0 0 0 0 0.1000 1 1 1 0 0 0 1 0.0875 1 1 1 0 0 1 0 0.0750 1 1 1 0 0 1 1 0.0625 1 1 1 0 1 0 0 0.0500 1 1 1 0 1 0 1 0.0375 1 1 1 0 1 1 0 0.0250 1 1 1 0 1 1 1 0.0125 1 1 1 1 0 0 0 0.0000 1 1 1 1 0 0 1 0.0000 1 1 1 1 0 1 0 0.0000 1 1 1 1 0 1 1 0.0000 1 1 1 1 1 0 0 0.0000 1 1 1 1 1 0 1 0.0000 1 1 1 1 1 1 0 0.0000 1 1 1 1 1 1 1 0.0000 http://onsemi.com 20 21 http://onsemi.com CFB 18pF RA CA 220pF 33.2kW 1% VCC(SENSE) VSS(SENSE) RB 1.67kW 1% CB 330pF CLKEN IMON R3 5.9kW R2 3kW V3_3S EN PWRGD IMON CLKEN FBRTN FB COMP NC TRDET DPRSLP C63 C33 R5 C11 1000p VDC C12 1nF RCS1 73.2kW RPH1 93.1kW 1% 5V VR ON 8 7 6 SW CROWBAR GND DRVL DRVLSD 4 5 6 VCC 5 U3 ADP3611 DRVL 7 SW DRVLSD CROWBAR GND 3 4 SD 2 8 BST 9 IN DRVH 1 U2 ADP3611 VCC 10 9 DRVH SD 3 2 10 BST IN 1 Figure 24. Typical Application Circuit VCC(CORE) RTN CCS1 1.8nF CCS2 47pF RPH2 93.1kW 1% RCS2 165kW RSW2* RSW1* VRTT C9 10nF + C8 10mF / 25V x 8 + C1 R4 6.81kW 1% TTSNS VRTT DCM1 OD PWM1 PWM2 PWM3 SW1 SW2 SW3 VCC(CORE) R17280kΩ R180W + R15 80.6K 1% 200kW R14 7.15kW 1% CSCOMP 1 40 FROM CPU** U1 ADP3210 R16 + C3 0.1mF R1 3kW C11 1mF R3 10W VID6 PSI NC VCC ILIM IREF RPM RT RAMP LLINE CSREF CSSUM CSCOMP GND DPRSLPVR VR_ON IMVP6_PWRGD VID0 VID1 VID2 VID3 VID4 V5S RTH1 100kW, 5% NTC VDC RTN VDC R30 0W C19 1nF Q6 NTMF4821N L1 360nH/0.89mW Q7 Q8 NTMFS4846N NTMFS4846N Q5 NTMF4821N C16 1nF C20 + 330mFx 4 6mW EACH RTH2 220kW, 5% NTC Q2 NTMF4821N L2 360nH/0.89mW Q4 Q3 NTMFS4846NNTMFS4846N Q1 NTMF4821N C30 0.47mF R31 C31 0W 0.47mF C25 + 10mFx32 MLCC IN & AROUND SOCKET V CC(CORE) RTN VCC(CORE) 0.3 V − 1.5 V 44 A ADP3210 ADP3210 Application Information The design parameters for a typical Intel IMVP6.5− compliant CPU Core VR application are as follows: • Maximum input voltage (VINMAX) = 19 V • Minimum input voltage (VINMIN) = 7.0 V • Output voltage by VID setting (VVID) = 1.150 V • Maximum output current (IO) = 55 A • Load line slope (RO) = 2.1 mW • Maximum output current step (DIO) = 34.5 A • Maximum output thermal current (IOTDC) = 32 A • Number of phases (n) = 3 • Switching frequency per phase (fSW) = 280 kHz • Duty cycle at maximum input voltage (DMIN) = 0.061 • Duty cycle at minimum input voltage (DMAX) = 0.164 IR + Lw Lw n 2 f SW 9 pF * 16 kW (1 * (n f SW (eq. 2) D MIN)) (1 * D MIN) V RIPPLE 1.150 V 2.1 mW (1 * (2 (eq. 3) 280 kHz 0.061)) (1 * 0.061) 20 mV + 356 nH (eq. 4) If the ripple voltage ends up being less than the initially selected value, then the inductor can be changed to a smaller value until the ripple value is met. This iteration allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 360 nH inductor is a good starting point, and gives a calculated ripple current of 10.7 A. The inductor should not saturate at the peak current of 27.4 A, and should be able to handle the sum of the power dissipation caused by the average current of 16 A in the winding and core loss. Another important factor in the inductor design is the DCR, which is used to measure phase currents. A large DCR causes excessive power losses, though too small a value leads to increased measurement error. This example uses an inductor with a DCR of 0.89 mW. In PWM mode operation, The ADP3210 uses a fixed−frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which directly relates to switching losses, and the sizes of the inductors and input and output capacitors. In a 2−phase design, a clock frequency of 560 kHz sets the switching frequency to 280 kHz per phase. This selection represents a trade−off between the switching losses and the minimum sizes of the output filter components. To achieve a 560 kHz oscillator frequency at VID voltage 1.150 V, RT has to be 196 kW. Alternatively, the value for RT can be calculated using: RT + RO L f SW Solving Equation 3 for a 20 mV peak−to−peak output ripple voltage yields: Setting the Clock Frequency for PWM Mode V VID ) 1.0 V V VID ǒ1 * D MINǓ V VID Selecting a Standard Inductor Once the inductance and DCR are known, the next step is to either design an inductor or select a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to keep the accuracy of the system controlled; 20% inductance and 15% DCR (at room temperature) are reasonable assumptions that most manufacturers can meet. (eq. 1) where 9 pF and 16 kW are internal IC component values. For good initial accuracy and frequency stability, it is recommended to use a 1% resistor. Inductor Selection The choice of inductance determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs. However, this allows the use of smaller−size inductors, and for a specified peak−to−peak transient deviation, it allows less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger size inductors and more output capacitance for the same peak−to−peak transient deviation. In a multiphase converter, the practical peak−to−peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 2 shows the relationship between the inductance, oscillator frequency, and peak−to−peak ripple current. Equation 3 can be used to determine the minimum inductance based on a given output ripple voltage. Power Inductor Manufacturers The following companies provide surface mount power inductors optimized for high power applications upon request: • Vishay Dale Electronics, Inc. − http://www.vishay.com • Panasonic − http://www.panasonic.com • Sumida Corporation − http://www.sumida.com • NEC Tokin Corporation − http://www.nec−tokin.com Output Droop Resistance The inductor design requires that the regulator output voltage measured at the CPU pins drops when the output current increases. The specified voltage drop corresponds to a dc output resistance (RO). http://onsemi.com 22 ADP3210 The output current is measured by summing the currents of the resistors monitoring the voltage across each inductor and by passing the signal through a low−pass filter. This summer−filter is implemented by the CS amplifier that is configured with resistors RPH(X) (summer), and RCS and CCS (filter). The output resistance of the regulator is set by the following equations, where RL is the DCR of the output inductors: RO + R CS C CS + 220 kW @ 220 kW + 93.2 kW (eq. 8) With the inductor DCR used as a sense element, and copper wire being the source of the DCR, users need to compensate for temperature changes in the inductor’s winding. Fortunately, copper has a well−known temperature coefficient (TC) of 0.39%/°C. If RCS is designed to have an opposite sign but equal percentage change in resistance, then it cancels the temperature variation of the inductor DCR. Due to the nonlinear nature of NTC thermistors, series resistors, RCS1 and RCS2 (see Figure 25) are needed to linearize the NTC and produce the desired temperature coefficient tracking. (eq. 5) L R L @ R CS 360 nH 0.89 mW 2.1 mW The standard 1% resistor for RPH(X) is 93.1 kW. (eq. 6) Users have the flexibility of choosing either RCS or RPH(X). Due to the current drive ability of the CSCOMP pin, the RCS resistance should be larger than 100 kW. For example, users should initially select RCS to be equal to 220 kW, then use Equation 6 to solve for CCS: C CS + 0.89 mW R PH(X) w Inductor DCR Temperature Correction RL R PH(x) Because CCS is not the standard capacitance, it is implemented with two standard capacitors in parallel: 1.8 nF and 47 pF. For the best accuracy, CCS should be a 5% NPO capacitor. Next, solve RPH(X) by rearranging Equation 5. + 1.84 nF (eq. 7) Place as close as possible to nearest inductor To Switch Node RTH To VOUT Sense ADP3210 CSCOMP − + CSSUM CSREF RCS1 RCS2 RPH1 RPH2 RPH3 19 CCS Keep This Path As Short As Possible And Well Away From Switch Node Lines 18 17 Figure 25. Temperature−Compensation Circuit Values The following procedure and equations yield values for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given RCS value: 1. Select an NTC to be used based on type and value. Because there is no value yet, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. 2. Based on the type of NTC, find its relative resistance value at two temperatures. Temperatures that work well are 50°C and 90°C. These are called Resistance Value A (A is RTH(50°C)/RTH(25°C)) and Resistance Value B (B is RTH(90°C)/RTH(25°C)). Note that the relative value of NTC is always 1 at 25°C. 3. Next, find the relative value of RCS that is required for each of these temperatures. This is based on the percentage of change needed, which is initially 0.39%/°C. These are called r1 and r2. r1 + r2 + where: TC = 0.0039 T1 = 50°C T2 = 90°C. 4. Compute the relative values for rCS1, rCS2, and rTH using: r CS2 + (A * B) A r CS1 + r TH + (T 1 * 25) 1 1 ) TC r2 * A (1 * B) (1 * B) r1 * B r2 ) B (1 * A) (1 * A) r1 r 2 * (A * B) (1 * A) 1 1*r CS2 *r 1 1 *r CS2 1 1 1*r CS2 *r 1 (eq. 10) CS1 5. Calculate RTH = RTH x RCS, then select the closest value of thermistor that is available. Also, compute a scaling factor k based on the ratio of the actual thermistor value relative to the computed one. 1 1 ) TC r1 (eq. 9) (T 2 * 25) k+ http://onsemi.com 23 R TH(ACTUAL) R TH(CALCULATED) (eq. 11) ADP3210 6. Finally, calculate values for RCS1 and RCS2 using: R CS1 + R CS k R CS2 + R CS ((1 * k) ) (k To meet the conditions of these equations and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance, RO. If the CX(MIN) is larger than CX(MAX), the system does not meet the VID OTF and/or deeper sleep exit specification and can require a smaller inductor or more phases (the switching frequency can also have to be increased to keep the output ripple the same). For example, if using 32 pieces of 10 mF 0805 MLC capacitors (CZ = 320 mF), the fastest VID voltage change is the exit of deeper sleep, and VCORE change is 220 mV in 22 ms with a setting error of 10 mV. Where K = 3.1, solving for the bulk capacitance yields: r CS1 r CS2)) (eq. 12) This example starts with a thermistor value of 100 kW and uses a Vishay NTHS0603N04 NTC thermistor (a 0603 size thermistor) with A = 0.3359 and B = 0.0771. From this data, rCS1 = 0.359, rCS2 = 0.729 and rTH = 1.094. Solving for RTH yields 240 kW, so 220 kW is chosen, making k = 0.914. Finally, RCS1 and RCS2 are 72.3 kW and 166 kW. Choosing the closest 1% resistor values yields a choice of 71.5 kW and 165 kW. ȡ 360 nH ȧ ǒ Ȣ2 2.1 mW ) COUT Selection The required output decoupling for processors and platforms is typically recommended by Intel. The following guidelines can also be used if both bulk and ceramic capacitors in the system: • Select the total amount of ceramic capacitance. This is based on the number and type of capacitors to be used. The best location for ceramics is inside the socket; 20 pieces of Size 0805 being the physical limit. Additional capacitors can be placed along the outer edge of the socket. • Select the number of ceramics and find the total ceramic capacitance (CZ). Combined ceramic values of 200 mF to 300 mF are recommended and are usually made up of multiple 10 mF or 22 mF capacitors. • Note that there is an upper limit imposed on the total amount of bulk capacitance (CX) when considering the VID OTF output voltage stepping (voltage step VV in time tV with error of VERR), and also a lower limit based on meeting the critical capacitance for load release at a given maximum load step DIO. For a step−off load current, the current version of the IMVP−6 specification allows a maximum VCORE overshoot (VOSMAX) of 10 mV, plus 1.5% of the VID voltage. For example, if the VID is 1.150 V, then the largest overshoot allowed is 27 mV. C x(MIN) ȡ wȧ Ȣn ǒR C X(MAX) v Ǹ DI O DI O ȣ *C ȧ Ȥ C X(MAX) v V VID Ǔ ȣȧ V VID nKR O Vv L LX v C2 ǒ Ǔ K + −1n Ǔ 1.150 V + 0.8 mF 220 mV 1.150 V 1.150 V 2 220 mV 3.1 Ǔ ȣȧ 2.1 mW 360 nH 2 *1 Ȥ * 320 mF + 2.3 mF Q2 (2.1 mW) 2 2 + 2 nH (eq. 17) where: Q is limited to the square root of 2 to ensure a critically damped system. In this example, LX is about 250 pH for the four SP capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased if there is excessive ringing. Note that for this multi−mode control technique, an all−ceramic capacitor design can be used as long as the conditions of Equation(s) 13, 14, and 15 are satisfied. (eq. 13) Power MOSFETs For normal 20 A per phase application, the N−channel power MOSFETs are selected for two high−side switches and two low−side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS and RDS(ON). Because the gate drive voltage (the supply voltage to the ADP3611) is 5.0 V, logic−level threshold MOSFETs must be used. * 1 * Cz (eq. 14) V ERR VV 34.5 A (2.1 mW) 2 RO 2 L X v C 320 mF 2 Ȥ 50 mV ȣ ȧ Ȥ * 320 mF Using four 330 mF Panasonic SP capacitors with a typical ESR of 6 mW each yields CX = 1.32 mF with an RX = 1.5 mW. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using: Vv ǒ 2 3.1 2 34.5 A (eq. 16) V VID 1 ) tv 360 nH ȡǸ1 ) ǒ22 ms ȧ Ȣ z Ǔ V OSMAX O) L nK 2R O 2 ȡ ȧ Ȣ where: L C X(MIN) w (eq. 15) http://onsemi.com 24 ADP3210 The maximum output current IO determines the RDS(ON) requirement for the low−side (synchronous) MOSFETs. In the ADP3210, currents are balanced between phases; the current in each low−side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following equation shows the total power dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO): P SF + (1 * D) ƪǒ IO Ǔ 2 n SF ) 1 12 ǒ n Ǔƫ IR nSF V CC n MF IO RG n C ISS ) 1 12 n MF ǒ n Ǔƫ IR n MF 2 R DS(MF) (eq. 20) 2 n MF 2 where: RDS(MF) is the on−resistance of the MOSFET. Typically, for main MOSFETs, users want the highest speed (low CISS) device, but these usually have higher on−resistance. Users must select a device that meets the total power dissipation (0.6 W for a single 8−lead SOIC package) when combining the switching and conduction losses. For example, using an IRF7821 device as the main MOSFET (four in total; that is, nMF = 4), with about CISS = 1010 pF (max) and RDS(MF) = 18 mW (max at TJ = 120°C) and an IR7832 device as the synchronous MOSFET (four in total; that is, nSF = 4), RDS(SF) = 6.7 mW (max at TJ = 120°C). Solving for the power dissipation per MOSFET at IO = 32 A and IR = 10.7 A yields 420 mW for each synchronous MOSFET and 410 mW for each main MOSFET. One last consideration is the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation: R DS(SF) Knowing the maximum output thermal current and the maximum allowed power dissipation, users can find the required RDS(ON) for the MOSFET. For 8−lead SOIC or 8−lead SOIC compatible packaged MOSFETs, the junction to ambient (PCB) thermal impedance is 50°C/W. In the worst case, the PCB temperature is 90°C during heavy load operation of the notebook; a safe limit for PSF is 0.6 W at 120°C junction temperature. Thus, for this example (32 A maximum thermal current), RDS(SF) (per MOSFET) is less than 9.6 mW for two pieces of low−side MOSFET. This RDS(SF) is also at a junction temperature of about 120°C; therefore, the RDS(SF) (per MOSFET) should be lower than 6.8 mW at room temperature, giving 9.6 mW at high temperature. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn−on of the synchronous MOSFETs when the switch node goes high. The high−side (main) MOSFET has to be able to handle two main power dissipation components, conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, Equation 19 provides an approximate value for the switching loss per main MOSFETs: f SW IO P C(MF) + D (eq. 18) P S(MF) + 2 ƪǒ Ǔ P DRV + ƪ f SW 2 ǒnMF n Q GMF ) n SF ƫ Q GSFǓ ) I CC V CC (eq. 21) where: QGMF is the total gate charge for each main MOSFET. QGSF is the total gate charge for each synchronous MOSFET. Also shown is the standby dissipation (ICC x VCC) of the driver. For the ADP3419, the maximum dissipation should be less than 300 mW, considering its thermal impedance is 220°C/W and the maximum temperature increase is 50°C. For this example, with ICC = 2 mA, QGMF = 14 nC and QGSF = 51 nC, there is 120 mW dissipation in each driver, which is below the 300 mW dissipation limit. See the ADP3419 data sheet for more details. Ramp Resistor Selection The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. Use this equation to determine a starting value: (eq. 19) where: nMF is the total number of main MOSFETs. RG is the total gate resistance (1.5 W for the ADP3419 and about 0.5 W for two pieces of typical high speed switching MOSFETs, making RG = 2 W). CISS is the input capacitance of the main MOSFET. The best thing to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by: RR + RR + http://onsemi.com 25 AR 3 AD 0.5 3 5 L R DS CR 360 nH 5.2 mW 5 pF (eq. 22) + 462 kW ADP3210 Current Limit Set−point where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS is the total low−side MOSFET ON−resistance, CR is the internal ramp capacitor value. Another consideration in the selection of RR is the size of the internal ramp voltage (see Equation 23). For stability and noise immunity, keep this ramp size larger than 0.5 V. Taking this into consideration, the value of RR is selected as 280 kW. The internal ramp voltage magnitude can be calculated using: VR + VR + AR (1 * D) RR 0.5 CR R LIM + f SW (eq. 23) 1.150 V 5 pF 280 kHz + 0.83 V The size of the internal ramp can be made larger or smaller. If it is made larger, then stability and transient response improves, but thermal balance degrades. Likewise, if the ramp is made smaller, then thermal balance improves at the sacrifice of transient response and stability. The factor of three in the denominator of Equation 22 sets a minimum ramp size that gives an optimal balance for good stability, transient response, and thermal balance. I PHLIM ^ During the RPM mode operation of Phase 1, the ADP3210 runs in pseudo constant frequency, given that the load current is high enough for continuous current mode. While in discontinuous current mode, the switching frequency is reduced with the load current in a linear manner. When considering power conversion efficiency in light load, lower switching frequency is usually preferred for RPM mode. However, the VCORE ripple specification in the IMVP−6 sets the limitation for lowest switching frequency. Therefore, depending on the inductor and output capacitors, the switching frequency in RPM mode can be equal, larger, or smaller than its counterpart in PWM mode. A resistor from RPM to GND sets the pseudo constant frequency as following: 2 RT V VID ) 1.0 V AR RR (1 * D) CR V VID f SW 2 280 kW 1.150 V ) 1.0 V 0.5 462 kW 5 pF AD R DS(MAX) ) IR 2 (eq. 27) V COMP(MAX) * V BIAS VR (eq. 28) For this example, the duty−cycle limit at maximum input voltage is found to be 0.25 when D is 0.061. Output Current Monitor * 0.5 kW The ADP3210 has output current monitor. The IMON pin sources a current proportional to the total inductor current. A resistor, RMON, from IMON to FBRTN sets the gain of the output current monitor. A 0.1 mF is placed in parallel with RMON to filter the inductor current ripple and high frequency load transients. Since the IMON pin is connected directly to the CPU, it is clamped to prevent it from going above 1.15 V. The IMON pin current is equal to the RLIM times a fixed gain of 10. RMON can be found using the following equation: (eq. 24) (1 * 0.061) (eq. 26) 20 mA V COMP(MAX) * V R * V BIAS D LIM + D MIN where: AR is the internal ramp amplifier gain. CR is the internal ramp capacitor value. RR is an external resistor on the RAMPADJ pin to set the internal ramp magnitude. Because RR = 280 kW, the following resistance sets up 300 kHz switching frequency in RPM operation. R RPM + RO For the ADP3210, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.0 V, and the current balancing amplifier gain (AD) is 5. Using a VR of 0.55 V, and a RDS(MAX) of 3.8 mW (low−side on−resistance at 150°C) results in a per−phase limit of 85 A. Although this number seems high, this current level can only be reached with a absolute short at the output and the current limit latchoff function shutting down the regulator before overheating occurs. This limit can be adjusted by changing the ramp voltage VR. However, users should not set the per−phase limit lower than the average per−phase current (ILIM/n). There is also a per−phase initial duty−cycle limit at maximum input voltage: Setting the Switching Frequency for RPM Mode Operation of Phase 1 R RPM + I LIM where: RLIM is the current limit resistor. RLIM is connected from the ILIM pin to CSCOMP. RO is the output load line resistance. ILIM is the current limit set point. This is the peak inductor current that will trip current limit. In this example, if choosing 55 A for ILIM, RLIM is 5.775 kW, which is close to a standard 1% resistance of 5.76 kW. The per−phase current limit described earlier has its limit determined by the following: V VID (1 * 0.061) 462 kW To select the current limit set−point, we need to find the resistor value for RLIM. The current limit threshold for the ADP3210 is set when the current in RLIM is equal to the internal reference current of 20 mA. The current in RLIM is equal to the inductor current times RO. RLIM can be found using the following equation: 1.150 R MON + 300 kHz * 500 W + 202 kW (eq. 25) http://onsemi.com 26 1.15 V 10 RO R LIM I FS (eq. 29) ADP3210 where: RMON is the current monitor resistor. RMON is connected from IMON pin to FBRTN. RLIM is the current limit resistor. RO is the output load line resistance. IFS is the output current when the voltage on IMON is at full scale. The compensation values can be solved using the following: CA + RA + Feedback Loop Compensation Design CB + Optimized compensation of the ADP3210 allows the best possible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate. This ensures the optimal positioning and minimizes the output decoupling. With the multi−mode feedback structure of the ADP3210, users need to set the feedback compensation to make the converter output impedance work in parallel with the output decoupling. Several poles and zeros are created by the output inductor and decoupling capacitors (output filter) that need to be compensated for. A type−three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equation 30 to Equation 36 is intended to yield an optimal starting point for the design; some adjustments can be necessary to account for PCB and component parasitic effects (see the Turning Procedure for ADP3210). The first step is to compute the time constants for all of the poles and zeros in the system. RE + n RO ) AD ) TA + CX 2 R DS ) L n CX LX R O * RȀ RX TC + TD + L* V VID CX CX CX A V VID R D 2 f RE CZ I CRMS + D TB RB (eq. 37) TD RA (eq. 38) 1 *1 n D 44 A Ǹ 1 * 1 + 10.3 A 0.164 2 (eq. 39) RC Snubber It is important in any buck topology to use a resistor−capacitor snubber across the low side power MOSFET. The RC snubber dampens ringing on the switch node when the high side MOSFET turns on. The switch node ringing could cause EMI system failures and increased stress on the power components and controller. The RC snubber should be placed as close as possible to the low side MOSFET. Typical values for the resistor range from 1 W to 10 W. Typical values for the capacitor range from 330 pF to 4.7 nF. The exact value of the RC snubber depends on the PCB layout and MOSFET selection. Some fine tuning must be done to find the best values. The equation below is used to find the starting values for the RC subber. (eq. 30) (eq. 31) RO 2 RO (eq. 36) In a typical notebook system, the battery rail decouplings are MLCC capacitors or a mixture of MLCC capacitors and bulk capacitors. In this example, the input capacitor bank is formed by eight pieces of 10 mF, and 25 V MLCC capacitors with a ripple current rating of about 1.5 A each. (eq. 33) (R O * RȀ) ) C Z Ǹ IO I CRMS + 0.164 (eq. 32) Ǔ CA In continuous inductor−current mode, the source current of the high−side MOSFET is approximately a square wave with a duty ratio equal to n × VOUT/VIN and an amplitude of 1−nth the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current happens at the lowest input voltage, and is given by: DS SW (eq. 35) TC CIN Selection and Input Current DI/DT Reduction V RT RO T B + (R X ) RȀ * R O) ǒ RO RB The standard values for these components are subject to the tuning procedure, as introduced in the CIN Selection and Input Current DI/DT Reduction section. V RT D) TA RO RE C FB + V ID (1 * n (R O * RȀ) ) V RT RL n (eq. 34) where: R’ is the PCB resistance from the bulk capacitors to the ceramics. RDS is the total low−side MOSFET on−resistance per phase. For this example, AD is 5, VRT = 1. 5 V, R’ is approximately 0.4 mW (assuming an 8−layer motherboard) and LX is 250 pH for the four Panasonic SP capacitors. R Snubber + C Snubber + 1 2 p 27 C OSS (eq. 40) 1 p f Ringing P Snubber + C Snubber http://onsemi.com f Ringing R Snubber V Input 2 f Swithing (eq. 41) (eq. 42) ADP3210 Where RSnubber is the snubber resistor. CSnubber is the snubber capacitor. fRininging is the frequency of the ringing on the switch node when the high side MOSFET turns on. COSS is the low side MOSFET output capacitance at VInput. This is taken from the low side MOSFET data sheet. VInput is the input voltage. fSwitching is the switching frequency. PSnubber is the power dissipated in RSnubber. 31 R + R R C TH TT R TTSET1 + 1 2 * V V V V FD REF C TT R TH1 R TH2 RTH3 V NL * V FLCOLD V NL * V FLHOT (eq. 44) 5. Repeat Step 4 until cold and hot voltage measurements remain the same. 6. Measure output voltage from no load to full load using 5 A steps. Compute the load line slope for each change and then average it to get the overall load line slope (ROMEAS). 7. If ROMEAS is off from RO by more than 0.05 mW, use the following to adjust the RPH values: FD REF R R CS2(NEW) + R CS2(OLD) Multiple−point hot spot thermal monitoring can be implemented as shown in Figure 27. If any of the monitored hot spots reaches alarm temperature, the VRTT signal is asserted. The following calculation sets the alarm temperature: ) 30 3. Measure the output voltage at no load (VNL). Verify that it is within tolerance. 4. Measure the output voltage at full load and at cold (VFLCOLD). Let the board set for a ~10 minutes at full load and measure the output (VFLHOT). If there is a change of more than a few millivolts, then adjust RCS1 and RCS2 using Equation 44 and Equation 45. TTSET1 Figure 26. Single−Point Thermal Monitoring 2 TTSET3 DC Loadline Setting + 1 R 1. Build the circuit based on compensation values computed from Equation 1 to Equation 43. 2. Hook−up the dc load to the circuit. Turn the circuit on and verify operation. Check for jitter at no load and full load. 30 R TTSET2 Tuning Procedure for ADP3210 5.0 V R TTSN − R The number of hot spots monitored is not limited. The alarm temperature of each hot spot can be set differently by playing different RTTSET1, RTTSET2, RTTSETn. 31 VRTT TTSET1 Figure 27. Multiple−Point Thermal Monitoring For single−point hot spot thermal monitoring, simply set RTTSET1 equal to the NTC thermistor’s resistance at the alarm temperature (see Figure 26). For example, if the VRTT alarm temperature is 100°C using a Vishey thermistor (NTHS−0603N011003J) with a resistance of 100 kW at 25°C, and 6.8 kW at 100°C, simply set RTTSET1 = RTH1(100°C) to 6.8 kW. VCC R TTSN − VRTT Selecting Thermal Monitor Components ADP3210 5.0 V VCC ADP3210 R TH1ALARMTEMPERATURE (eq. 43) where VFD is the forward drop voltage of the parallel diode. Because the forward current is very small, the forward drop voltage is very low (100 mV). Assuming the same 100°C alarm temperature used in the single−spot thermal monitoring example, and the same Vishay thermistor, then Equation 43 leads to RTTSET = 7.37 kW, whose closest standard resistor is 7.32 kW (1%). R PH(NEW) + R PH(OLD) R OMEAS RO (eq. 45) 8. Repeat Step 6 and Step 7 to check load line and repeat adjustments if necessary. 9. Once complete with dc load line adjustment, do not change RPH, RCS1, RCS2, or RTH for the rest of procedure. 10. Measure output ripple at no load and full load with a scope to make sure it is within specification. http://onsemi.com 28 ADP3210 turn−on are set for a slew rate of ~150 A/ms to 250 A/ms (for example, a load step of 50 A should take 200 ns to 300 ns) with no overshoot. Some dynamic loads have an excessive turn−on overshoot if a minimum current is not set properly (this is an issue if you are using a VTT tool). AC Loadline Setting VACDRP Initial Transient Setting VDCDRP 19. With dynamic load still set at the maximum step size, expand the scope time scale to see 2 ms/div to 5 ms/div. A waveform that has two overshoots and one minor undershoot can result (see Figure 29). Here, VDROOP is the final desired value. Figure 28. AC Load Line Waveform 11. Remove the dc load from the circuit and hook up the dynamic load. 12. Hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 ms/div. 13. Set the dynamic load for a transient step of about 40 A at 1 kHz with a 50% duty cycle. 14. Measure the output waveform (using the dc offset on scope to see the waveform, if necessary). Try to use the vertical scale of 100 mV/div or finer. 15. Users should see a waveform that similar to the one in Figure 29. Use the horizontal cursors to measure VACDRP and VDCDRP as shown. Do not measure the undershoot or overshoot that occurs immediately after the step. 16. If the VACDRP and VDCDRP are different by more than a couple of mV, use the following to adjust CCS (note that users may need to parallel different values to get the right one due to the limited standard capacitor values available. It is also wise to have locations for two capacitors in the layout for this): C CS(NEW) + C CS(OLD) VDROOP VTRAN1 Figure 29. Transient Setting Waveform, Load Step • • V ACDRP V DCDRP VTRAN2 • (eq. 46) 17. Repeat Steps15 and Step 16. Repeat adjustments if necessary. Once complete, do not change CCS for the rest of the procedure. 18. Set dynamic load step to maximum step size. Do not use a step size larger than needed. Verify that the output waveform is square, which means VACDRP and VDCDRP are equal. Note: Make sure that the load step slew rate and 20. If both overshoots are larger than desired, make the following adjustments in the order they appear. Note that if these adjustments do not change the response, then users are limited by the output decoupling. In addition, check the output response each time a change is made, as well as the switching nodes to make sure they are still stable. Make ramp resistor larger by 25% (RRAMP). For VTRAN1, increase CB or increase switching frequency. For VTRAN2, increase RA and decrease CA both by 25%. 21. For load release (see Figure 30), if VTRANREL is larger than the IMVP−6 specification, there is not enough output capacitance. Either more capacitance is needed or the inductor values needed to be smaller. If the inductors are changed, then start the design over using Equation 1 to Equation 43 and this tuning guide. http://onsemi.com 29 ADP3210 example, a microprocessor core). If the load is distributed, then the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic. VTRANREL Power Circuitry VDROOP Avoid crossing any signal lines over the switching power path loop. This path should be routed on the PCB to encompass the shortest possible length in order to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise−related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. Whenever a power−dissipating component (for example, a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: improved current rating through the vias, and improved thermal performance from vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, the largest possible pad area should be used. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, use a solid power ground plane as one of the inner layers extending fully under all the power components. It is important for conversion efficiency that MOSFET drivers, such as ADP3419, are placed as close to the MOSFETs as possible. Thick and short traces are required between the driver and MOSFET gate, especially for the SR MOSFETs. Ground the MOSFET driver’s GND pin through immediately close vias. Figure 30. Transient Setting Waveform, Load Release Layout and Component Placement The following guidelines are recommended for optimal performance of a switching regulator in a PC system. General Recommendations For effective results, at least a four−layer PCB is recommended. This allows the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the rest of the power delivery current paths. Note that each square unit of 1 ounce copper trace has a resistance of ~0.53 mW at room temperature. When high currents need to be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths are minimized, and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3210) must cross through power circuitry, then a signal ground plane should be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3210 for referencing the components associated with the controller. Tie this plane to the nearest output decoupling capacitor ground. It should not be tied to any other power circuitry to prevent power currents from flowing in it. The best location for the ADP3210 is close to the CPU corner where all the related signal pins are located: VID0 to VID6, PSI, VCCSENSE, and VSSSENSE. The components around the ADP3210 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB and CSSUM pins (refer to Figure 24 for more details on layout for the CSSUM node.) The MLCC for the VCC decoupling should be placed as close to the VCC pin as possible. In addition, the noise filtering cap on the TTSENSE pin should also be as close to that pin as possible. The output capacitors should be connected as closely as possible to the load (or connector) that receives the power (for Signal Circuitry The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connects to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, route the FB and FBRTN traces adjacent to each other atop the power ground plane back to the controller. To filter any noise from the FBRTN trace, using a 1000 pF MLCC is suggested. It should be placed between the FBRTN pin and local ground and as close to the FBRTN pin as possible. http://onsemi.com 30 ADP3210 Connect the feedback traces from the switch nodes as close as possible to the inductor. The CSREF signal should be Kelvin connected to the center point of the copper bar, which is the VCORE common node for the inductors of all phases. In the back side of the ADP3210 package, a metal pad can be used as the device heat sink. In addition, running vias under the ADP3210 is not recommended because the metal pad can cause shorting between vias. ORDERING INFORMATION Device Number ADP3210MNR2G Temperature Range Package Shipping† −10°C to 100°C 340−Lead QFN 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *The “G’’ suffix indicates Pb−Free package. All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. http://onsemi.com 31 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN40 6x6, 0.5P CASE 488AR−01 ISSUE A DATE 18 APR 2007 1 40 SCALE 2:1 PIN ONE LOCATION 2X ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ 0.15 C 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30mm FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B D E DIM A A1 A3 b D D2 E E2 e L K TOP VIEW 0.15 C (A3) 0.10 C A 40X 0.08 C SIDE VIEW A1 C D2 L 40X 11 SEATING PLANE GENERIC MARKING DIAGRAM* K 20 40X XXXXXXXX AWLYYWWG 21 10 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 4.00 4.20 6.00 BSC 4.00 4.20 0.50 BSC 0.30 0.50 0.20 −−− EXPOSED PAD E2 b 0.10 C A B 40X 30 1 0.05 C XXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package 40 31 e 36X BOTTOM VIEW SOLDERING FOOTPRINT* *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 6.30 4.20 40X 0.65 1 4.20 6.30 40X 36X 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON21406D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. QFN40, 6 x 6 x 0.85, 0.5 MM PITCH PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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