CS8182
Linear Voltage Tracking
Regulator - Micropower
Low Dropout, Line Driver
200 mA
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8
•
200 mA Source Capability
Output Tracks within ±10 mV Worst Case
Low Dropout (0.35 V Typ. @ 200 mA)
Low Quiescent Current
Thermal Shutdown
Short Circuit Protection
Wide Operating Range
Internally Fused Leads in SO−8 Package
For Automotive and Other Applications Requiring Site and Change
Control
These are Pb−Free Devices
VIN
1
5
D2PAK−5
DPS SUFFIX
CASE 936AC
SO−8
DF SUFFIX
CASE 751
5
DPAK−5
DT SUFFIX
CASE 175AA
PIN CONNECTIONS AND
MARKING DIAGRAMS
1
VOUT
GND
GND
Adj
Features
•
•
•
•
•
•
•
•
•
1
1
CS
8182
AWLYWWG
1
A
WL, L
Y
WW, W
G or G
8
8182
ALYW
G
The CS8182 is a monolithic integrated low dropout tracking
regulator designed to provides an adjustable buffered output voltage
that closely tracks (±10 mV) the reference input. The output delivers
up to 200 mA while being able to be configured higher, lower or equal
to the reference voltages.
The device has been designed to operate over a wide range (2.8 V to
45 V) while still maintaining excellent DC characteristics. The
CS8182 is protected from reverse battery, short circuit and thermal
runaway conditions. The device also can withstand 45 V load dump
transients and −50 V reverse polarity input voltage transients. This
makes it suitable for use in automotive environments.
The VREF/ENABLE lead serves two purposes. It is used to provide
the input voltage as a reference for the output and it also can be pulled
low to place the device in sleep mode where it nominally draws 30 mA
from the supply.
Tab GND
Pin 1. VIN
2. VOUT
3. GND
4. Adj
5. VREF
VIN
GND
GND
VREF/ENABLE
8182G
ALYWW
1
5
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
VOUT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Current Limit &
SAT Sense
Adj
−
ENABLE
+
VREF/ENABLE
+
GND
Thermal
Shutdown
−
2.0 V
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2016
October, 2019 − Rev. 28
1
Publication Order Number:
CS8182/D
CS8182
PACKAGE PIN DESCRIPTION
Package Lead Number
SO−8
D2PAK 5−PIN
DPAK 5−PIN
Lead Symbol
8
1
1
VIN
1
2
2
VOUT
Regulated Output
2, 3, 6, 7
3
3
GND
Ground
4
4
4
Adj
5
5
5
VREF/ENABLE
Function
Input Voltage
Adjust Lead
Reference Voltage and ENABLE Input
MAXIMUM RATINGS
Rating
Value
Unit
−65 to +150
°C
+150
°C
−16 to 45
V
45
V
−10 to +VIN
V
Package Thermal Resistance, SO−8:
Junction−to−Case, RqJC
Junction−to−Air, RqJA
25
80
°C/W
°C/W
Package Thermal Resistance, D2PAK
Junction−to−Case, RqJC
Junction−to−Air, RqJA
4.0
48
°C/W
°C/W
Package Thermal Resistance, DPAK
Junction−to−Case, RqJC
Junction−to−Air, RqJA
8.0
64
°C/W
°C/W
ESD Capability (Human Body Model)
(Machine Model)
2.0
200
kV
V
240
225
260
°C
Storage Temperature Range
Junction Temperature
Supply Voltage Range (Continuous)
Peak Transient Voltage (VIN = 14 V, Load Dump Transient = 31 V)
Voltage Range (Adj, VOUT, VREF/ENABLE)
Lead Temperature Soldering: (Note 1)
(SO−8)
(D2PAK)
(DPAK)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. 60 second maximum above 183°C.
RECOMMENDED OPERATING RANGES
Rating
Junction Temperature, TJ
Input Voltage, Continuous VIN
Value
Unit
−40 to+125
°C
3.4 to 45
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
CS8182
ELECTRICAL CHARACTERISTICS (VIN = 14 V; VREF/ENABLE > 2.75 V; −40°C < TJ < +125°C; COUT ≥ 10 mF;
0.1 W < COUT−ESR < 1.0 W @ 10 kHz, unless otherwise specified.)
Test Conditions
Parameter
Min
Typ
Max
Unit
−10
−5.0
−
−
10
5
mV
mV
Regular Output
VREF − VOUT
VOUT Tracking Error
4.5 V ≤ VIN ≤ 26 V, 100 mA ≤ IOUT ≤ 200 mA, Note 2
VIN = 12 V, IOUT = 30 mA, VREF = 5.0 V, Note 2
Dropout Voltage (VIN − VOUT)
IOUT = 100 mA
IOUT = 30 mA
IOUT = 200 mA
−
−
−
100
−
350
150
500
600
mV
mV
mV
Line Regulation
4.5 V ≤ VIN ≤ 26 V, Note 2
−
−
10
mV
Load Regulation
100 mA ≤ IOUT ≤ 200 mA, Note 2
−
−
10
mV
Adj Lead Current
Loop in Regulation
−
0.2
1.0
mA
Current Limit
VIN = 14 V, VREF = 5.0 V, VOUT = 90% of VREF, Note 2
250
−
700
mA
Quiescent Current (IIN − IOUT)
VIN = 12 V, IOUT = 200 mA
VIN = 12 V, IOUT = 100 mA
VIN = 12 V, VREF/ENABLE = 0 V
−
−
−
15
75
30
25
150
55
mA
mA
mA
Reverse Current
VOUT = 5.0 V, VIN = 0 V
−
0.2
1.5
mA
Ripple Rejection
f = 120 Hz, IOUT = 200 mA, 4.5 V ≤ VIN ≤ 26 V
60
−
−
dB
Thermal Shutdown
GBD
150
180
210
°C
0.80
2.00
2.75
V
−
0.2
1.0
mA
VREF/ENABLE
−
Enable Voltage
Input Bias Current
VREF/ENABLE
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. VOUT connected to Adj lead.
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3
CS8182
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT (mA)
18
16
14
12
10
8
6
4
2
0
0
20
40
60
80
100
120 140 160 180 200
OUTPUT CURRENT (mA)
1
100
0.9
90
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
Figure 2. Quiescent Current vs. Output Current
0.8
0.7
0.6
0.5
0.4
I (VOUT) = 20 mA
0.3
0.2
0.1
0
5
10
15
20
70
60
50
40
30
20
VREF/ ENABLE = 0 V
10
I (VOUT) = 1 mA
0
80
25
30
35
40
0
45
0
5
VIN, INPUT VOLTAGE (V)
14
12
10
8
VIN = 6 V*
VREF = 5 V**
6
4
2
0
VIN = 0 V
0
5
10
15
25
30
35
40
45
140
CURRENT INTO VOUT (mA)
CURRENT INTO VOUT (mA)
16
20
Figure 4. Quiescent Current vs. Input Voltage
(Sleep Mode)
* Graph is duplicate for VIN > 1.6 V.
**Dip (@5 V) shifts with VREF voltage.
18
15
VIN, INPUT VOLTAGE (V)
Figure 3. Quiescent Current vs. Input Voltage
(Operating Mode)
20
10
20
100
VIN = 0 V
80
60
VIN = 6 V*
VREF = 5 V**
40
20
0
25
* Graph is duplicate for VIN > 1.6 V.
**Dip (@5 V) shifts with VREF voltage.
120
0
FORCED VOUT VOLTAGE (V)
5
10
15
20
25
30
FORCED VOUT VOLTAGE (V)
Figure 5. VOUT Reverse Current
Figure 6. VOUT Reverse Current
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4
35
40
CS8182
CIRCUIT DESCRIPTION
ENABLE Function
Output Voltage
By pulling the VREF/ENABLE lead below 2.0 V typically,
(see Figure 10 or Figure 11), the IC is disabled and enters a
sleep state where the device draws less than 55 mA from
supply. When the VREF/ENABLE lead is greater than 2.75 V,
VOUT tracks the VREF/ENABLE lead normally.
The output is capable of supplying 200 mA to the load
while configured as a similar (Figure 7), lower (Figure 9), or
higher (Figure 8) voltage as the reference lead. The Adj lead
acts as the inverting terminal of the op amp and the VREF
lead as the non−inverting.
The device can also be configured as a high−side driver as
displayed in Figure 12.
GND
GND
VREF/
ENABLE
Adj
RA
GND
GND
Adj
CS8182
VOUT, 200 mA
B+
VIN
VREF/
ENABLE
GND
VREF
C3***
10 nF
Figure 8. Tracking Regulator at Higher Voltages
Figure 7. Tracking Regulator at the Same Voltage
GND
GND
R
VOUT + VREF(1 ) E)
RA
VOUT + VREF
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 mF
C1*
1.0 mF
VREF/
ENABLE
Adj
5.0 V
C3***
10 nF
B+
VIN
CS8182
C1*
1.0 mF
C2**
10 mF
C1*
1.0 mF
VOUT
GND
GND
R1
C3***
10 nF
R2
C1*
1.0 mF
GND
GND
VREF/
ENABLE
Adj
VREF
B+
VIN
CS8182
GND
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 mF
RF
GND
B+
VIN
CS8182
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 mF
from MCU
R
C3***
10 nF
VREF
VOUT + VREF( R2 )
R1 ) R2
Figure 9. Tracking Regulator at Lower Voltages
NCV8501
VREF (5.0 V)
200 mA
100 nF
5.0 V
To Load 10 mF
(e.g. sensor)
GND
GND
Adj
VIN
CS8182
VOUT
GND
GND
C1*
1.0 mF
mC
GND
Adj
GND
VREF/
ENABLE
VOUT
I/O
C3***
10 nF
B+
VIN
CS8182
VIN
6.0 V−40 V
Figure 10. Tracking Regulator with ENABLE Circuit
GND
GND
VREF/
ENABLE
C3***
10 nF
VOUT + B ) * VSAT
Figure 11. Alternative ENABLE Circuit
Figure 12. High−Side Driver
* C1 is required if the regulator is far from the power source filter.
** C2 is required for stability.
*** C3 is recommended for EMC susceptibility.
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5
MCU
CS8182
APPLICATION NOTES
VOUT Short to Battery
Figure 14. In this case the CS8182 supply input voltage is set
at 7 V when a short to battery (14 V typical) occurs on VOUT
which normally runs at 5 V. The current into the device
(ammeter in Figure 14) will draw additional current as
displayed in Figure 15.
The CS8182 will survive a short to battery when hooked
up the conventional way as shown in Figure 13. No damage
to the part will occur. The part also endures a short to battery
when powered by an isolated supply at a lower voltage as in
Short to battery
C2**
10 mF
B+
VOUT
VIN
GND
GND
CS8182
VOUT 70 mA
Loads
GND
C1*
1.0 mF
GND
VREF/
ENABLE
Adj
+ Automotive Battery
− typically 14 V
5.0 V
+
5.0 V
−
C3***
10 nF
VOUT = VREF
Figure 13.
Short to battery
A
Loads
VOUT
B+
70 mA
C2**
10 mF
VOUT
VIN
GND
GND
GND
CS8182
Automotive Battery
typically 14 V
Adj
* C1 is required if the regulator is far from the power source filter.
** C2 is required for stability.
*** C3 is recommended for EMC susceptibility.
C1*
7V
1.0 mF
+
−
GND
VREF/
ENABLE
VOUT = VREF
C3***
10 nF
5.0 V
+
5.0 V
−
Figure 14.
2.0
Switched Application
1.8
The CS8182 has been designed for use in systems where
the reference voltage on the VREF/ENABLE pin is
continuously on. Typically, the current into the
VREF/ENABLE pin will be less than 1.0 mA when the
voltage on the VIN pin (usually the ignition line) has been
switched out (VIN can be at high impedance or at ground.)
Reference Figure 16.
1.4
1.2
1.0
0.8
Ignition
Switch
0.6
0.4
VOUT
0.2
C2
10 mF
0
5 6 7 8 9 10 1112 1314 15 1617 1819 20 2122 2324 25 26
VOUT VOLTAGE (V)
VOUT
VIN
GND
GND
GND
Figure 15. VOUT Short to Battery
Adj
CS8182
CURRENT (mA)
1.6
6
VBAT
GND
VREF/
ENABLE
Figure 16.
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C1
1.0 mF
< 1.0 mA
VREF
5.0 V
CS8182
External Capacitors
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
The output capacitor for the CS8182 is required for
stability. Without it, the regulator output will oscillate.
Actual size and type may vary depending upon the
application load and temperature range. Capacitor effective
series resistance (ESR) is also a factor in the IC stability.
Worst−case is determined at the minimum ambient
temperature and maximum load expected.
The output capacitor can be increased in size to any
desired value above the minimum. One possible purpose of
this would be to maintain the output voltage during brief
conditions of negative input transients that might be
characteristic of a particular system.
The capacitor must also be rated at all ambient
temperatures expected in the system. To maintain regulator
stability down to −40°C, a capacitor rated at that temperature
must be used.
RqJA + 150° C * TA
PD
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external heat
sink will be required.
IIN
VIN
SMART
REGULATOR®
IOUT
VOUT
Control
Features
Ceramic Capacitor Stability
The CS8182 has been verified to work with ceramic
output capacitors with an additional series resistor
simulating traditional ESR of tantalum capacitors; however,
it has been determined the best operational performance is
with a 330 mW series resistor (or parallel combination of
three 1 W resistors) in conjunction with a 22 mF output
capacitor. Values outside of this are known to have limited
performance with respect to stability. For more
information, please contact your local ON Semiconductor
sales office.
IQ
Figure 17. Single Output Regulator with Key
Performance Parameters Labeled
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
Calculating Power Dissipation in a Single Output
Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 17) is:
PD(max) + {VIN(max) * VOUT(min)} IOUT(max)
) VIN(max)IQ
(2)
RqJA + RqJC ) RqCS ) RqSA
(1)
(3)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heatsink thermal resistance, and
RqSA = the heatsink−to−ambient thermal resistance.
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current, for the
application,and
IQ is the quiescent current the regulator consumes at
IOUT(max).
RqJC appears in the package section of the data sheet. Like
RqJA, it is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heatsink manufacturers.
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7
CS8182
180
180
160
160
140
140
120
qJA (°C/W)
100
2 oz
80
60
100
20
20
100
200
300
400
500
600
700
0
800
0
100
200
400
500
600
700
800
COPPER AREA (mm2)
Figure 18. 8 Lead SOIC (Fused) Thermal
Resistance
Figure 19. 5 Lead DPAK Thermal Resistance
180
160
160
140
140
120
120
100
80
1 oz
60
2 oz
40
8 Lead SOIC w/ 4 Thermal Leads 1 oz
8 Lead SOIC w/ 4 Thermal Leads 2 oz
5 Lead DPAK 1 oz
5 Lead DPAK 2 oz
100
80
60
5 Lead D2PAK 1 oz
40
20
5 Lead D2PAK 2 oz
20
0
300
COPPER AREA (mm2)
180
0
2 oz
60
40
0
1 oz
80
40
0
qJA (°C/W)
1 oz
qJA (°C/W)
qJA (°C/W)
120
100
200
300
400
500
600
700
0
800
0
100
200
300
400
500
600
700
COPPER AREA (mm2)
COPPER AREA (mm2)
Figure 20. 5 Lead D2PAK Thermal Resistance
Figure 21. Thermal Resistance Summary
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8
800
CS8182
ORDERING INFORMATION
Package
Shipping†
CS8182YDF8G
SO−8
(Pb−Free)
95 Units / Rail
CS8182YDFR8G
SO−8
(Pb−Free)
2500 / Tape & Reel
CS8182YDPS5G
D2PAK 5−PIN
(Pb−Free)
50 Units / Rail
CS8182YDPSR5G
D2PAK 5−PIN
(Pb−Free)
750 / Tape & Reel
CS8182DTG
DPAK 5L
(Pb−Free)
50 Units / Rail
CS8182DTRKG
DPAK 5L
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK−5, CENTER LEAD CROP
CASE 175AA
ISSUE B
DATE 15 MAY 2014
SCALE 1:1
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
R1
Z
A
S
12 3 4 5
U
K
F
J
L
H
D
G
5 PL
0.13 (0.005)
M
T
2.2
0.086
0.34 5.36
0.013 0.217
5.8
0.228
10.6
0.417
0.8
0.031
SCALE 4:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12855D
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
0.170 0.190
0.185 0.210
0.025 0.040
0.020
−−−
0.035 0.050
0.155 0.170
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.51
0.71
0.46
0.58
0.61
0.81
4.56 BSC
0.87
1.01
0.46
0.58
2.60
2.89
1.14 BSC
4.32
4.83
4.70
5.33
0.63
1.01
0.51
−−−
0.89
1.27
3.93
4.32
GENERIC
MARKING DIAGRAMS*
RECOMMENDED
SOLDERING FOOTPRINT*
6.4
0.252
DIM
A
B
C
D
E
F
G
H
J
K
L
R
R1
S
U
V
Z
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DPAK−5 CENTER LEAD CROP
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK−5
CASE 936AC−01
ISSUE A
DATE 10 SEP 2009
A
SCALE 1:1
E
L1
B
A
SEATING
PLANE
0.10
A
E/2
M
B A
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH AND GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED
0.005 MAXIMUM PER SIDE. THESE DIMENSIONS
TO BE MEASURED AT DATUM H.
4. THERMAL PAD CONTOUR OPTIONAL WITHIN
DIMENSIONS E, L1, D1, AND E1. DIMENSIONS
D1 AND E1 ESTABLISH A MINIMUM MOUNTING
SURFACE FOR THE THERMAL PAD.
D1
c2
E1
D
DETAIL C
H
5X
c
e
b
VIEW A−A
A
0.13
M
B A
M
B
H
SEATING
PLANE
A1
L3
L
RECOMMENDED
SOLDERING FOOTPRINT*
M
0.424
GAUGE
PLANE
DIM
A
A1
b
c
c2
D
D1
E
E1
e
H
L
L1
L3
M
INCHES
MIN
MAX
0.170
0.180
0.000
0.010
0.026
0.036
0.017
0.026
0.045
0.055
0.325
0.368
0.250
−−−
0.380
0.420
0.200
−−−
0.067 BSC
0.580
0.620
0.090
0.110
−−−
0.066
0.010 BSC
0_
8_
MILLIMETERS
MIN
MAX
4.32
4.57
0.00
0.25
0.66
0.91
0.43
0.66
1.14
1.40
8.25
9.53
6.35
−−−
9.65
10.67
5.08
−−−
1.70 BSC
14.73
15.75
2.29
2.79
−−−
1.68
0.25 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
DETAIL C
XX
XXXXXXXXX
AWLYWWG
0.310
0.584
1
XXXXX
A
WL
Y
WW
G
0.176
5X
0.067
PITCH
0.040
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14120D
D2PAK−5
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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