FS7145-01-XTP

FS714x Programmable Phase-Locked Loop Clock Generator 1.0 Key Features • • • • • • • • Extremely flexible and low-jitter phase locked loop (PLL) frequency synthesis No external loop filter components needed 150MHz CMOS or 340MHz PECL outputs Completely configurable via I2C™-bus Up to four FS714x can be used on a single I2C-bus 3.3V operation Independent on-chip crystal oscillator and external reference input Very low “cumulative” jitter 2.0 Description The FS714x (FS7140x or FS7145x) is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component 2 count in a variety of electronic systems. Via the I C-bus interface, the FS714x can be adapted to many clock generation requirements. The length of the reference and feedback dividers, their fine granularity and the flexibility of the post divider make the FS714x the most flexible stand-alone PLL clock generator available. Figure 1: Pin Configuration: 16-pin (0.150") SOIC, 16-pin (5.3mm) SSOP 3.0 Applications • • • • Precision frequency synthesis Low-frequency clock multiplication Video line-locked clock generation Laser beam printers (FS7145) ©2008 SCILLC. All rights reserved. May 2008 – Rev. 5 Publication Order Number: FS714x/D FS714x Figure 2: Device Block Diagram Table 1: FS7140 Pin Descriptions Pin Type Name Description 1 DI SCL Serial interface clock (requires an external pull-up) 2 DIO SDA Serial interface data input/output (requires an external pull-up) 3 DID ADDR0 Address select bit “0” 4 P VSS Ground 5 AI XIN Crystal oscillator feedback 6 AO XOUT Crystal oscillator drive 7 DID ADDR1 Address select bit “1” 8 P VDD Power supply (+3.3V nominal) 9 AI IPRG PECL current drive programming 10 n/c No connection 11 P VSS Ground U 12 DI REF Reference frequency input 13 n/c No connection 14 P VDD Power supply (+3.3V nominal) 15 DO CLKP Clock output 16 DO CLKN Inverted clock output Key: AI: Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-up; DID = Input with Internal Pull-down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input; DO = Digital Output; P = Power/Ground; # = Active Low Pin Rev. 5 | Page 2 of 19 | www.onsemi.com FS714x Table 2: FS7145 Pin Descriptions Pin Type Name Description 1 DI SCL Serial interface clock (requires an external pull-up) 2 DIO SDA Serial interface data input/output (requires an external pull-up) 3 DID ADDR0 Address select bit “0” 4 P VSS Ground 5 AI XIN Crystal oscillator feedback 6 AO XOUT Crystal oscillator drive 7 DID ADDR1 Address select bit “1” 8 P VDD Power supply (+3.3V nominal) 9 AI IPRG PECL current drive programming 10 n/c No connection 11 P VSS Ground U 12 DI REF Reference frequency input U 13 DI SYNC Synchronization input 14 P VDD Power supply (+3.3V nominal) 15 DO CLKP Clock output 16 DO CLKN Inverted clock output Key: AI: Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-up; DID = Input with Internal Pull-down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input; DO = Digital Output; P = Power/Ground; # = Active Low Pin 4.0 Functional Block Diagram 4.1 Phase Locked Loop (PLL) The PLL is a standard phase- and frequency-locked loop architecture. The PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider. The reference frequency (generated by either the on-board crystal oscillator or an external frequency source), is first reduced by the reference divider. The integer value that the frequency is divided by is called the modulus and is denoted as NR for the reference divider. This divided reference is then fed into the PFD. The VCO frequency is fed back to the PFD through the feedback divider (the modulus is denoted by NF). The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is then: This basic PLL equation can be rewritten as A post divider (actually a series combination of three post dividers) follows the PLL and the final equation for device output frequency is: Rev. 5 | Page 3 of 19 | www.onsemi.com FS714x 4.1.1. Reference Divider The reference divider is designed for low phase jitter. The divider accepts the output of either the crystal oscillator circuit or an external reference frequency. The reference divider is a 12 bit divider, and can be programmed for any modulus from 1 to 4095 (divide by 1 not available on date codes prior to 0108). 4.1.2. Feedback Divider The feedback divider is based on a dual-modulus divider (also called dual-modulus prescaler) technique. It permits division by any integer value between 12 and 16383. Simply program the FBKDIV register with the binary equivalent of the desired modulus. Selected moduli below 12 are also permitted. Moduli of: 4, 5, 8, 9, and 10 are also allowed (4 and 5 are not available on date codes prior to 0108). 4.1.3. Post Divider The post divider consists of three individually programmable dividers, as shown in Figure 3. Figure 3: Post Divider The moduli of the individual dividers are denoted as NP1, NP2 and NP3, and together they make up the array modulus NPX. NPX = NP1 x NP2 x NP3 The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. Second, the extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. Note that a nominal 50/50 duty factor is always preserved (even for selections which have an odd modulus). See Table 8 for additional information. 4.1.4. Crystal Oscillator The FS7140 is equipped with a Pierce-type crystal oscillator. The crystal is operated in parallel resonant mode. Internal load capacitance is provided for the crystal. While a recommended load capacitance for the crystal is specified, crystals for other standard load capacitances may be used if great precision of the reference frequency (100ppm or less) is not required. 4.1.5. Reference Divider Source MUX The source of frequency for the reference divider can be chosen to be the device crystal oscillator or the REF pin by the REFDSRC bit. When not using the crystal oscillator, it is preferred to connect XIN to VSS. Do not connect to XOUT. Rev. 5 | Page 4 of 19 | www.onsemi.com FS714x When not using the REF input, it is preferred to leave it floating or connected to VDD. 4.1.6. Feedback Divider Source MUX The source of frequency for the feedback divider may be selected to be either the output of the post divider or the output of the VCO by the FBKDSRC bit. Ordinarily, for frequency synthesis, the output of the VCO is used. Use the output of the post divider only where a deterministic phase relationship between the output clock and reference clock are desired (line-locked mode, for example). 4.1.7. Device Shutdown Two bits are provided to effect shutdown of the device if desired, when it is not active. SHUT1 disables most externally observable device functions. SHUT2 reduces device quiescent current to absolute minimum values. Normally, both bits should be set or cleared together. Serial communications capability is not disabled by either SHUT1 or SHUT2. 4.2 Differential Output Stage The differential output stage supports both CMOS and pseudo-ECL (PECL) signals. The desired output interface is chosen via the programming registers. If a PECL interface is used, the transmission line is usually terminated using a Thévenin termination. The output stage can only sink current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. The ratio of output sink current to IPRG current is 13:1. Source current for the CLKx pins is provided by the pull-up resistors that are part of the Thévenin termination. 4.2.1. Example Assume that it is desired to connect a PECL-type fanout buffer right next to the FS7140. Further assume: • VDD = 3.3V • Desired VHI = 2.4V • Desired VLO = 1.6V • Equivalent RLOAD = 75 ohms Rev. 5 | Page 5 of 19 | www.onsemi.com FS714x Then: R1 (from CLKP and CLKN output to VDD) = RLOAD * VDD / VHI = 75 * 3.3 / 2.4 = 103 ohms R2 (from CLKP and CLKN output to GND) = RLOAD * VDD / (VDD - VHI) = 75 * 3.3 / (3.3 - 2.4) = 275 ohms Rprgm (from VDD to IPRG pin) = 26 * (VDD * RLOAD) / (VHI - VLO) / 3 = 26 * (3.3 * 75) / (2.4 - 1.6) / 3 = 2.68 Kohms 4.3 SYNC Circuitry The FS7145 supports nearly instantaneous adjustment of the output CLK phase by the SYNC input. Either edge direction of SYNC (positive-going or negative-going) is supported. Example (positive-going SYNC selected): Upon the negative edge of SYNC input, a sequence begins to stop the CLK output. Upon the positive edge, CLK resumes operation, synchronized to the phase of the SYNC input (plus a deterministic delay). This is performed by control of the device post-divider. Phase resolution equal to ½ of the VCO period can be achieved (approximately down to 2ns). 5.0 I2C-bus Control Interface This device is a read/write slave device meeting all Philips I2C-bus specifications except a "general call." The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. I2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS). 5.1 Bus Conditions Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START 2 or STOP condition. The following bus conditions are defined by the I C-bus protocol. 5.1.1. Not Busy Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy. 5.1.2. START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition. Rev. 5 | Page 6 of 19 | www.onsemi.com FS714x 5.1.3. STOP Data Transfer A low to high transition of the SDA line while SCL input is high indicates a STOP condition. All commands to the device must be followed by a STOP condition. 5.1.4. Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first eight bytes will overflow into the first register, then the second, and so on, in a first-in, firstoverwritten fashion. 5.1.5. Acknowledge When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition. 5.2 I2C-bus Operation All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The crystal oscillator does not have to run for communication to occur. The device accepts the following I2C-bus commands: 5.2.1. Slave Address After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the device is: A6 1 A5 0 A4 1 A3 1 A2 0 A1 X A0 X where X is controlled by the logic level at the ADDR pins. The selectable ADDR bits allow four different FS7140 devices to exist on the 2 same bus. Note that every device on an I C-bus must have a unique address to avoid possible bus conflicts. 5.2.2. Random Register Write Procedure Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored. Rev. 5 | Page 7 of 19 | www.onsemi.com FS714x 5.2.3. Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but does generate a STOP condition. 5.2.4. Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the random register write if several registers must be written. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to eight bytes of data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a sequential register write. 5.2.5. Sequential Register Read Procedure Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure is more efficient than the random register read if several registers must be read. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all eight bytes of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition. Rev. 5 | Page 8 of 19 | www.onsemi.com FS714x Figure 4: Random Register Write Procedure Figure 5: Random Register Read Procedure Figure 6: Sequential Register Write Procedure Rev. 5 | Page 9 of 19 | www.onsemi.com FS714x Figure 7: Sequential Register Read Procedure Rev. 5 | Page 10 of 19 | www.onsemi.com FS714x 6.0 Programming Information All register bits are cleared to zero on power-up. All register bits may be read back as written. Table 3: FS7140 Register Map Address BIT 7 BIT 6 Reserved Reserved Byte 7 (Bit 63) (Bit 62) Must be set to “0” Must be set to “0” BIT 5 Reserved (Bit 61) Must be set to “0” BIT 4 Reserved (Bit 60) Must be set to “0” BIT 3 Reserved (Bit 59) Must be set to “0” BIT 2 Reserved (Bit 58) Must be set to “0” BIT 1 Reserved (Bit 57) Must be set to “0” BIT 0 Reserved (Bit 56) Must be set to “0” Reserved Byte 6 (Bit 55) Must be set to “0” Reserved (Bit 54) Must be set to “0” SHUT2 (Bit 53) 0 = Normal 1 = Powered down Reserved (Bit 52) Must be set to “0” Reserved (Bit 51) Must be set to “0” Reserved (Bit 50) Must be set to “0” Reserved (Bit 49) Must be set to “0” Reserved (Bit 48) Must be set to “0” Reserved Byte 5 (Bit 47) Must be set to “0” LC (Bit 46) Loop filter cap select LR[1] LR[0] Reserved (Bit 43) Must be set to “0” Reserved (Bit 42) Must be set to “0” CP[1] CP[0] (Bit 45) (Bit 44) Loop filter resistor select (Bit 41) (Bit 40) Charge pump current select CMOS Byte 4 (Bit 39) 0 = PECL 1 = CMOS FBKDSRC (Bit 38) 0 = VCO output 1 = Post divider output FBKDIV[13] (Bit 37) 8192 FBKDIV[12] (Bit 36) 4096 FBKDIV[11] (Bit 35) 2048 FBKDIV[10] (Bit 34) 1024 FBKDIV[9] (Bit 33) 512 FBKDIV[8] (Bit 32) 256 See Section 4.1.2 for disallowed FBKDIV values FBKDIV[7] Byte 3 Byte 2 (Bit 31) 128 FBKDIV[6] (Bit 30) 64 FBKDIV[5] (Bit 29) 32 FBKDIV[4] FBKDIV[3] FBKDIV[2] (Bit 26) 4 FBKDIV[1] (Bit 25) 2 FBKDIV[0] (Bit 24) 1 (Bit 28) (Bit 27) 16 8 See Section 4.1.2 for disallowed FBKDIV values POST2[3] (Bit 23) POST2[2] POST3[0] POST2[1] SHUT1 (Bit 13) 0 = Normal 1 = Powered down POST2[0] (Bit 20) POST1[3] (Bit 19) POST1[2] REFDIV[10] (Bit 10) 1024 POST1[1] REFDIV[9] (Bit 9) 512 POST1[0] REFDIV[8] (Bit 8) 256 (Bit 22) (Bit 21) Modulus = N +1 (N = 0 to 11); See Table 8 (Bit 18) (Bit 17) (Bit 16) Modulus = N +1 (N = 0 to 11); See Table 8 POST3[1] Byte 1 REFDSRC (Bit 12) 0 = Crystal oscillator 1 = REF pin REFDIV[11] (Bit 11) 2048 (Bit 15) (Bit 14) Modulus = 1,2,4, or 8; See Table 8 Byte 0 REFDIV[7] (Bit 7) 128 REFDIV[6] (Bit 6) 64 REFDIV[5] (Bit 5) 32 REFDIV[4] (Bit 4) 16 REFDIV[3] (Bit 3) 8 REFDIV[2] (Bit 2) 4 REFDIV[1] (Bit 1) 2 REFDIV[0] (Bit 0) 1 Rev. 5 | Page 11 of 19 | www.onsemi.com FS714x Table 4: FS7145 Register Map Address BIT 7 BIT 6 Reserved Reserved Byte 7 (Bit 63) (Bit 62) Must be set to “0” Must be set to “0” BIT 5 Reserved (Bit 61) Must be set to “0” BIT 4 Reserved (Bit 60) Must be set to “0” BIT 3 Reserved (Bit 59) Must be set to “0” BIT 2 Reserved (Bit 58) Must be set to “0” BIT 1 Reserved (Bit 57) Must be set to “0” BIT 0 Reserved (Bit 56) Must be set to “0” Reserved Byte 6 (Bit 55) Must be set to “0” Reserved (Bit 54) Must be set to “0” SHUT2 (Bit 53) 0 = Normal 1 = Powered down Reserved (Bit 52) Must be set to “0” Reserved (Bit 51) Must be set to “0” Reserved (Bit 50) Must be set to “0” SYNCPOL (Bit 49) “0” = negative “1” = positive SYNCEN (Bit 48) “0” = negative “1” = positive Reserved Byte 5 (Bit 47) Must be set to “0” LC (Bit 46) Loop filter cap select LR[1] LR[0] Reserved (Bit 43) Must be set to “0” Reserved (Bit 42) Must be set to “0” CP[1] CP[0] (Bit 45) (Bit 44) Loop filter resistor select (Bit 41) (Bit 40) Charge pump current select CMOS Byte 4 (Bit 39) 0 = PECL 1 = CMOS FBKDSRC (Bit 38) 0 = VCO output 1 = Post divider output FBKDIV[13] (Bit 37) 8192 FBKDIV[12] (Bit 36) 4096 FBKDIV[11] (Bit 35) 2048 FBKDIV[10] (Bit 34) 1024 FBKDIV[9] (Bit 33) 512 FBKDIV[8] (Bit 32) 256 See Section 4.1.2 for disallowed FBKDIV values FBKDIV[7] Byte 3 Byte 2 (Bit 31) 128 FBKDIV[6] (Bit 30) 64 FBKDIV[5] (Bit 29) 32 FBKDIV[4] FBKDIV[3] FBKDIV[2] (Bit 26) 4 FBKDIV[1] (Bit 25) 2 FBKDIV[0] (Bit 24) 1 (Bit 28) (Bit 27) 16 8 See Section 4.1.2 for disallowed FBKDIV values POST2[3] POST3[1] POST2[2] POST3[0] POST2[1] SHUT1 (Bit 13) 0 = Normal 1 = Powered down POST2[0] (Bit 20) POST1[3] (Bit 19) POST1[2] REFDIV[10] (Bit 10) 1024 POST1[1] REFDIV[9] (Bit 9) 512 POST1[0] REFDIV[8] (Bit 8) 256 (Bit 23) (Bit 22) (Bit 21) Modulus = N +1 (N = 0 to 11); See Table 8 (Bit 15) (Bit 14) Modulus = 1,2,4, or 8; See Table 8 (Bit 18) (Bit 17) (Bit 16) Modulus = N +1 (N = 0 to 11); See Table 8 REFDSRC (Bit 12) 0 = Crystal oscillator 1 = REF pin REFDIV[11] (Bit 11) 2048 Byte 1 Byte 0 REFDIV[7] (Bit 7) 128 REFDIV[6] (Bit 6) 64 REFDIV[5] (Bit 5) 32 REFDIV[4] (Bit 4) 16 REFDIV[3] (Bit 3) 8 REFDIV[2] (Bit 2) 4 REFDIV[1] (Bit 1) 2 REFDIV[0] (Bit 0) 1 Table 5: Device Configuration Bits Name Description Reference divider source REFDSRC [0] = crystal oscillator / [1] = REF pin Feedback divider source FBKDSRC [0] = VCO output / [1] = post divider output Shutdown1 SHUT1 [0] = normal / [1] = powered down Shutdown2 SHUT2 [0] = normal / [1] = powered down CLKP/CLKN output mode CMOS [0] = PECL output / [1] CMOS output Table 6: Main Loop Tuning Bits Name Description Charge pump current [00] CP[1:0] [01] [10] [11] Loop filter resistor select [00] LR[1:0] [01] [10] [11] Loop filter capacitor select LC [0] [1] 2.0µA 4.5µA 11.0µA 22.5µA 400KΩ 133KΩ 30KΩ 12KΩ 185pF 500pF Table 7: PLL Divider Control Bits Name Description REFDIV[11:0] Reference divider (NR) FBKDIV[13:0] Feedback divider (NR) Rev. 5 | Page 12 of 19 | www.onsemi.com FS714x Table 8: SYNC Control Bits (FS7145 only) Name Description SYNCEN Sync enable [0] = disabled / [1] = enabled SYNCPOL Sync polarity [0] = negative edge / [1] = positive edge Table 9: Post Divider Control Bits Name Description Post divider #1 (NP1) modulus [0000] [0001] [0010] [0011] [0100] [0101] [0110] POST1[3:0] [0111] [1000] [1001] [1010] [1011] [1100] [1101] [1110] [1111] Post divider #2 (NP2) modulus [0000] [0001] [0010] [0011] [0100] [0101] [0110] POST2[3:0] [0111] [1000] [1001] [1010] [1011] [1100] [1101] [1110] [1111] Post divider #3 (NP3) modulus [00] POST3[1:0] [01] [10] [11] 1 2 3 4 5 6 7 8 9 10 11 12 Do not use 1 2 3 4 5 6 7 8 9 10 11 12 Do not use 1 2 4 8 Rev. 5 | Page 13 of 19 | www.onsemi.com FS714x 7.0 Electrical Specifications Table 10: Absolute Maximum Ratings Parameter Supply voltage, dc (VSS = ground) Input voltage, dc Output voltage, dc Input clamp current, dc (VI < 0 or VI > VDD) Output clamp current, dc (VI < 0 or VI > VDD) Storage temperature range (non-condensing) Ambient temperature range, under bias Junction temperature Re-flow solder profile Input static discharge voltage protection (MIL-STD 883E, Method 3015.7) Symbol VDD V1 VO IIK IOK TS TA TJ Min. VSS – 0.5 VSS – 0.5 VSS – 0.5 -50 -50 -65 -55 Max. 4.5 VDD + 0.5 VDD + 0.5 50 50 150 125 150 2 Units V V V mA mA °C °C °C Per IPC/JEDEC J-STD-020B kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only and functional operation of the device at these or any other conditions above the operational limited noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability. CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 11: Operating Conditions Parameter Supply voltage Ambient operating temperature range Symbol VDD TA Conditions/Description Min. 3.0 0 Typ. 3.3 Max. 3.6 70 Units V °C Rev. 5 | Page 14 of 19 | www.onsemi.com FS714x Table 12: DC Electrical Specifications Parameter Overall Supply current, dynamic Supply current, static Serial Communication I/O (SDA, SCL) High-level input voltage Low-level input voltage Hysteresis voltage Input leakage current Low-level output sink current (SDA) Address Select Input (ADDR0, ADDR1) High-level input voltage Low-level input voltage High-level input current (pull-down) Low-level input current Reference Frequency Input (REF) High-level input voltage Low-level input voltage High-level input current Low-level input current (pull-down) Sync Control Input (SYNC) High-level input voltage Low-level input voltage High-level input current Low-level input current (pull-down) Crystal Oscillator Input (XIN) Threshold bias voltage High-level input current Low-level input current Crystal frequency Recommended crystal load capacitance* Symbol IDD IDDL VIH VIL Vhys II IOL VIH VIL IIH IIL VIH VIL IIH IIL VIH VIL IIH IIL VTH IIH IIL FX CL(XTAL) Conditions/Description CMOS mode; FXTAL = 15MHz; FVCO = 400MHz; FCLK = 200MHz; does not include load current SHUT1, SHUT2 bit both “1” 0.8*VDD 0.33*VDD SDA, SCL in read condition SDA in acknowledge condition; VSDA = 0.4V -10 5 VDD – 1.0 0.8 VADDRx = VDD VADDRx = 0V 30 -1 VDD – 1.0 VREF = VDD VREF = 0V -1 -30 VDD – 1.0 VREF = VDD VREF = 0V VXIN = VDD VXIN = GND Fundamental mode For best matching with internal crystal oscillator load VXOUT = 0 VXOUT = VDD VIPRG = 0V; PECL mode VO = 2.0V VO = 0.4V VIPRG will be clamped to this level when a resistor is connected from VDD to IPRG IIPRG – (VVDD – VIPRG) / RSET -10 -10 19 -35 VDD/3 3.5 13 10 µA -1 -30 VDD/2 40 -40 35 16-18 -8.5 11 10 0.8 1 0.8 1 1 14 0.2*VDD +10 Min. Typ. 35 400 700 Max. Units mA µA V V V µA mA V V µA µA V V µA µA V V µA µA V µA µA MHz pF mA mA µA mA mA V mA Crystal Oscillator Output (XOUT) High-level output source current IOH Low-level output sink current IOL PECL Current Program I/O (IPRG) Low-level input current IIL Clock Outputs, CMOS Mode (CLKN, CLKP) High-level output source current IOH Low-level output sink current IOL Clock Outputs, PECL Mode (CLKN, CLKP) IPRG bias voltage IPRG bias current Sink current to IPRG current ratio Tristate output current VIPRG IIPRG IZ Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate flows out of the device. Rev. 5 | Page 15 of 19 | www.onsemi.com FS714x Table 13: AC Timing Specifications Parameter Overall Output frequency* fo(max) CMOS outputs PECL outputs CL = 7pF CL = 7pF CL = 7pF; RL = 65 ohm CL = 7pF; RL = 65 ohm 3 3 For orderly CLK stop/start For orderly CLK stop/start 3 3 VCO frequency* fVCO CMOS mode rise time* tr CMOS mode fall time* tf PECL mode rise time* tr PECL mode fall time* tf Reference Frequency Input (REF) Input frequency FREF Reference high time tREHF Reference low time tREFL Sync Control Input (SYNC) Sync high time tSYNCH Sync low time tSYNCL Clock Output (CLKP, CLKN) Duty cycle (CMOS mode)* Duty cycle (PECL mode)* 0 0 40 1 1 1 1 80 150 300 400 MHz MHz ns ns ns ns MHz ns ns TCLK TCLK % % ps ps ps ps ps ps ps ps ps Symbol Conditions/Description Clock (MHz) Min. Typ. Max. Units Jitter, long term (σy(τ))* tj(LT) Jitter, period (peak-peak)* tj(ΔP) Measured at 1.4V 50 Measured at zero crossings of (VCLKP – VCLKN) 50 For valid programming solutions. Long-term (or cumulative) jitter specified is RMS position error of any edge compared with an ideal clock generated from the same reference frequency. It is measured with a time interval analyzer using a 500 microsecond window, using statistics gathered over 1000 samples. FREF/NREF > 1000kHz 25 FREF/NREF ~= 500kHz 50 FREF/NREF ~= 250kHz 100 FREF/NREF ~= 125kHz 190 FREF/NREF ~= 62.5kHz 240 FREF/NREF ~= 31.5kHz 300 40MHz < VCO frequency 100MHz 50 Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Table 14: Serial Interface Timing Specifications Parameter Symbol Clock frequency Bus free time between STOP and START Set-up time, START (repeated) Hold time, START Set-up time, data input Hold time, data input Output data valid from clock Rise time, data and clock Fall time, data and clock High time, clock Low time, clock Set-up time, STOP fSCL tBUF Tsu:STA thd:STA Tsu:DAT thd:DAT tAA tR tF tHI tLO Tsu:STO Conditions/Description SCL SDA SDA SDA, SCL SDA, SCL SCL SCL Fast Mode Min. Max. 0 400 1300 600 600 100 0 900 300 300 600 1300 600 Units kHz ns ns ns ns ns ns ns ns ns ns ns Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Rev. 5 | Page 16 of 19 | www.onsemi.com FS714x Figure 8: Bus Timing Data Figure 9: Data Transfer Sequence Rev. 5 | Page 17 of 19 | www.onsemi.com FS714x 8.0 Package Information for ‘Green’ and ‘Non-Green’ Table 15: 16-pin SOIC (0.150") Package Dimensions Dimensions Inches Millimeters Min. Max. Min. Max. A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1.40 1.55 B 0.013 0.019 0.33 0.49 C 0.0075 0.0098 0.191 0.249 D 0.386 0.393 9.80 9.98 E 0.150 0.157 3.81 3.99 e 0.050 BSC 1.27 BSC H 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 0° 8° 0° 8° Θ Table 16: 16-pin SOIC (0.150") Package Characteristics Parameter Symbol Thermal impedance, junction to free-air ΘJA Lead inductance, self L11 Conditions/Description Air flow = 0ft./min. Corner lead Center lead Typ. 108 2.5 1.2 Units °C/W nH nH Table 17: 16-pin 5.3mm (0.209") SSOP Package Dimensions Dimensions Inches Millimeters Min. Max. Min. Max. A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 A2 0.066 0.070 1.68 1.78 B 0.010 0.015 0.25 0.38 C 0.005 0.008 0.13 0.20 D 0.239 0.249 6.07 6.33 E 0.205 0.212 5.20 5.38 e 0.0256 BSC 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.022 0.037 0.55 0.95 0 8 0 8 Θ Table 18: 16-pin 5.3mm (0.208") SSOP Package Characteristics Parameter Thermal impedance, junction to free-air Lead inductance, self Symbol ΘJA L11 Conditions/Description Air flows = 0ft./min Corner lead Center lead Typ. 90 2.3 1 Units °C/W nH nH Rev. 5 | Page 18 of 19 | www.onsemi.com FS714x 9.0 Ordering Information Part Number FS7145-01-XTD FS7145-01-XTP FS7140-02G-XTD FS7140-02G-XTP FS7140-01G-XTD FS7140-01G-XTP Package 16-pin (0.150”) SOIC 16-pin (0.150”) SOIC 16-pin (5.3mm) SSOP ‘Green’ or lead-free packaging 16-pin (5.3mm) SSOP ‘Green’ or lead-free packaging 16-pin (0.150”) SOIC ‘Green’ or lead-free packaging 16-pin (0.150”) SOIC ‘Green’ or lead-free packaging Shipping Configuration Tube/Tray Tape & Reel Tube/Tray Tape & Reel Tube/Tray Tape & Reel Temperature Range 0°C to 70°C (commercial) 0°C to 70°C (commercial) 0°C to 70°C (commercial) 0°C to 70°C (commercial) 0°C to 70°C (commercial) 0°C to 70°C (commercial) 10.0 Revision History Revision 3 4 5 Date February 2006 December 2007 May 2008 Modification Update to new AMIS template; update ordering codes Update to new ON Semiconductor template ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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