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MC100EP016A
3.3 V ECL 8-Bit
Synchronous Binary
Up Counter
Description
The MC100EP016A is a high-speed synchronous, presettable,
cascadeable 8-bit binary counter. Architecture and operation are the
same as the ECLinPS™ family MC100E016 with higher operating
speed.
The counter features internal feedback to TC gated by the TCLD
(Terminal Count Load) pin. When TCLD is LOW (or left open, in
which case it is pulled LOW by the internal pulldowns), the TC
feedback is disabled, and counting proceeds continuously, with TC
going LOW to indicate an all-one state. When TCLD is HIGH, the TC
feedback causes the counter to automatically reload upon TC = LOW,
thus functioning as a programmable counter. The Qn outputs do not
need to be terminated for the count function to operate properly. To
minimize noise and power, unused Q outputs should be left
unterminated.
COUT and COUT provide differential outputs from a single,
non-cascaded counter or divider application. COUT and COUT
should not be used in cascade configuration. Only TC should be used
for a counter or divider cascade chain output.
A differential clock input has also been added to improve
performance.
The 100 Series contains temperature compensation.
Features
•550 ps Typical Propagation Delay
•Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016
•PECL Mode Operating Range: VCC = 3.0 V to 3.6 V
with VEE = 0 V
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MARKING
DIAGRAMS*
MC100
EP016A
AWLYYWWG
LQFP-32
FA SUFFIX
CASE 873A
1
1
32
QFN32
MN SUFFIX
CASE 488AM
MC100
EP016A
AWLYYWWG
G
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
•NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -3.6 V
ORDERING INFORMATION
•Open Input Default State
•Safety Clamp on Clock Inputs
•Internal TC Feedback (Gated)
•Addition of COUT and COUT
•8-Bit
•Differential Clock Input
•VBB Output
•Fully Synchronous Counting and TC Generation
•Asynchronous Master Reset
•Pb-Free Packages are Available
© Semiconductor Components Industries, LLC, 2008
March, 2008 - Rev. 9
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
1
Publication Order Number:
MC100EP016A/D
MC100EP016A
VCC
Q2 Q1
Q0 VEE MR CE
Exposed Pad
(EP)
PE
VCC Q2
32
31
30
29
28
27
26
32
25
31
Q1
30
Q0 VEE MR CE
29
28
27
26
PE
25
VCC
1
24
VBB VCC
1
24 VBB
Q3
2
23
CLK
Q3
2
23 CLK
Q4
3
22
CLK
Q4
3
22 CLK
Q5
4
21
P0
Q5
4
MC100EP016A
21 P0
MC100EP016A
Q6
5
20
P1
Q6
5
20 P1
Q7
6
19
P2
Q7
6
19 P2
TCLD
7
18
P3 TCLD
7
18 P3
VCC
8
17
P4
VCC
8
17 P4
9
10
11
12
13
VEE COUT COUT TC VCC
14
15
P7
P6
16
9
10
11
12
13
14
15
16
VEE COUT COUT TC VCC P7
P6
P5
P5
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
Figure 2. 32-Lead QFN Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Function
P0-P7
ECL Parallel Data (Preset) Inputs
Q0-Q7
ECL Data Outputs
CE*
ECL Count Enable Control Input
PE*
ECL Parallel Load Enable Control Input
MR*
ECL Master Reset
CLK*, CLK*
ECL Differential Clock
TC
ECL Terminal Count Output
TCLD*
ECL TC-Load Control Input
COUT, COUT
ECL Differential Output
VCC
Positive Supply
VEE
Negative Supply
VBB
Reference Voltage Output
EP
The exposed pad (EP) on the QFN-32 package bottom is thermally connected to the die for improved
heat-sinking conduit. The pad is electrically connected to VEE.
*Pins will default LOW when left open.
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2
MC100EP016A
Table 2. FUNCTION TABLE
CE
PE
TCLD
MR
CLK
X
L
L
H
X
X
L
H
H
H
X
X
X
L
H
X
X
X
L
L
L
L
L
H
Z
Z
Z
Z
ZZ
X
FUNCTION
Load Parallel (Pn to Qn)
Continuous Count
Count; Load Parallel on TC = LOW
Hold
Masters Respond, Slaves Hold
Reset (Qn : = LOW, TC : = HIGH)
ZZ = Clock Pulse (High-to-Low)
Z = Clock Pulse (Low-to-High)
Table 3. FUNCTION TABLE
Function
PE
CE
MR
TCLD
CLK
P7-P4
P3
P2
P1
P0
Q7-Q4
Q3
Q2
Q1
Q0
TC
COUT
COUT
Load Count
L
H
H
H
H
X
L
L
L
L
L
L
L
L
L
X
L
L
L
L
Z
Z
Z
Z
Z
H
X
X
X
X
H
X
X
X
X
H
X
X
X
X
L
X
X
X
X
L
X
X
X
X
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
L
H
H
H
H
L
H
L
L
L
H
L
Load Hold
L
H
H
X
H
H
L
L
L
X
X
X
Z
Z
Z
H
X
X
H
X
X
H
X
X
L
X
X
L
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
Load on
Terminal
Count
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
Z
Z
Z
Z
Z
Z
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
H
H
H
H
L
H
L
H
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
L
L
H
L
L
L
Reset
X
X
H
X
X
X
X
X
X
X
L
L
L
L
L
H
H
L
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3
MC100EP016A
Q1
Q0
Q7
PE
TCLD
Q0M
MASTER Q0M SLAVE
CE
Q0
CE
CE Q
Q1 0
Q2
Q3
Q
Q5 Q4
BIT 1
BIT 0
BIT 7
6
P0
P1
P7
MR
CLK
BITS 2-6
CLK
TC
5
VBB
COUT
COUT
VEE
Note that this diagram is provided for understanding of logic operation only.
It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
Figure 3. 8‐BIT Binary Counter Logic Diagram
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4
MC100EP016A
Table 4. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
LQFP-32
QFN-32
Flammability Rating Oxygen Index: 28 to 34
> 2 kV
> 100 V
> 2 kV
Pb Pkg
Pb-Free Pkg
Level 2
N/A
Level 2
Level 1
UL 94 V-0 @ 0.125 in
Transistor Count
1226 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +70
°C
Tstg
Storage Temperature Range
-65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
32 LQFP
32 LQFP
74
61
°C/W
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
32 LQFP
12 to 17
°C/W
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
QFN-32
QFN-32
31
27
°C/W
°C/W
qJC
Thermal Resistance (Junction-to-Case)
2S2P
QFN-32
12
°C/W
Tsol
Wave Solder
265
265
°C
Pb
Pb-Free
VI VCC
VI VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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5
MC100EP016A
Table 6. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
-40°C
Symbol
Characteristic
25°C
70°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
130
170
210
130
177
210
130
180
210
mA
VOH
Output HIGH Voltage (Note 3)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 3)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
1875
2.0
1875
150
1875
150
0.5
0.5
mA
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V.
3. All loading with 50 ohms to VCC-2.0 volts.
4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 7. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.6 V to -3.0 V (Note 5)
-40°C
Symbol
Characteristic
25°C
70°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
130
170
210
130
177
210
130
180
210
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6)
-1145
-1020
-895
-1145
-1020
-895
-1145
-1020
-895
mV
VOL
Output LOW Voltage (Note 6)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
-1425
VEE+2.0
0.0
VEE+2.0
150
0.5
-1425
0.0
VEE+2.0
150
0.5
-1425
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC.
6. All loading with 50 ohms to VCC-2.0 volts.
7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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6
MC100EP016A
Table 8. AC CHARACTERISTICS VEE = -3.0 V to -3.6 V; VCC = 0 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 8)
-40°C
Symbol
fCOUNT
Min
Characteristic
Maximum Frequency
Count & Division Modes
Q, TC, COUT/COUT
Typ
25°C
Max
Min
Typ
70°C
Max
Min
Typ
Max
Unit
GHz
1.3
1.5
CLK to Q
MR to Q
CLK to TC
MR to TC
CLK to COUT/COUT
MR to COUT/COUT
350
400
350
400
475
450
511
550
511
555
705
720
1.4
400
400
400
400
500
500
550
570
550
570
745
760
1.3
480
450
480
520
550
570
610
630
610
635
825
830
Propagation Delay
tS
Setup Time
P0
P1 to P4
P5 to P7
CE
PE
TCLD
400
300
250
500
500
550
240
140
80
320
315
355
400
300
250
500
500
550
240
135
65
330
320
365
400
300
250
500
500
550
245
125
55
340
325
380
ps
tH
Hold Time
P0
P1 to P4
P5 to P7
CE
PE
TCLD
100
50
150
600
625
525
-145
-160
-105
380
465
320
100
50
150
600
625
525
-155
-170
-110
410
500
325
100
50
150
600
625
525
-170
-180
-115
450
535
340
ps
tJITTER
Clock Random Jitter
(RMS, 1000 Waveforms)
tRR
Reset Recovery Time
400
195
400
205
400
220
ps
tPW
Minimum Pulse Width CLK
Minimum Pulse Width MR
385
550
334
380
416
550
357
380
416
550
385
380
ps
tr, tf
Output Rise/Fall Times
20% - 80%
90
180
100
190
125
215
8.5
320
2.5
700
750
700
750
900
900
1.2
tPLH
tPHL
2.6
650
700
650
700
850
850
1.2
8.0
320
2.5
780
820
780
820
1000
950
8.0
450
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to VCC-2.0 V.
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7
MC100EP016A
APPLICATIONS INFORMATION
Cascading Multiple EP016A Devices
count one bit thus sending their terminal count outputs back
to a high state disabling the count operation of the more
significant counters and placing them back into hold modes.
Therefore, for an EP016A in the chain to count, all of the
lower order terminal count outputs must be in the low state.
The bit width of the counter can be increased or decreased
by simply adding or subtracting EP016A devices from
Figure 4 and maintaining the logic pattern illustrated in the
same figure.
The maximum frequency of operation for a cascaded
counter chain is set by the propagation delay of the TC output,
the necessary setup time of the CE input, and the propagation
delay through the OR gate controlling it (for 16-bit counters
the limitation is only the TC propagation delay and the CE
setup time). Figure 4 shows EP01 gates used to control the
count enable inputs, however, if the frequency of operation is
slow enough, a LVECL OR gate can be used. Using the worst
case guarantees for these parameters.
For applications which call for larger than 8‐bit counters
multiple EP016As can be tied together to achieve very wide
bit width counters. The active low terminal count (TC)
output and count enable input (CE) greatly facilitate the
cascading of EP016A devices. Two EP016As can be
cascaded without the need for external gating, however for
counters wider than 16 bits external OR gates are necessary
for cascade implementations.
Figure 4 below pictorially illustrates the cascading of 4
EP016As to build a 32‐bit high frequency counter. Note the
EP01 gates used to OR the terminal count outputs of the
lower order EP016As to control the counting operation of
the higher order bits. When the terminal count of the
preceding device (or devices) goes low (the counter reaches
an all 1s state) the more significant EP016A is set in its count
mode and will count one binary digit upon the next positive
clock transition. In addition, the preceding devices will also
LOAD
Q0 to Q7
LO
CE
PE
EP016
LSB
CLK
CLK
TC
Q0 to Q7
CE
Q0 to Q7
PE
CE
EP016
CLK
CLK
PE
CE
EP016
CLK
CLK
TC
PE
EP016
MSB
CLK
CLK
TC
TC
EP01
EP01
P0 to P7
Q0 to Q7
P0 to P7
P0 to P7
P0 to P7
CLK
CLK
Figure 4. 32‐Bit Cascaded EP016A Counter
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not the
case estimates of these delays need to be added to the
calculations.
data present at the parallel input pin (Pn's) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 5
below illustrates the input conditions necessary for utilizing
the EP016A as a programmable divider set up to divide by
113.
Programmable Divider
The EP016A has been designed with a control pin which
makes it ideal for use as an 8‐bit programmable divider. The
TCLD pin (load on terminal count) when asserted reloads the
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8
MC100EP016A
APPLICATIONS INFORMATION (continued)
H
L
L
P7
P6 P5
L
H
H
H
H
P4
P3
P2 P1 P0
Table 9. Preset Values for Various Divide Ratios
Preset Data Inputs
H
PE
Divide
Ratio
P7
P6
P5
P4
P3
P2
P1
P0
L
CE
2
H
H
H
H
H
H
H
L
H
TCLD
3
H
H
H
H
H
H
L
H
4
H
H
H
H
H
H
L
L
5
H
H
H
H
H
L
H
H
•
•
•
•
•
•
•
•
•
TC
CLK
COUT
CLK
COUT
Q4 Q3 Q2 Q1 Q0
Q7 Q6 Q5
Figure 5. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
Pn's = 256 - 113 = 8F16 = 1000 1111
where:
P0 = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 5
will result in the waveforms of Figure 6. Note that the TC
output is used as the divide output and the pulse duration is
equal to a full clock period. For even divide ratios, twice the
desired divide ratio can be loaded into the EP016A and the
TC output can feed the clock input of a toggle flip flop to
create a signal divided as desired with a 50% duty cycle.
Load
1001 0000
•
•
•
•
•
•
•
•
•
112
H
L
L
H
L
L
L
L
113
H
L
L
L
H
H
H
H
114
H
L
L
L
H
H
H
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
254
L
L
L
L
L
L
H
L
255
L
L
L
L
L
L
L
H
256
L
L
L
L
L
L
L
L
A single EP016A can be used to divide by any ratio from
2 to 256 inclusive. If divide ratios of greater than 256 are
needed multiple EP016As can be cascaded in a manner
similar to that already discussed. When EP016As are
cascaded to build larger dividers the TCLD pin will no
longer provide a means for loading on terminal count.
Because one does not want to reload the counters until all of
the devices in the chain have reached terminal count,
external gating of the TC pins must be used for multiple
EP016A divider chains.
1001 0001
1111 1100
•••
1111 1101
1111 1110
1111 1111
CLK
•••
PE
•••
TC
DIVIDE BY 113
Figure 6. Divide by 113 EP016A Programmable Divider Waveforms
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9
Load
MC100EP016A
APPLICATIONS INFORMATION (continued)
EP01
Q0 to Q7
LO
CE
PE
Q0 to Q7
CE
EP016
LSB
CLK
CLK
Q0 to Q7
PE
CE
EP016
TC
CLK
CLK
Q0 to Q7
PE
CE
EP016
CLK
CLK
TC
EP016
MSB
CLK
CLK
TC
EP01
P0 to P7
PE
TC
EP01
P0 to P7
P0 to P7
P0 to P7
CLK
CLK
Figure 7. 32‐Bit Cascaded EP016A Programmable Divider
Maximizing EP016A Count Frequency
Figure 7 shows a typical block diagram of a 32‐bit divider
chain. Once again to maximize the frequency of operation
EP01 OR gates were used. For lower frequency applications
a slower OR gate could replace the EP01. Note that for a
16‐bit divider the OR function feeding the PE (program
enable) input CANNOT be replaced by a wire OR tie as the
TC output of the least significant EP016A must also feed the
CE input of the most significant EP016A. If the two TC
outputs were OR tied the cascaded count operation would
not operate properly. Because in the cascaded form the PE
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
Q
The EP016A device produces 9 fast transitioning single
ended outputs, thus VCC noise can become significant in
situations where all of the outputs switch simultaneously in
the same direction. This VCC noise can negatively impact
the maximum frequency of operation of the device. Since
the device does not need to have the Q outputs terminated to
count properly, it is recommended that if the outputs are not
going to be used in the rest of the system they should be left
unterminated. In addition, if only a subset of the Q outputs
are used in the system only those outputs should be
terminated. Not terminating the unused outputs will not only
cut down the VCC noise generated but will also save in total
system power dissipation. Following these guidelines will
allow designers to either be more aggressive in their designs
or provide them with an extra margin to the published data
book specifications.
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
Zo = 50 W
D
50 W
50 W
VTT
VTT = VCC - 2.0 V
Figure 8. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
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10
MC100EP016A
ORDERING INFORMATION
Package
Shipping†
MC100EP016AFA
LQFP-32
250 Units / Tray
MC100EP016AFAG
LQFP-32
(Pb-Free)
250 Units / Tray
MC100EP016AFAR2
LQFP-32
2000 / Tape & Reel
MC100EP016AFAR2G
LQFP-32
(Pb-Free)
2000 / Tape & Reel
MC100EP016AMNG
QFN-32
(Pb-Free)
74 Units / Rail
MC100EP016AMNR4G
QFN-32
(Pb-Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
- ECL Clock Distribution Techniques
AN1406/D
- Designing with PECL (ECL at +5.0 V)
AN1503/D
- ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
- Metastability and the ECLinPS Family
AN1568/D
- Interfacing Between LVDS and ECL
AN1672/D
- The ECL Translator Guide
AND8001/D
- Odd Number Counters Design
AND8002/D
- Marking and Date Codes
AND8020/D
- Termination of ECL Logic Devices
AND8066/D
- Interfacing with ECLinPS
AND8090/D
- AC Characteristics of ECL Devices
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11
MC100EP016A
PACKAGE DIMENSIONS
A
4X
A1
32
-T-, -U-, -Z-
32 LEAD LQFP
CASE 873A-02
ISSUE C
25
0.20 (0.008) AB T-U Z
1
AE
-U-
-TB
P
V
17
8
BASE
METAL
DETAIL Y
V1
ÉÉ
ÉÉ
ÉÉ
ÉÉ
-Z9
S1
4X
0.20 (0.008) AC T-U Z
F
S
8X M_
J
R
D
DETAIL AD
G
SECTION AE-AE
-AB-
C E
-AC-
H
W
K
X
DETAIL AD
NOTES:
1.
DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.
CONTROLLING DIMENSION:
MILLIMETER.
3.
DATUM PLANE -AB- IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4.
DATUMS -T-, -U-, AND -Z- TO BE
DETERMINED AT DATUM PLANE -AB-.
5.
DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE -AC-.
6.
DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -AB-.
7.
DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8.
MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9.
EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
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12
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.450
0.750
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.018
0.030
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
Q_
0.250 (0.010)
0.10 (0.004) AC
GAUGE PLANE
SEATING
PLANE
M
N
9
0.20 (0.008)
DETAIL Y
AC T-U Z
AE
B1
MC100EP016A
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM-01
ISSUE O
A
B
ÉÉ
ÉÉ
D
PIN ONE
LOCATION
0.15 C
2X
2X
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
SEATING
PLANE
A1
SIDE VIEW
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.950 3.100 3.250
5.00 BSC
2.950 3.100 3.250
0.500 BSC
0.200
----0.300 0.400 0.500
C
L
EXPOSED PAD
32 X
D2
9
16
K
32 X
17
SOLDERING FOOTPRINT*
8
5.30
E2
3.20
1
24
32
32 X
25
32 X b
0.10 C A B
0.63
e
3.20
0.05 C
5.30
BOTTOM VIEW
32 X
0.28
28 X
0.50 PITCH
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
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