MC10EP57, MC100EP57
3.3V / 5V ECL 4:1
Differential Multiplexer
Description
The MC10/100EP57 is a fully differential 4:1 multiplexer. By
leaving the SEL1 line open (pulled LOW via the input pulldown
resistors) the device can also be used as a differential 2:1 multiplexer
with SEL0 input selecting between D0 and D1. The fully differential
architecture of the EP57 makes it ideal for use in low skew
applications such as clock distribution.
The SEL1 is the most significant select line. The binary number
applied to the select inputs will select the same numbered data input
(i.e., 00 selects D0).
Multiple VBB outputs are provided. The VBB pin, an internally
generated voltage supply, is available to this device only. For
single−ended input conditions, the unused differential input is
connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, VBB should be left open.
The 100 Series contains temperature compensation.
• 375 ps Typical Propagation Delays
• Maximum Frequency > 2 GHz Typical
• PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
VCC = 0 V with VEE = −3.0 V to −5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at VEE
VBB Outputs
Useful as Either 4:1 or 2:1 Multiplexer
These Devices are Pb−Free and are RoHS Compliant
April, 2014 − Rev. 13
XXXX
EP57
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
xxx
A
L
Y
W
G
• NECL Mode Operating Range:
© Semiconductor Components Industries, LLC, 2014
MARKING
DIAGRAM*
QFN−20
MN SUFFIX
CASE 485E
Features
•
•
•
•
•
•
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XXXX
EP57
ALYWG
G
= MC10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
1
Publication Order Number:
MC10EP57/D
MC10EP57, MC100EP57
VCC
SEL1
SEL0
VCC
Q
Q
VCC
20
19
18
17
16
15
VBB1
VBB2
VEE
14
13
12
11
4:1
1
2
3
4
5
6
7
8
9
10
VCC
D0
D0
D1
D1
D2
D2
D3
D3
VEE
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 20−Lead Package (Top View) and Logic Diagram
Exposed Pad
D0
VCC
20
19
18
17
16
D0
1
15
VCC
D1
2
14
Q
D1
3
D2
4
12
VCC
D2
5
11
VBB1
MC10/100EP57
6
NOTE:
VCC SEL1 SEL0
7
8
13
9
Q
10
D3 D3 VEE VEE VBB2
The Exposed Pad (EP) on package bottom must be attached to a heat−sinking conduit.
The Exposed Pad may only be electrically connected to VEE.
Figure 1. QFN−20 Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
Table 2. TRUTH TABLE
SEL1
SEL0
DATA OUT
D0 − 3*, D0 − 3*
ECL Differential Data Inputs
FUNCTION
L
L
D0, D0
SEL0*, SEL1*
ECL MUX Select Inputs
L
H
D1, D1
VBB1, VBB2
ECL Reference Output Voltage
H
L
D2, D2
Q, Q
ECL Data Outputs
H
H
D3, D3
VCC
Positive Supply
VEE
Negative Supply
EP
Exposed Pad
*Pins will default LOW when left open.
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2
MC10EP57, MC100EP57
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
TSSOP−20
QFN−20
Flammability Rating
Oxygen Index: 28 to 34
Pb Pkg
Pb−Free Pkg
Level 1
N/A
Level 3
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
584 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
−6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−20
TSSOP−20
140
100
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−20
23 to 41
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
QFN−20
QFN−20
47
33
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
QFN−20
18
°C/W
Tsol
Wave Solder
265
265
°C
Pb
Pb−Free
Condition 2
VI v VCC
VI w VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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MC10EP57, MC100EP57
Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 3)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 3)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single−Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single−Ended)
1365
1690
1460
1755
1490
1815
mV
VBB
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
1835
2.0
1900
150
0.5
1960
150
0.5
mA
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
3. All loading with 50 W to VCC − 2.0 V.
4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
Output HIGH Voltage (Note 6)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 6)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single−Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single−Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3490
3690
3555
3755
3685
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
Symbol
Characteristic
IEE
Power Supply Current
VOH
3535
2.0
150
0.5
3600
150
0.5
0.5
3660
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
6. All loading with 50 W to VCC − 2.0 V.
7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP57, MC100EP57
Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 8)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 9)
−1135
−1010
−885
−1070
−945
−820
−1010
−885
−760
mV
VOL
Output LOW Voltage (Note 9)
−1935
−1810
−1685
−1870
−1745
−1620
−1810
−1685
−1560
mV
VIH
Input HIGH Voltage (Single−Ended)
−1210
−885
−1145
−820
−1085
−760
mV
VIL
Input LOW Voltage (Single−Ended)
−1935
−1610
−1870
−1545
−1810
−1485
mV
VBB
Output Voltage Reference
−1510
−1310
−1445
−1245
−1385
−1185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
−1465
VEE + 2.0
0.0
−1400
VEE + 2.0
150
0.5
0.0
−1340
VEE + 2.0
150
0.5
mA
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with VCC.
9. All loading with 50 W to VCC − 2.0 V.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
Output HIGH Voltage (Note 12)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 12)
1305
1480
1605
1305
1480
1605
1305
1480
1605
mV
VIH
Input HIGH Voltage (Single−Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1305
1675
1305
1675
1305
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
1875
2.0
150
0.5
1875
150
0.5
0.5
1875
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
12. All loading with 50 W to VCC − 2.0 V.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP57, MC100EP57
Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 15)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 15)
3005
3180
3305
3005
3180
3305
3005
3180
3305
mV
VIH
Input HIGH Voltage (Single−Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3005
3375
3005
3375
3005
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 16)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
3575
2.0
3575
150
3575
150
0.5
0.5
mA
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
15. All loading with 50 W to VCC − 2.0 V.
16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 17)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
Output HIGH Voltage (Note 18)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
VOL
Output LOW Voltage (Note 18)
−1995
−1820
−1695
−1995
−1820
−1695
−1995
−1820
−1695
mV
VIH
Input HIGH Voltage (Single−Ended)
−1225
−880
−1225
−880
−1225
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1995
−1625
−1995
−1625
−1995
−1625
mV
VBB
Output Voltage Reference
−1525
−1325
−1525
−1325
−1525
−1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
−1425
VEE + 2.0
0.0
150
0.5
−1425
VEE + 2.0
0.0
150
0.5
−1425
VEE + 2.0
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17. Input and output parameters vary 1:1 with VCC.
18. All loading with 50 W to VCC − 2.0 V.
19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP57, MC100EP57
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
−40°C
Symbol
Characteristic
fmax
Maximum Frequency (Figure 2)
tPLH,
tPHL
Propagation Delay to
Output Differential
Min
Typ
25°C
Max
Min
Typ
>3
85°C
Max
Min
>3
Typ
Max
>3
Unit
GHz
ps
D to Q, Q
COM_SEL, SEL to Q, Q
tSKEW
Device to Device Skew (Note 21)
tJITTER
CLOCK Random Jitter (RMS)
@ v0.5 GHz
@ v1.0 GHz
@ v1.5 GHz
@ v2.0 GHz
@ v2.5 GHz
@ v3.0 GHz
250
300
350
400
450
500
275
320
375
420
200
475
520
320
320
420
450
200
520
575
200
ps
ps
0.122
0.110
0.112
0.128
0.114
0.116
0.3
0.3
0.3
0.3
0.3
0.3
0.140
0.135
0.132
0.139
0.129
0.152
0.3
0.3
0.3
0.3
0.3
0.3
0.172
0.151
0.152
0.163
0.177
0.305
0.3
0.3
0.3
0.3
0.3
1.0
VPP
Input Voltage Swing (Differential Configuration)
150
800
1200
150
800
1200
150
800
1200
mV
tr
tf
Output Rise/Fall Times
(20% − 80%)
70
120
170
70
140
200
70
150
220
ps
Q, Q
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
21. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
1000
900
VOUTpp (mV)
800
700
600
500
400
300
200
100
0
0
1000
2000
FREQUENCY (MHz)
Figure 2. Fmax
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7
3000
4000
MC10EP57, MC100EP57
Zo = 50 W
Q
D
Receiver
Device
Driver
Device
Zo = 50 W
Q
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping†
MC10EP57DTG
TSSOP−20
(Pb−Free)
75 Units / Rail
MC10EP57DTR2G
TSSOP−20
(Pb−Free)
2500 / Tape & Reel
MC10EP57MNG
QFN−20
(Pb−Free)
92 Units / Rail
MC10EP57MNTXG
QFN−20
(Pb−Free)
3000 / Tape & Reel
MC100EP57DTG
TSSOP−20
(Pb−Free)
75 Units / Rail
MC100EP57DTR2G
TSSOP−20
(Pb−Free)
2500 / Tape & Reel
MC100EP57MNG
QFN−20
(Pb−Free)
92 Units / Rail
MC100EP57MNTXG
QFN−20
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN20, 4x4, 0.5P
CASE 485E
ISSUE C
DATE 13 FEB 2018
SCALE 2:1
A
B
D
PIN ONE
REFERENCE
2X
0.15 C
ÉÉ
ÉÉ
EXPOSED
COPPER
ÉÉ
ÉÉ
ÇÇ
A3
A1
E
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
MOLD
COMPOUND
PLATING
A1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
DETAIL B
ALTERNATE
CONSTRUCTIONS
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
2X
0.15 C
L
L
TOP VIEW
(A3)
DETAIL B
L1
A
0.10 C
DETAIL A
OPTIONAL CONSTRUCTIONS
0.08 C
A1
SIDE VIEW
C
SEATING
PLANE
GENERIC
MARKING DIAGRAM*
20
0.10 C A B
D2
DETAIL A
20X
1
L
6
0.10 C A B
11
E2
20
20X
e
b
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
SOLDERING FOOTPRINT*
4.30
XXXXXX
XXXXXX
ALLYWG
G
XXXXXX= Specific Device Code
A
= Assembly Location
LL
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
1
K
MILLIMETERS
MIN
MAX
0.80
1.00
--0.05
0.20 REF
0.20
0.30
4.00 BSC
2.60
2.90
4.00 BSC
2.60
2.90
0.50 BSC
0.20 REF
0.35
0.45
0.00
0.15
20X
0.58
2.88
1
2.88 4.30
PKG
OUTLINE
20X
0.35
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON03163D
QFN20, 4X4, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
0.65
PITCH
16X
0.36
16X
1.26
DOCUMENT NUMBER:
98ASH70169A
DESCRIPTION:
TSSOP−20 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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