MTP23P06VG

MTP23P06V Preferred Device Power MOSFET 23 Amps, 60 Volts P−Channel TO−220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. http://onsemi.com 23 AMPERES, 60 VOLTS RDS(on) = 120 mW P−Channel D Features • Avalanche Energy Specified • IDSS and VDS(on) Specified at Elevated Temperature • Pb−Free Package is Available* G MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating S Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 1.0 MW) VDGR 60 Vdc Gate−to−Source Voltage − Continuous − Non−repetitive (tp ≤ 10 ms) VGS VGSM ± 15 ± 25 Vdc Vpk ID ID 23 15 81 Adc PD 90 0.60 W W/°C TJ, Tstg −55 to 175 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 23 Apk, L = 3.0 mH, RG = 25 W) EAS 794 mJ Thermal Resistance − Junction−to−Case Thermal Resistance − Junction−to−Ambient RqJC RqJA 1.67 62.5 °C/W TL 260 °C Drain Current − Continuous @ 25°C Drain Current − Continuous @ 100°C Drain Current − Single Pulse (tp ≤ 10 ms) Total Power Dissipation @ 25°C Derate above 25°C Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds IDM MARKING DIAGRAM AND PIN ASSIGNMENT Apk TO−220AB CASE 221A STYLE 5 1 2 3 MTP23P06V A Y WW G *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 1 2 Drain 3 Source = Device Code = Location Code = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device June, 2006 − Rev. 4 MTP 23P06VG AYWW 1 Gate Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. © Semiconductor Components Industries, LLC, 2006 4 Drain 4 Package Shipping MTP23P06V TO−220AB 50 Units/Rail MTP23P06VG TO−220AB (Pb−Free) 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MTP23P06V/D MTP23P06V ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 60 − − 60.5 − − Vdc mV/°C − − − − 10 100 − − 100 nAdc 2.0 − 2.8 5.3 4.0 − Vdc mV/°C − 0.093 0.12 W − − − − 3.3 3.2 5.0 11.5 − Ciss − 1160 1620 Coss − 380 530 Crss − 105 210 td(on) − 13.8 30 tr − 98.3 200 td(off) − 41 80 tf − 62 120 QT − 38 50 Q1 − 7.0 − Q2 − 18 − Q3 − 14 − − − 2.2 1.8 3.5 − trr − 142.2 − ta − 100.5 − tb − 41.7 − QRR − 0.804 − − 3.5 4.5 − − 7.5 − OFF CHARACTERISTICS V(BR)DSS Drain−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS mAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 11.5 Adc) RDS(on) Drain−Source On−Voltage (VGS = 10 Vdc, ID = 23 Adc) (VGS = 10 Vdc, ID = 11.5 Adc, TJ = 150°C) VDS(on) Forward Transconductance (VDS = 10.9 Vdc, ID = 11.5 Adc) Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 2) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 30 Vdc, ID = 23 Adc, VGS = 10 Vdc, RG = 9.1 W) Fall Time Gate Charge (See Figure 8) (VDS = 48 Vdc, ID = 23 Adc, VGS = 10 Vdc) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 23 Adc, VGS = 0 Vdc) (IS = 23 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 23 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge VSD Vdc ns mC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS 1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 nH nH MTP23P06V TYPICAL ELECTRICAL CHARACTERISTICS 40 VGS = 10V TJ = 25°C 40 8V 9V 7V 30 6V 20 10 5V 2 4 6 8 100°C 25 20 15 10 2 6 7 Figure 2. Transfer Characteristics TJ = 100°C 0.12 25°C 0.1 0.08 − 55°C 0.06 0.04 0.02 5 10 15 20 25 30 ID, DRAIN CURRENT (AMPS) 35 40 45 8 0.12 TJ = 25°C 0.115 0.11 0.105 VGS = 10 V 0.1 0.095 15 V 0.09 0.085 0.08 0 Figure 3. On−Resistance versus Drain Current and Temperature 5 10 15 20 30 35 25 ID, DRAIN CURRENT (AMPS) 40 45 50 Figure 4. On−Resistance versus Drain Current and Gate Voltage 1.8 100 VGS = 0 V VGS = 10 V ID = 11.5 A I DSS , LEAKAGE (nA) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 5 Figure 1. On−Region Characteristics 0.14 1.4 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) VGS = 10 V 1.6 3 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.16 0 25°C 30 0 10 R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) 0 TJ = −55°C 5 4V 0 VDS ≥ 10 V 35 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 50 1.2 1 0.8 0.6 TJ = 125°C 10 0.4 0.2 0 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 1 175 0 Figure 5. On−Resistance Variation with Temperature 50 10 20 30 40 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 60 MTP23P06V POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 4000 C, CAPACITANCE (pF) Ciss 3000 VGS = 0 V VDS = 0 V TJ = 25°C Crss 2000 Ciss 1000 Coss Crss 0 10 0 5 VGS 5 10 15 20 25 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 30 QT 9 8 27 24 Q2 Q1 VGS 7 21 6 18 5 15 4 12 9 3 2 Q3 1 0 0 5 TJ = 25°C ID = 23 A VDS 10 15 25 20 30 35 6 3 0 40 1000 t, TIME (ns) 10 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) MTP23P06V TJ = 25°C ID = 23 A VDD = 30 V VGS = 10 V 100 tr tf td(off) td(on) 10 1 1 10 Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 DRAIN−TO−SOURCE DIODE CHARACTERISTICS I S , SOURCE CURRENT (AMPS) 25 TJ = 25°C VGS = 0 V 20 15 10 5 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 5 MTP23P06V SAFE OPERATING AREA 800 VGS = 20 V SINGLE PULSE TC = 25°C EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 100 100 ms 10 1 ms 10 ms dc 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 600 500 400 300 200 100 0 0.1 0.1 ID = 23 A 700 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 25 100 50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 P(pk) 0.10 0.05 0.02 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 t, TIME (s) Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform E−FET is a trademark of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 6 RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E+00 1.0E+01 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220 CASE 221A ISSUE AK DATE 13 JAN 2022 SCALE 1:1 STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. BASE EMITTER COLLECTOR EMITTER STYLE 3: PIN 1. 2. 3. 4. CATHODE ANODE GATE ANODE STYLE 4: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE MAIN TERMINAL 2 STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 6: PIN 1. 2. 3. 4. ANODE CATHODE ANODE CATHODE STYLE 7: PIN 1. 2. 3. 4. CATHODE ANODE CATHODE ANODE STYLE 8: PIN 1. 2. 3. 4. CATHODE ANODE EXTERNAL TRIP/DELAY ANODE STYLE 9: PIN 1. 2. 3. 4. GATE COLLECTOR EMITTER COLLECTOR STYLE 10: PIN 1. 2. 3. 4. GATE SOURCE DRAIN SOURCE STYLE 11: PIN 1. 2. 3. 4. DRAIN SOURCE GATE SOURCE STYLE 12: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE NOT CONNECTED DOCUMENT NUMBER: DESCRIPTION: 98ASB42148B TO−220 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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