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or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
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MTP36N06V
Preferred Device
Power MOSFET
32 Amps, 60 Volts
N−Channel TO−220
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
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32 AMPERES
60 VOLTS
RDS(on) = 40 mΩ
N−Channel
D
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
VDGR
60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 25
Vdc
Vpk
ID
ID
32
22.6
112
Adc
PD
90
0.6
Watts
W/°C
TJ, Tstg
−55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak
IL = 32 Apk, L = 0.1 mH, RG = 25 Ω)
EAS
205
mJ
Thermal Resistance − Junction to Case
Thermal Resistance − Junction to Ambient
RθJC
RθJA
1.67
62.5
°C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10
seconds
TL
260
°C
Rating
Drain Current − Continuous @ 25 °C
Drain Current − Continuous @ 100 °C
Drain Current − Single Pulse (tp ≤ 10 μs)
Total Power Dissipation @ 25 °C
Derate above 25 °C
Operating and Storage Temperature
Range
IDM
G
S
MARKING DIAGRAM
& PIN ASSIGNMENT
Apk
4
Drain
4
TO−220AB
CASE 221A
STYLE 5
1
2
3
MTP30N06V
LLYWW
1
Gate
3
Source
2
Drain
MTP30N06V
LL
Y
WW
= Device Code
= Location Code
= Year
= Work Week
ORDERING INFORMATION
Device
MTP36N06V
Package
Shipping
TO−220AB
50 Units/Rail
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 4
1
Publication Order Number:
MTP36N06V/D
MTP36N06V
ELECTRICAL CHARACTERISTICS (TJ = 25 °C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
−
−
61
−
−
Vdc
mV/°C
−
−
−
−
10
100
−
−
100
nAdc
2.0
−
2.6
6.0
4.0
−
Vdc
mV/°C
−
0.034
0.04
Ohm
−
−
1.25
−
1.54
1.47
gFS
5.0
7.83
−
mhos
Ciss
−
1220
1700
pF
Coss
−
337
470
Crss
−
74.8
150
td(on)
−
14
30
tr
−
138
270
td(off)
−
54
100
tf
−
91
180
QT
−
39
50
Q1
−
7.0
−
Q2
−
17
−
Q3
−
13
−
−
−
1.03
0.94
2.0
−
trr
−
92
−
ta
−
64
−
tb
−
28
−
QRR
−
0.332
−
−
3.5
4.5
−
−
7.5
−
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 μAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150 °C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
μAdc
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 μAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 16 Adc)
RDS(on)
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID = 32 Adc)
(VGS = 10 Vdc, ID = 16 Adc, TJ = 150 °C)
VDS(on)
Forward Transconductance (VDS = 7.6 Vdc, ID = 16 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 30 Vdc, ID = 32 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Fall Time
Gate Charge
(See Figure 8)
(VDS = 48 Vdc, ID = 32 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 32 Adc, VGS = 0 Vdc)
(IS = 32 Adc, VGS = 0 Vdc,
TJ = 150 °C)
Reverse Recovery Time
(IS = 32 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs)
Reverse Recovery Stored
Charge
VSD
Vdc
ns
μC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
1. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
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2
nH
nH
MTP36N06V
TYPICAL ELECTRICAL CHARACTERISTICS
72
7V
9V
54
TJ = 100°C
VDS ≥ 10 V
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
72
VGS = 10 V
TJ = 25°C
8V
6V
36
5V
18
25°C
54
36
18
−55°C
4V
0
1
0.1
2
3
0
4
5
6
7
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.08
TJ = 100°C
0.06
25°C
0.04
−55°C
0.02
0
0
18
36
54
ID, DRAIN CURRENT (AMPS)
72
8
9
0.052
TJ = 25°C
0.044
VGS = 10 V
0.036
0.028
15 V
0
Figure 3. On−Resistance versus Drain Current
and Temperature
18
36
54
ID, DRAIN CURRENT (AMPS)
72
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.8
1000
VGS = 0 V
VGS = 10 V
ID = 16 A
TJ = 125°C
I DSS , LEAKAGE (nA)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
4
3
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
VGS = 10 V
1.6
2
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
1.4
1.2
1
100
100°C
10
25°C
0.8
0.6
−50
1
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
150
175
0
Figure 5. On−Resistance Variation with
Temperature
10
20
40
50
30
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
60
MTP36N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
4000
C, CAPACITANCE (pF)
VDS = 0 V
3000
VGS = 0 V
TJ = 25°C
Ciss
2000
Ciss
Crss
1000
Coss
0
Crss
10
5
0
VGS
5
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
QT
25
10
VGS
8
20
Q2
Q1
15
6
4
Q3
2
0
10
TJ = 25°C
ID = 32 A
5
VDS
0
5
10
15
20
25
30
35
40
0
1000
TJ = 25°C
ID = 32 A
VDD = 30 V
VGS = 10 V
t, TIME (ns)
30
12
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MTP36N06V
tr
100
tf
td(off)
td(on)
10
1
1
10
QT, TOTAL CHARGE (nC)
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
32
I S , SOURCE CURRENT (AMPS)
TJ = 25°C
VGS = 0 V
24
16
8
0
0.5 0.55
0.6 0.65
0.7 0.75
0.8 0.85 0.9
0.95
1
1.05
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
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5
MTP36N06V
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25°C
225
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
1000
100
10 μs
10
100 μs
1 ms
10 ms
dc
1
0.1
1
175
150
125
100
75
50
25
0
100
10
ID = 32 A
200
25
50
75
100
125
150
175
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.00
D = 0.5
0.2
0.1
P(pk)
0.10 0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
1.0E+00
1.0E+01
MTP36N06V
PACKAGE DIMENSIONS
TO−220 THREE−LEAD
TO−220AB
CASE 221A−09
ISSUE AA
SEATING
PLANE
−T−
B
F
T
C
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 5:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
GATE
DRAIN
SOURCE
DRAIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MTP36N06V/D