MUN5336DW1T1G

MUN5336DW1, NSBC115EPDXV6 Complementary Bias Resistor Transistors R1 = 100 kW, R2 = 100 kW www.onsemi.com NPN and PNP Transistors with Monolithic Bias Resistor Network PIN CONNECTIONS This series of digital transistors is designed to replace a single device and its external resistor bias network. The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base-emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. (3) (2) R1 • R2 Q1 Q2 R2 Features • • • • (1) Simplifies Circuit Design Reduces Board Space Reduces Component Count NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant (4) R1 (5) (6) MARKING DIAGRAMS 6 36 M G G SOT−363 CASE 419B MAXIMUM RATINGS 1 (TA = 25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted) Rating 36 M G = Specific Device Code = Date Code* = Pb-Free Package Symbol Max Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc (Note: Microdot may be in either location) IC 100 mAdc Input Forward Voltage VIN(fwd) 40 Vdc *Date Code orientation may vary depending upon manufacturing location. Input Reverse Voltage VIN(rev) 10 Vdc Collector Current − Continuous Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1 ORDERING INFORMATION Package Shipping† MUN5336DW1T1G, NSVMUN5336DW1T1G* SOT−363 3,000 / Tape & Reel NSBC115EPDXV6T1G, NSVBC115EPDXV6T1G* SOT−563 4,000 / Tape & Reel Device SOT−563 CASE 463A 6 36 MG 1 36 = Specific Device Code M = Month Code G = Pb−Free Package †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This document contains information on some products that are still under development. ON Semiconductor reserves the right to change or discontinue these products without notice. © Semiconductor Components Industries, LLC, 2014 October, 2017 − Rev. 1 1 Publication Order Number: DTC115EP/D MUN5336DW1, NSBC115EPDXV6 THERMAL CHARACTERISTICS Characteristic Symbol Max Unit 187 256 1.5 2.0 mW MUN5336DW1 (SOT−363) ONE JUNCTION HEATED Total Device Dissipation TA = 25°C (Note 1) (Note 2) Derate above 25°C (Note 1) (Note 2) Thermal Resistance, Junction to Ambient PD (Note 1) (Note 2) RqJA mW/°C 670 490 °C/W 250 385 2.0 3.0 mW MUN5336DW1 (SOT−363) BOTH JUNCTION HEATED (Note 3) PD Total Device Dissipation (Note 1) TA = 25°C (Note 2) Derate above 25°C (Note 1) (Note 2) Thermal Resistance, Junction to Ambient (Note 2) RqJA (Note 1) Thermal Resistance, Junction to Lead (Note 1) (Note 2) RqJL Junction and Storage Temperature Range TJ, Tstg mW/°C °C/W 493 325 °C/W 188 208 −55 to +150 °C 357 2.9 mW mW/°C NSBC115EPDXV6 (SOT−563) ONE JUNCTION HEATED PD Total Device Dissipation (Note 1) TA = 25°C Derate above 25°C (Note 1) Thermal Resistance, Junction to Ambient RqJA (Note 1) °C/W 350 NSBC115EPDXV6 (SOT−563) BOTH JUNCTION HEATED (Note 3) PD Total Device Dissipation (Note 1) TA = 25°C Derate above 25°C (Note 1) Thermal Resistance, Junction to Ambient 500 4.0 RqJA (Note 1) Junction and Storage Temperature Range TJ, Tstg 1. FR−4 @ Minimum Pad. 2. FR−4 @ 1.0 × 1.0 Inch Pad. 3. Both junction heated values assume total power is sum of two equally powered channels. www.onsemi.com 2 mW mW/°C °C/W 250 −55 to +150 °C MUN5336DW1, NSBC115EPDXV6 ELECTRICAL CHARACTERISTICS (TA = 25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted) Symbol Characteristic Min Typ Max − − 100 − − 500 − − 0.05 50 − − 50 − − 80 150 − − − 0.25 − − 1.2 1.2 0.5 0.5 3.0 3.0 1.7 1.6 − − − − 0.2 4.9 − − Unit OFF CHARACTERISTICS Collector-Base Cutoff Current (VCB = 50 V, IE = 0) ICBO Collector-Emitter Cutoff Current (VCE = 50 V, IB = 0) ICEO Emitter-Base Cutoff Current (VEB = 6.0 V, IC = 0) IEBO nAdc nAdc mAdc Collector-Base Breakdown Voltage (IC = 10 mA, IE = 0) V(BR)CBO Collector-Emitter Breakdown Voltage (Note 4) (IC = 2.0 mA, IB = 0) V(BR)CEO Vdc Vdc ON CHARACTERISTICS hFE DC Current Gain (Note 4) (IC = 5.0 mA, VCE = 10 V) Collector-Emitter Saturation Voltage (Note 4) (IC = 10 mA, IB = 0.3 mA) VCE(sat) Input Voltage (Off) (VCE = 5.0 V, IC = 100 mA) (NPN) (VCE = 5.0 V, IC = 100 mA) (PNP) Vi(off) Input Voltage (On) (VCE = 0.3 V, IC = 3.0 mA) (NPN) (VCE = 0.3 V, IC = 3.0 mA) (PNP) Vi(on) Output Voltage (On) (VCC = 5.0 V, VB = 5.5 V, RL = 1.0 kW) VOL Output Voltage (Off) (VCC = 5.0 V, VB = 0.5 V, RL = 1.0 kW) VOH V Vdc Vdc Vdc Vdc Input Resistor R1 70 100 130 Resistor Ratio R1/R2 0.8 1.0 1.2 kW Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle ≤ 2%. PD, POWER DISSIPATION (mW) 400 350 300 250 200 (1) SOT−363; 1.0 × 1.0 Inch Pad (2) SOT−563; Minimum Pad (1) (2) 150 100 50 0 −50 −25 0 25 50 75 100 AMBIENT TEMPERATURE (°C) Figure 1. Derating Curve www.onsemi.com 3 125 150 MUN5336DW1, NSBC115EPDXV6 1000 1 VCE = 10 V IC/IB = 10 TA = −25°C hFE, DC CURRENT GAIN VCE(sat), COLLECTOR−EMITTER VOLTAGE (V) TYPICAL CHARACTERISTICS − NPN TRANSISTOR MUN5336DW1, NSBC115EPDXV6 25°C 75°C 0.1 75°C 25°C 100 0.01 0 5 15 25 10 20 30 IC, COLLECTOR CURRENT (mA) 35 TA = −25°C 10 40 10 1 IC, COLLECTOR CURRENT (mA) 0.1 Figure 2. VCE(sat) vs. IC Figure 3. DC Current Gain 100 3.2 IC, COLLECTOR CURRENT (mA) 3.6 f = 10 kHz lE = 0 A TA = 25°C 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 75°C TA = −25°C 10 25°C 1 VO = 5 V 0.1 0 10 20 30 40 VR, REVERSE VOLTAGE (V) 0 50 Figure 4. Output Capacitance 5 10 15 20 25 30 Vin, INPUT VOLTAGE (V) VO = 0.2 V 25°C TA = −25°C 75°C 10 1 0.1 0 5 35 Figure 5. Output Current vs. Input Voltage 100 Vin, INPUT VOLTAGE (V) Cob, CAPACITANCE (pF) 100 10 20 15 25 IC, COLLECTOR CURRENT (mA) 30 Figure 6. Input Voltage vs. Output Current www.onsemi.com 4 35 40 MUN5336DW1, NSBC115EPDXV6 TYPICAL CHARACTERISTICS − PNP TRANSISTOR MUN5336DW1, NSBC115EPDXV6 1000 25°C IC/IB = 10 150°C hFE, DC CURRENT GAIN VCE(sat), COLLECTOR−EMITTER VOLTAGE (V) 10 1 25°C 150°C 0.1 100 10 −55°C VCE = 10 V 0.01 1 0 10 20 30 40 50 0.1 1 10 100 IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA) Figure 7. VCE(sat) vs. IC Figure 8. DC Current Gain 12 100 10 IC, COLLECTOR CURRENT (mA) f = 10 kHz IE = 0 A TA = 25°C 8 6 4 2 0 150°C −55°C 10 25°C 1 0.1 VO = 5 V 0.01 0 10 20 30 40 0 50 4 8 12 16 20 24 VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V) Figure 9. Output Capacitance Figure 10. Output Current vs. Input Voltage 100 Vin, INPUT VOLTAGE (V) Cob, OUTPUT CAPACITANCE (pF) −55°C −55°C 25°C 10 150°C 1 VO = 0.2 V 0.1 0 10 20 30 40 IC, COLLECTOR CURRENT (mA) Figure 11. Input Voltage vs. Output Current www.onsemi.com 5 50 28 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y 1 SCALE 2:1 DATE 11 DEC 2012 2X aaa H D D H A D 6 5 GAGE PLANE 4 1 2 L L2 E1 E DETAIL A 3 aaa C 2X bbb H D 2X 3 TIPS e B 6X b ddd TOP VIEW C A-B D M A2 DETAIL A A 6X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END. 4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. ccc C A1 SIDE VIEW C SEATING PLANE END VIEW c RECOMMENDED SOLDERING FOOTPRINT* 6X DIM A A1 A2 b C D E E1 e L L2 aaa bbb ccc ddd MILLIMETERS MIN NOM MAX −−− −−− 1.10 0.00 −−− 0.10 0.70 0.90 1.00 0.15 0.20 0.25 0.08 0.15 0.22 1.80 2.00 2.20 2.00 2.10 2.20 1.15 1.25 1.35 0.65 BSC 0.26 0.36 0.46 0.15 BSC 0.15 0.30 0.10 0.10 GENERIC MARKING DIAGRAM* 6 XXXMG G 6X 0.30 INCHES NOM MAX −−− 0.043 −−− 0.004 0.035 0.039 0.008 0.010 0.006 0.009 0.078 0.086 0.082 0.086 0.049 0.053 0.026 BSC 0.010 0.014 0.018 0.006 BSC 0.006 0.012 0.004 0.004 MIN −−− 0.000 0.027 0.006 0.003 0.070 0.078 0.045 0.66 1 2.50 0.65 PITCH XXX = Specific Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *Date Code orientation and/or position may vary depending upon manufacturing location. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y DATE 11 DEC 2012 STYLE 1: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 2: CANCELLED STYLE 3: CANCELLED STYLE 4: PIN 1. CATHODE 2. CATHODE 3. COLLECTOR 4. EMITTER 5. BASE 6. ANODE STYLE 5: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 6: PIN 1. ANODE 2 2. N/C 3. CATHODE 1 4. ANODE 1 5. N/C 6. CATHODE 2 STYLE 7: PIN 1. SOURCE 2 2. DRAIN 2 3. GATE 1 4. SOURCE 1 5. DRAIN 1 6. GATE 2 STYLE 8: CANCELLED STYLE 9: PIN 1. EMITTER 2 2. EMITTER 1 3. COLLECTOR 1 4. BASE 1 5. BASE 2 6. COLLECTOR 2 STYLE 10: PIN 1. SOURCE 2 2. SOURCE 1 3. GATE 1 4. DRAIN 1 5. DRAIN 2 6. GATE 2 STYLE 11: PIN 1. CATHODE 2 2. CATHODE 2 3. ANODE 1 4. CATHODE 1 5. CATHODE 1 6. ANODE 2 STYLE 12: PIN 1. ANODE 2 2. ANODE 2 3. CATHODE 1 4. ANODE 1 5. ANODE 1 6. CATHODE 2 STYLE 13: PIN 1. ANODE 2. N/C 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 14: PIN 1. VREF 2. GND 3. GND 4. IOUT 5. VEN 6. VCC STYLE 15: PIN 1. ANODE 1 2. ANODE 2 3. ANODE 3 4. CATHODE 3 5. CATHODE 2 6. CATHODE 1 STYLE 16: PIN 1. BASE 1 2. EMITTER 2 3. COLLECTOR 2 4. BASE 2 5. EMITTER 1 6. COLLECTOR 1 STYLE 17: PIN 1. BASE 1 2. EMITTER 1 3. COLLECTOR 2 4. BASE 2 5. EMITTER 2 6. COLLECTOR 1 STYLE 18: PIN 1. VIN1 2. VCC 3. VOUT2 4. VIN2 5. GND 6. VOUT1 STYLE 19: PIN 1. I OUT 2. GND 3. GND 4. V CC 5. V EN 6. V REF STYLE 20: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 21: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. N/C 6. CATHODE 1 STYLE 22: PIN 1. D1 (i) 2. GND 3. D2 (i) 4. D2 (c) 5. VBUS 6. D1 (c) STYLE 23: PIN 1. Vn 2. CH1 3. Vp 4. N/C 5. CH2 6. N/C STYLE 24: PIN 1. CATHODE 2. ANODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE STYLE 25: PIN 1. BASE 1 2. CATHODE 3. COLLECTOR 2 4. BASE 2 5. EMITTER 6. COLLECTOR 1 STYLE 26: PIN 1. SOURCE 1 2. GATE 1 3. DRAIN 2 4. SOURCE 2 5. GATE 2 6. DRAIN 1 STYLE 27: PIN 1. BASE 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. EMITTER 2 6. COLLECTOR 2 STYLE 28: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 29: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE/ANODE 6. CATHODE STYLE 30: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1 Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−563, 6 LEAD CASE 463A ISSUE H 6 1 SCALE 4:1 DOCUMENT NUMBER: DESCRIPTION: 98AON11126D SOT−563, 6 LEAD DATE 26 JAN 2021 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOT−563, 6 LEAD CASE 463A ISSUE H DATE 26 JAN 2021 GENERIC MARKING DIAGRAM* XX MG 1 XX = Specific Device Code M = Month Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON11126D SOT−563, 6 LEAD Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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