NB3L14SMNG

NB3L14S 2.5 V 1:4 LVDS Fanout Buffer The NB3L14S is a differential 1:4 LVDS Clock fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. The NB3L14S LVDS signals will be buffered and replicated to identical LVDS copies of the Input operating up to 300 MHz. As such, the NB3L14S is ideal for Clock distribution applications that require low skew. The NB3L14S is offered in a small 3 mm x 3 mm 16−QFN package. Application notes, models, and support documentation are available at www.onsemi.com. http://onsemi.com MARKING DIAGRAM* 16 1 QFN−16 MN SUFFIX CASE 485G Features • • • • • • Maximum Input Clock Frequency; 300 MHz Low Output−to−Output Skew; 20 ps 450 ps Typical Propagation Delay 250 ps Typical Rise and Fall Times Single Power Supply; VCC = 2.5 $ 5% These are Pb−Free Devices 1 A L Y W G NB3L 14S ALYW G G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Q0 Q0 VCC Q1 Q1 IN W VT 50 50 W IN Q2 Q2 VCC Q3 Q3 Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2012 November, 2012 − Rev. 0 1 Publication Order Number: NB3L14S/D NB3L14S Q0 Q0 16 15 VCC GND 14 Exposed Pad (EP) 13 Q1 1 12 IN Q1 2 11 VT NB3L14S Q2 3 10 NC Q2 4 9 5 6 Q3 Q3 7 Table 1. TRUTH TABLE IN IN* IN* Q Q 0 1 0 1 1 0 1 0 x x 0 (Note 1) 1 (Note 1) 1. Outputs will be at the known state in this table at initial power up. The outputs will also be at the known state during normal operation when inputs are left open. *Defaults high when left open 8 VCC VCC Figure 2. NB3L14S Pinout, 16−pin QFN (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 Q1 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 2 Q1 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 3 Q2 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 4 Q2 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 5 Q3 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 6 Q3 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 7 VCC − Positive Supply Voltage. 8 VCC − Positive Supply Voltage. 9 IN LVDS 10 NC No Connect 11 VT Input Termination 12 IN LVDS 13 GND − Negative Supply Voltage. 14 VCC − Positive Supply Voltage. 15 Q0 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 16 Q0 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. − EP − Inverted Differential Input; pin will default HIGH when left open This is not connected. Internal 100 W Center−tapped Termination Pin for IN and IN, leave open for LVDS. Non−inverted Differential Input; pin will default HIGH when left open. The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and is required to be electrically and thermally connected to GND on the PC board. http://onsemi.com 2 NB3L14S Table 3. ATTRIBUTES Characteristics Value Moisture Sensitivity (Note 2) Flammability Rating Level 1 Oxygen Index: 28 to 34 Input Pull−up Resistors to VCC on Inputs ESD Protection UL 94 V−0 @ 0.125 in 200 kW Human Body Model Machine Model > 4 kV > 200 V Transistor Count 440 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 VCC Positive Power Supply GND = 0 V VIN Positive Input GND = 0 V IIN Input Current Through RT (50 W Resistor) Static Surge IOSC Output Short Circuit Current Line−to−Line (Q to Q) Line−to−GND (Q or Q to GND) Q or Q Q to Q to GND TA Operating Temperature Range QFN−16 Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 3) Tsol Wave Solder Pb−Free Condition 2 VIN ≤ VCC Continuous Continuous Rating Unit 4.6 V 4.6 V 35 70 mA mA 12 24 mA −40 to +85 °C −65 to +150 °C QFN−16 QFN−16 41.6 35.2 °C/W °C/W QFN−16 4.0 °C/W 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB3L14S Table 5. DC CHARACTERISTICS VCC = 2.375 V to 2.625 V, GND = 0 V, TA = −40°C to +85°C Symbol ICC Characteristic Min Power Supply Current (Note 4) Typ Max Unit 45 65 mA DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 4, 8, and 9) (Note 5) VIHD Differential Input HIGH Voltage 1150 1800 mV VILD Differential Input LOW Voltage GND VIHD − 150 mV VCMR Input Common Mode Range (Differential Configuration) (Note 6) 75 1725 mV VID Differential Input Voltage (VIHD − VILD) 150 1800 mV RTIN Internal Input Termination Resistor 40 50 60 W 250 350 450 mV 0 1 25 mV 1125 1250 1375 mV 1 25 mV 1425 1600 mV LVDS OUTPUTS (Note 7) VOD Differential Output Voltage (Single−Ended Measurement) DVOD Change in Magnitude of VOD for Complementary Output States (Note 8) VOS Offset Voltage (Figure 7) DVOS Change in Magnitude of VOS for Complementary Output States (Note 8) VOH Output HIGH Voltage (Note 9) VOL Output LOW Voltage (Note 10) 0 900 1075 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input pins, IN = 300 mV, IN = 1 V. Output pins loaded with RL = 100 W across the outputs. 5. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 6. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. 7. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 6. 8. Parameter guaranteed by design verification not tested in production. 9. VOHmax = VOSmax + ½ VODmax. 10. VOLmax = VOSmin − ½ VODmax. http://onsemi.com 4 NB3L14S Table 6. AC CHARACTERISTICS (VCC = 2.375 V to 2.625 V, GND = 0 V) −40°C to +85°C Symbol Min Characteristic finMax Maximum Input Clock Frequency VOUTPP Output Voltage Amplitude (@ VINPPmin) tPLH, tPHL Differential Input to Differential Output, IN to Q Propagation Delay @ 50 MHz tSKEW Within Device Output−to−Output Skew (Note 12) Device−to−Device Skew (Note 12) VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 11) tr tf Output Rise/Fall Times @ 50 MHz (20% − 80%) Typ Max 300 fin ≤ 300 MHz Unit MHz 250 350 450 mV 300 450 600 ps 5 30 20 200 ps 1800 mV 350 ps 150 Q, Q 250 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input voltage swing is a single−ended measurement operating in differential mode. 12. Skew is measured between outputs under identical transition @ 50 MHz. OUTPUT VOLTAGE AMPLITUDE (mV) 400 350 300 250 200 150 100 50 0 0 100 200 300 400 INPUT CLOCK FREQUENCY (MHz) Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature (@ VCC = 2.5 V) http://onsemi.com 5 NB3L14S VCC = 3.3 V or 2.5 V VCC = 2.5 V NB3L14S IN Zo = 50 W 50 W LVDS Driver VT = OPEN 50 W Zo = 50 W IN GND GND Figure 4. LVDS Interface IN VINPP = VIH(IN) − VIL(IN) IN Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 5. AC Reference Measurement Q LVDS Driver Device Zo = 50 W HI Z Probe D 100 W Q Zo = 50 W Oscilloscope HI Z Probe D Figure 6. Typical LVDS Termination for Output Driver and Device Evaluation QN VOH VOS IN VOD VOL QN IN Figure 7. LVDS Output Figure 8. Differential Inputs Driven Differentially http://onsemi.com 6 NB3L14S VCC VIHD(MAX) VCMRmax VILD(MAX) VIHD VID = VIHD − VILD VCMR VILD VIHD(MIN) VCMRmin VILD(MIN) GND Figure 9. VCMR Diagram Figure 10. Tape and Reel Pin 1 Quadrant Orientation ORDERING INFORMATION Package Shipping† NB3L14SMNG QFN−16, 3 X 3 mm (Pb−Free) 123 Units / Rail NB3L14SMNTXG QFN−16, 3 X 3 mm (Pb−Free) 3000 / Tape & Reel (Pin 1 Orientation in Quadrant B, Figure 10) Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NB3L14S PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE F D ÇÇÇ ÇÇÇ ÇÇÇ PIN 1 LOCATION 2X A B L DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E ÉÉ ÉÉ EXPOSED Cu 0.10 C TOP VIEW (A3) DETAIL B 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 0.10 C 2X L ÇÇ ÉÉ A1 DETAIL B A 0.05 C A3 MOLD CMPD ALTERNATE CONSTRUCTIONS NOTE 4 A1 SIDE VIEW C SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.03 0.05 0.20 REF 0.18 0.24 0.30 3.00 BSC 1.65 1.75 1.85 3.00 BSC 1.65 1.75 1.85 0.50 BSC 0.18 TYP 0.30 0.40 0.50 0.00 0.08 0.15 RECOMMENDED SOLDERING FOOTPRINT* 0.10 C A B 16X L DETAIL A D2 8 4 16X 16X 0.58 PACKAGE OUTLINE 1 9 2X E2 K 2X 1.84 3.30 1 16X 16 e e/2 BOTTOM VIEW 16X 0.30 b 0.50 PITCH 0.10 C A B 0.05 C NOTE 3 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. AnyLevel and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC). 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