NB6N14S
3.3 V 1:4 AnyLevelt
Differential Input to LVDS
Fanout Buffer/Translator
The NB6N14S is a differential 1:4 Clock or Data Receiver and will
accept AnyLevelt differential input signals: LVPECL, CML or
LVDS. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6N14S has a wide input common mode range from
GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6N14S is ideal for
translating a variety of differential or single−ended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB6N14S is offered in a small 3 mm x 3 mm 16−QFN
package. Application notes, models, and support documentation are
available at www.onsemi.com.
The NB6N14S is a member of the ECLinPS MAXt family of high
performance products.
Features
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum RMS Clock Jitter
Typically 10 ps Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
VREF_AC Reference Output
TIA/EIA − 644 Compliant
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
These are Pb−Free Devices
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MARKING
DIAGRAM*
16
1
QFN−16
MN SUFFIX
CASE 485G
1
A
L
Y
W
G
NB6N
14S
ALYW G
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
Q1
Q1
IN
W
VT 50
W
50
/IN
+
Q2
Q2
RPU
EN
(LVTTL/CMOS)
D
Q
Q3
VOLTAGE (130 mV/div)
VREF_AC
Q3
Figure 1. Logic Diagram
Device DDJ = 10 ps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
© Semiconductor Components Industries, LLC, 2013
September, 2013 − Rev. 8
1
Publication Order Number:
NB6N14S/D
NB6N14S
Q0
Q0
VCC GND
16
15
14
Exposed Pad (EP)
13
Table 1. TRUTH TABLE
Q1
1
12 IN
Q1
2
11 VT
Q2
3
10 VREF_AC
Q2
4
9
NB6N14S
IN
IN
IN
EN
Q
Q
0
1
1
0
1
1
0
1
1
0
x
x
0
0 (Note 1)
1 (Note 1)
1. On next transition of the input signal (IN).
5
6
7
Q3
Q3
VCC
8
EN
Figure 3. NB6N14S Pinout, 16−pin QFN (Top View)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
Q1
LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2
Q1
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
3
Q2
LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4
Q2
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5
Q3
LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
6
Q3
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
7
VCC
−
8
EN
LVTTL / LVCMOS Input
9
IN
LVPECL, CML, LVDS
10
VREF_AC
LVPECL Output
The VREF_AC reference output can be used to rebias capacitor−coupled
differential or single−ended input signals. For the capacitor−coupled IN and/or
INb inputs, VREF_AC should be connected to the VT pin and bypassed to
ground with a 0.01 mF capacitor.
Internal 100 W Center−tapped Termination Pin for IN and IN
Positive Supply Voltage.
Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb
outputs will go HIGH on the next negative transition of IN input. The internal
DFF register is clocked on the falling edge of IN input; see Figure 23. The EN
pin has an internal pullup resistor and defaults HIGH when left open.
Inverted Differential Input
11
VT
LVPECL Output
12
IN
LVPECL, CML, LVDS
13
GND
−
Negative Supply Voltage.
14
VCC
−
Positive Supply Voltage.
15
Q0
LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
16
Q0
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
−
EP
−
Non−inverted Differential Input. (Note 2)
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is not electrically connected to the
die, but is recommended to be electrically and thermally connected to GND on
the PC board.
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied
on IN/IN inputs, then the device will be susceptible to self−oscillation.
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2
NB6N14S
Table 3. ATTRIBUTES
Characteristics
Value
Moisture Sensitivity (Note 3)
Flammability Rating
ESD Protection
Level 1
Oxygen Index: 28 to 34
Human Body Model
Machine Model
EN Input Pullup Resistor − RPU
UL 94 V−0 @ 0.125 in
> 2 kV
> 200 V
37 kW
Transistor Count
225
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
VCC
Positive Power Supply
GND = 0 V
VIN
Positive Input
GND = 0 V
IIN
Input Current Through RT (50 W Resistor)
Static
Surge
IOSC
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
TIA/EIA − 644 Compliant
Q or Q
Q to Q to GND
IREF_AC
VREF_AC Sink/Source Current
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient) (Note 4)
0 lfpm
500 lfpm
qJC
Thermal Resistance (Junction−to−Case)
1S2P (Note 4)
Tsol
Wave Solder
Condition 2
VIN ≤ VCC
Continuous
Continuous
QFN−16
Pb−Free
Rating
Unit
3.8
V
3.8
V
35
70
mA
mA
12
24
mA
"0.5
mA
−40 to +85
°C
−65 to +150
°C
QFN−16
QFN−16
41.6
35.2
°C/W
°C/W
QFN−16
4.0
°C/W
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB6N14S
Table 5. DC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
Symbol
ICC
Characteristic
Min
Power Supply Current (Note 9)
Typ
Max
Unit
65
100
mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 14, 15, 19, and 21)
Vth
Input Threshold Reference Voltage Range (Note 8)
GND +100
VCC − 100
mV
VIH
Single−ended Input HIGH Voltage
Vth + 100
VCC
mV
VIL
Single−ended Input LOW Voltage
GND
Vth − 100
mV
VREF_AC
Reference Output Voltage (Note 11)
VCC − 1.300
V
VCC − 1.600
VCC − 1.425
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 10, 11, 12, 13, 20, and 22)
VIHD
Differential Input HIGH Voltage
100
VCC
mV
VILD
Differential Input LOW Voltage
GND
VCC − 100
mV
VCMR
Input Common Mode Range (Differential Configuration)
GND + 50
VCC − 50
mV
VID
Differential Input Voltage (VIHD − VILD)
100
VCC
mV
RTIN
Internal Input Termination Resistor
40
60
W
450
mV
25
mV
1375
mV
1
25
mV
1425
1600
mV
50
LVDS OUTPUTS (Note 5)
VOD
Differential Output Voltage
250
DVOD
Change in Magnitude of VOD for Complementary Output States
(Note 10)
VOS
Offset Voltage (Figure 18)
DVOS
Change in Magnitude of VOS for Complementary Output States
(Note 10)
VOH
Output HIGH Voltage (Note 6)
VOL
Output LOW Voltage (Note 7)
0
1
1125
0
900
1075
mV
LVTTL/LVCMOS INPUTS
VIH
Input HIGH Voltage (Note 7, 8)
2.0
VCC
V
VIL
Input LOW Voltage (Note 7, 8)
GND
0.8
V
IIH
Input HIGH Current
−150
150
mA
IIL
Input LOW Current
−150
150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 17.
6. VOHmax = VOSmax + ½ VODmax.
7. VOLmax = VOSmin − ½ VODmax.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. Input termination pins open, D/D at the DC level within VCMR and output pins loaded with RL = 100 W across differential.
10. Parameter guaranteed by design verification not tested in production.
11. VREF_AC used to rebias capacitor−coupled inputs only (see Figures 14 and 15).
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4
NB6N14S
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 12)
−40°C
Min
Characteristic
Symbol
Typ
25°C
Max
Min
85°C
Typ
Max
Typ
Max
Maximum Input Clock Frequency
2.0
VOUTPP
Output Voltage Amplitude (@ VINPPmin) fin ≤ 1.0 GHz
(Figure 4)
fin= 1.5 GHz
fin= 2.0 GHz
220
200
170
350
300
270
220
200
170
350
300
270
220
200
170
350
300
270
mV
fDATA
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
Gb/s
tPLH,
tPHL
Differential Input to Differential Output
Propagation Delay
300
450
300
450
300
450
ts
th
Setup Time
Hold Time
300
500
60
70
300
500
60
70
300
500
60
70
tSKEW
Within Device Skew (Note 17)
Device−to−Device Skew (Note 16)
5
30
20
200
5
30
20
200
tJITTER
RMS Random Clock Jitter (Note 14)
0.5
0.5
6.0
7.0
10
1.0
1.0
20
20
20
0.5
0.5
6.0
7.0
10
1.0
1.0
20
20
20
Deterministic Jitter (Note 15)
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 13)
tr
tf
Output Rise/Fall Times @ 250 MHz
(20% − 80%)
100
Q, Q
60
120
600
VCC−
GND
100
190
60
2.0
Unit
finMax
fin = 1.0 GHz
fin = 1.5 GHz
fDATA = 622 Mb/s
fDATA = 1.5 Gb/s
fDATA = 2.488 Gb/s
2.0
Min
600
VCC−
GND
100
190
60
120
GHz
600
ps
5
30
20
200
ps
0.5
0.5
6.0
7.0
10
1.0
1.0
20
20
20
ps
VCC−
GND
mV
190
ps
120
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W. Input
edge rates 150 ps (20%−80%). See Figure 17.
13. Input voltage swing is a single−ended measurement operating in differential mode.
14. RMS jitter with 50% Duty Cycle clock signal at 750 MHz.
15. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5.
16. Skew is measured between outputs under identical transition @ 250 MHz.
17. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
OUTPUT VOLTAGE AMPLITUDE (mV)
400
350
300
−40°C
250
85°C
200
25°C
150
100
50
0
0
0.5
1
1.5
2
2.5
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
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5
3
NB6N14S
Figure 5. Typical Phase Noise Plot at
fcarrier = 156.25 MHz
Figure 6. Typical Phase Noise Plot at
fcarrier = 622.08 MHz
Figure 7. Typical Phase Noise Plot at
fcarrier = 1 GHz
Figure 8. Typical Phase Noise Plot at
fcarrier = 1.5 GHz
The above phase noise plots captured using Agilent
E5052A show additive phase noise of the NB6N14S device
at frequencies 156.25 MHz, 622.08 MHz, 1 GHz and
1.5 GHz respectively at an operating voltage of 3.3 V in
room temperature. The RMS Phase Jitter contributed by the
device (integrated between 12 kHz and 20 MHz; as shown
in the shaded region of the plot) at each of the frequencies
is 182 fs, 31 fs, 20 fs and 15 fs respectively. The input source
used for the phase noise measurements is Agilent E8663B.
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6
VOLTAGE (63.23 mV/div)
NB6N14S
Device DDJ = 10 ps
TIME (58 ps/div)
Figure 9. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 and OC48 mask
(VINPP = 100 mV; Input Signal DDJ = 14 ps)
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7
NB6N14S
VCC
VCC
VCC
Zo = 50 W
LVPECL
Driver
VT = VCC − 2.0 V
NB6N14S
CLK
Zo = 50 W
50 W
LVDS
Driver
VEE
50 W
VEE
Figure 11. LVDS Interface
VCC
VCC
NB6N14S
CLK
VCC
Zo = 50 W
50 W
CML
Driver
50 W
VEE
50 W
VEE
Figure 13. Standard 50 W Load HSTL Interface
VCC
VCC
VCC
NB6N14S
CLK
Zo = 50 W
50 W
Differential
Driver
VEE
NB6N14S
CLK
50 W
Single−Ended
Driver
VT = VREF_AC
50 W
Zo = 50 W
CLK
VEE
Figure 12. Standard 50 W Load CML Interface
Zo = 50 W
VT =VEE
Zo = 50 W
CLK
VEE
VCC
NB6N14S
CLK
50 W
HSTL
Driver
VT = VCC
Zo = 50 W
CLK
VEE
Figure 10. LVPECL Interface
Zo = 50 W
VT = OPEN
Zo = 50 W
CLK
VEE
VCC
NB6N14S
CLK
50 W
50 W
Zo = 50 W
VCC
CLK
VT = VREF_AC
50 W
CLK
VEE
VEE
Figure 14. Capacitor−Coupled Differential
Interface (VT Connected to VREF_AC)
VEE
Figure 15. Capacitor−Coupled Single−Ended
Interface (VT Connected to VREF_AC)
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8
NB6N14S
D
VINPP = VIH(D) − VIL(D)
D
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 16. AC Reference Measurement
Q
LVDS
Driver
Device
Zo = 50 W
HI Z Probe
D
Oscilloscope
100 W
Q
Zo = 50 W
D
HI Z Probe
Figure 17. Typical LVDS Termination for Output Driver and Device Evaluation
QN
VOH
VOS
VOD
VOL
QN
Figure 18. LVDS Output
IN
VIH
IN
Vth
VIL
Vth
IN
IN
Figure 19. Differential Input Driven
Single−Ended
Figure 20. Differential Inputs Driven
Differentially
VCC
VCC
VIHmax
Vthmax
IN
VIL
VILmax
VCMR
Vth
Vthmin
GND
VIH(MAX)
VIH
VINPP = VIHD − VILD
VIL
VIHmin
IN
VIH
VILmin
GND
Figure 21. Vth Diagram
VIL(MIN)
Figure 22. VCMR Diagram
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9
NB6N14S
EN
VCC/2
tS
/IN
IN
VCC/2
tH
VINPP
tpd
/Q
VOUTPP
Q
Figure 23. EN Timing Diagram
ORDERING INFORMATION
Package
Shipping†
NB6N14SMNG
QFN−16, 3 X 3 mm
(Pb−Free)
123 Units / Rail
NB6N14SMNR2G
QFN−16, 3 X 3 mm
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
AnyLevel and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC).
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE G
1
SCALE 2:1
DATE 08 OCT 2021
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON04795D
QFN16 3X3, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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