NB6N11SMNG

NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB6N11S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The NB6N11S has a wide input common mode range from GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB6N11S is ideal for translating a variety of differential or single−ended Clock or Data signals to 350 mV typical LVDS output levels. The NB6N11S is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices and is offered in a small, 3 mm X 3 mm, 16−QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB6N11S is a member of the ECLinPS MAX™ family of high performance products. Features • • • • • • • • Maximum Input Clock Frequency > 2.0 GHz Maximum Input Data Rate > 2.5 Gb/s 1 ps Maximum of RMS Clock Jitter Typically 10 ps of Data Dependent Jitter 380 ps Typical Propagation Delay 120 ps Typical Rise and Fall Times Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and SG Devices These are Pb−Free Devices www.onsemi.com MARKING DIAGRAM* 16 1 1 QFN−16 MN SUFFIX CASE 485G A L Y W G NB6N 11S ALYW G G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Q0 VTD Q0 D D VTD Q1 VOLTAGE (130 mV/div) Q1 Figure 1. Logic Diagram ORDERING INFORMATION Device DDJ = 10 ps See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. TIME (58 ps/div) Figure 2. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps) © Semiconductor Components Industries, LLC, 2014 November, 2014 − Rev. 7 1 Publication Order Number: NB6N11S/D NB6N11S Exposed Pad (EP) VCC VCC VCC VCC 16 Q0 1 Q0 2 15 14 13 12 VTD 11 D NB6N11S Q1 3 10 D Q1 4 9 5 6 7 VCC NC VEE VTD 8 VEE Figure 3. NB6N11S Pinout, 16−pin QFN (Top View) Table 1. PIN DESCRIPTION Pin Name I/O 1 Q0 LVDS Output Non−inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. 2 Q0 LVDS Output Inverted D output. Typically loaded with 10 W receiver termination resistor across differential pair. 3 Q1 LVDS Output Non−inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. 4 Q1 LVDS Output Inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. 5 VCC − 6 NC No Connect 7 VEE Negative Supply Voltage 8 VEE 9 VTD − 10 D LVPECL, CML, LVDS, LVCMOS, LVTTL Inverted Differential Clock/Data Input (Note 1) 11 D LVPECL, CML, LVDS, LVCMOS, LVTTL Non−inverted Differential Clock/Data Input (Note 1) 12 VTD − Internal 50 W termination pin for D 13 VCC − Positive Supply Voltage 14 VCC − Positive Supply Voltage 15 VCC − Positive Supply Voltage 16 VCC − Positive Supply Voltage EP Description Positive Supply Voltage Negative Supply Voltage Internal 50 W termination pin for D Exposed pad. The exposed pad (EP) on the package bottom must be attached to a heat−sinking conduit. The exposed pad may only be electrically connected to VEE. 1. In the differential configuration when the input termination pins (VTD/VTD) are connected to a common termination voltage or left open, and if no signal is applied on D/D inputs, then the device will be susceptible to self oscillation. www.onsemi.com 2 NB6N11S Table 2. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) QFN−16 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 200 V > 1 kV Pb Pkg Pb−Free Pkg − 1 UL 94 V−0 @ 0.125 in 225 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 3.8 V 3.8 V 35 70 mA mA VCC Positive Power Supply GND = 0 V VIN Positive Input GND = 0 V IIN Input Current Through RT (50 W Resistor) Static Surge IOSC Output Short Circuit Current Line−to−Line (Q to Q) Line−to−End (Q or Q to GND) Q or Q Q to Q to GND TA Operating Temperature Range QFN−16 Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm QFN−16 QFN−16 41.6 35.2 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 3) QFN−16 4.0 °C/W Tsol Wave Solder 265 265 °C VIN ≤ VCC mA Pb Pb−Free Continuous Continuous 12 24 −40 to +85 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad. www.onsemi.com 3 NB6N11S Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C Symbol ICC Characteristic Min Power Supply Current (Note 8) Typ Max Unit 35 50 mA DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 15, 16, 20, and 22) Vth Input Threshold Reference Voltage Range (Note 7) GND +100 VCC − 100 mV VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV VIL Single−ended Input LOW Voltage GND Vth − 100 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 12, 13, 14, 21, and 23) VIHD Differential Input HIGH Voltage 100 VCC mV VILD Differential Input LOW Voltage GND VCC − 100 mV VCMR Input Common Mode Range (Differential Configuration) GND + 50 VCC − 50 mV VID Differential Input Voltage (VIHD − VILD) 100 VCC mV RTIN Internal Input Termination Resistor 40 60 W 450 mV 25 mV 1375 mV 1 25 mV 1425 1600 mV 50 LVDS OUTPUTS (Note 4) VOD Differential Output Voltage 250 DVOD Change in Magnitude of VOD for Complementary Output States (Note 9) VOS Offset Voltage (Figure 19) DVOS Change in Magnitude of VOS for Complementary Output States (Note 9) VOH Output HIGH Voltage (Note 5) VOL Output LOW Voltage (Note 6) 0 1 1125 0 900 1075 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 18. 5. VOHmax = VOSmax + ½ VODmax. 6. VOLmax = VOSmin − ½ VODmax. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. Input termination pins open, D/D at the DC level within VCMR and output pins loaded with RL = 100 W across differential. 9. Parameter guaranteed by design verification not tested in production. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 4 NB6N11S Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 10) −40°C Characteristic Symbol fin ≤ 1.0 GHz fin= 1.5 GHz fin= 2.0 GHz Min Typ 220 200 170 350 300 270 25°C Max VOUTPP Output Voltage Amplitude (@ VINPPmin) (Figure 4) fDATA Maximum Operating Data Rate 1.5 2.5 tPLH, tPHL Differential Input to Differential Output Propagation Delay 270 370 470 tSKEW Duty Cycle Skew (Note 11) Within Device Skew (Note 16) Device−to−Device Skew (Note 15) 8 5 30 tJITTER RMS Random Clock Jitter (Note 13) 0.5 0.5 6 7 10 Deterministic Jitter (Note 14) fin = 1.0 GHz fin = 1.5 GHz fDATA = 622 Mb/s fDATA = 1.5 Gb/s fDATA = 2.488 Gb/s VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 12) tr tf Output Rise/Fall Times @ 250 MHz (20% − 80%) 100 Q, Q 70 120 Min Typ 250 200 170 350 300 270 85°C Max 1.5 2.5 270 370 470 45 25 100 8 5 30 1 1 0.5 0.5 6 7 10 20 20 VCC− GND 100 170 70 Min Typ 250 200 170 350 300 270 Unit mV 1.5 2.5 270 370 470 ps 45 25 100 8 5 30 45 25 100 ps 1 1 0.5 0.5 6 7 10 1 1 20 20 VCC− GND 100 170 70 120 Max 120 Gb/s ps 20 20 VCC− GND mV 170 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W across “D” and “D” of the receiver. Input edge rates 150 ps (20%−80%). 11. See Figure 17 differential measurement of tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform @ 250 MHz. 12. Input voltage swing is a single−ended measurement operating in differential mode. 13. RMS jitter with 50% Duty Cycle clock signal at 750 MHz. 14. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5. 15. Skew is measured between outputs under identical transition @ 250 MHz. 16. The worst case condition between Q0/Q0 and Q1/Q1 from D, D, when both outputs have the same transition. OUTPUT VOLTAGE AMPLITUDE (mV) 400 350 300 −40°C 250 85°C 200 25°C 150 100 50 0 0 0.5 1 1.5 2 2.5 INPUT CLOCK FREQUENCY (GHz) Figure 4. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V) www.onsemi.com 5 3 NB6N11S Figure 5. Typical Phase Noise Plot at fcarrier = 311.04 MHz Figure 6. Typical Phase Noise Plot at fcarrier = 622.08 MHz Figure 7. Typical Phase Noise Plot at fcarrier = 1.5 GHz Figure 8. Typical Phase Noise Plot at fcarrier = 2 GHz The above phase noise plots captured using Agilent E5052A show additive phase noise of the NB6N11S device at frequencies 311.04 MHz, 622.08 MHz, 1.5 GHz and 2 GHz respectively at an operating voltage of 3.3 V in room temperature. The RMS Phase Jitter contributed by the device (integrated between 12 kHz and 20 MHz; as shown in the shaded region of the plot) at each of the frequencies is 96 fs, 40 fs, 15 fs and 14 fs respectively. The input source used for the phase noise measurements is Agilent E8663B. www.onsemi.com 6 VOLTAGE (63.23 mV/div) NB6N11S Device DDJ = 10 ps TIME (58 ps/div) Figure 9. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 and OC48 mask (VINPP = 100 mV; Input Signal DDJ = 14 ps) RC RC 1.25 kW 1.25 kW Dx 50 W 1.25 kW 1.25 kW I VTDx VTDx 50 W Dx Figure 10. Input Structure www.onsemi.com 7 NB6N11S VCC VCC VCC NB6N11S D Zo = 50 W VCC Zo = 50 W NB6N11S D 50 W* LVPECL Driver 50 W* VTD VTD 50 W* Zo = 50 W VTD LVDS Driver VTD Zo = 50 W D 50 W* D VTD = VTD VTD = VTD = VCC − 2.0 V GND GND GND Figure 11. LVPECL Interface Figure 12. LVDS Interface VCC VCC CML Driver VCC VCC NB6N11S D Zo = 50 W VCC VTD GND Zo = 50 W 50 W* VTD 50 W* VTD = VTD = VCC GND GND Figure 13. Standard 50 W Load CML Interface VTD = VTD = GND or VDD/2 Depending on Driver. 50 W* 50 W* 50 W* VTD D 50 W* D 1.5 kW GND GND NB6N11S D VTD LVTTL Driver 2.5 kW GND GND VCC Zo = 50 W VTD VTD D VCC NB6N11S D Zo = 50 W 50 W* Figure 14. HSTL Interface VCC VCC VTD Zo = 50 W D GND VTD HSTL Driver 50 W* Zo = 50 W LVCMOS Driver NB6N11S D GND GND VTD = VTD = OPEN VTD = VTD = OPEN Figure 15. LVCMOS Interface Figure 16. LVTTL Interface *RTIN, Internal Input Termination Resistor. www.onsemi.com 8 GND NB6N11S D VINPP = VIH(D) − VIL(D) D Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 17. AC Reference Measurement Zo = 50 W Q LVDS Driver Device HI Z Probe D 100 W Zo = 50 W Q Oscilloscope D HI Z Probe Figure 18. Typical LVDS Termination for Output Driver and Device Evaluation QN VOH VOS VOD VOL QN Figure 19. LVDS Output D D VIH Vth VIL D D Vth Figure 20. Differential Input Driven Single−Ended Figure 21. Differential Inputs Driven Differentially VCC VCC VIH(MAX) VIHmax Vthmax D VIL VILmax VIH VINPP = VIHD − VILD VCMR Vth VIL VIHmin Vthmin D GND VIH VILmin VIL(MIN) GND Figure 22. Vth Diagram Figure 23. VCMR Diagram ORDERING INFORMATION Package Shipping† NB6N11SMNG QFN−16, 3 X 3 mm (Pb−Free) 123 Units / Rail NB6N11SMNR2G QFN−16, 3 X 3 mm (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. AnyLevel and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC). www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE G 1 SCALE 2:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON04795D QFN16 3X3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative