NCP1031

NCP1030, NCP1031 Low Power PWM Controller with On−Chip Power Switch and Startup Circuits for 48 V Telecom Systems The NCP1030 and NCP1031 are a family of miniature high−voltage monolithic switching regulators with on−chip Power Switch and Startup Circuits. The NCP103x family incorporates in a single IC all the active power, control logic and protection circuitry required to implement, with minimal external components, several switching regulator applications, such as a secondary side bias supply or a low power dc−dc converter. This controller family is ideally suited for 48 V telecom, 42 V automotive and 12 V input applications. The NCP103x can be configured in any single−ended topology such as forward or flyback. The NCP1030 is targeted for applications requiring up to 3 W, and the NCP1031 is targeted for applications requiring up to 6 W. The internal error amplifier allows the NCP103x family to be easily configured for secondary or primary side regulation operation in isolated and non−isolated configurations. The fixed frequency oscillator is optimized for operation up to 1 MHz and is capable of external frequency synchronization, providing additional design flexibility. In addition, the NCP103x incorporates individual line undervoltage and overvoltage detectors, cycle by cycle current limit and thermal shutdown to protect the controller under fault conditions. The preset current limit thresholds eliminate the need for external sensing components. Features http://onsemi.com MARKING DIAGRAMS 8 8 1 Micro8t DM SUFFIX CASE 846A 1 8 8 1 SO−8 D SUFFIX CASE 751 1 N1031 ALYW 1030 AYW 1030/N1031 A L Y W = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week • • • • • • • • • • • • • • • On Chip High 200 V Power Switch Circuit and Startup Circuit Internal Startup Regulator with Auxiliary Winding Override Operation up to 1 MHz External Frequency Synchronization Capability Frequency Fold−down Under Fault Conditions Trimmed ± 2% Internal Reference Line Undervoltage and Overvoltage Detectors Cycle by Cycle Current Limit Using SENSEFETt Active LEB Circuit Overtemperature Protection Internal Error Amplifier PIN CONNECTIONS 1 GND CT VFB COMP (Top View) 2 3 4 8 7 6 5 OV VDRAIN VCC UV ORDERING INFORMATION Device NCP1030DMR2 NCP1031DR2 Package Micro8t SO−8 Shipping† 4000/Tape & Reel 2500/Tape & Reel Typical Applications Secondary Side Bias Supply for Isolated dc−dc Converters Stand Alone Low Power dc−dc Converter Low Power Bias Supply Low Power Boost Converter †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2004 1 August, 2004 − Rev. 4 Publication Order Number: NCP1030/D NCP1030, NCP1031 GND RSENSE Disable Internal Bias I1 CT Ramp Current Limit Comparator + − LEB + 7.5 V/10 V − − + Thermal Shutdown S Reset Dominant Q Latch R ISTART VDRAIN VCC 16 V + 10 V + − − + 6.5 V − UV CT 10 V + 3.0 V/3.5 V − I2 = 3I1 One Shot Pulse O + 50 mV − I VFB Error Amplifier − + − + S Reset Q Dominant R Latch PWM Latch 10 V + 2.5 V − COMP 2 kW 10 V PWM Comparator 10 V 4.5 V Figure 1. NCP1030/31 Functional Block Diagram FUNCTIONAL PIN DESCRIPTION Pin 1 2 Name GND CT Function Ground Oscillator Frequency Selection Ground reference pin for the circuit. An external capacitor connected to this pin sets the oscillator frequency up to 1 MHz. The oscillator can be synchronized to a higher frequency by charging or discharging CT to trip the internal 3.0 V/3.5 V comparator. If a fault condition exists, the power switch is disabled and the frequency is reduced by a factor of 7. The regulated voltage is scaled down to 2.5 V by means of a resistor divider. Regulation is achieved by comparing the scaled voltage to an internal 2.5 V reference. Requires external compensation network between COMP and VFB pins. This pin is effectively grounded if faults are present. Line voltage (Vin) is scaled down using an external resistor divider such that the OV voltage reaches 2.5 V when line voltage reaches its maximum operating voltage. Line voltage is scaled down using an external resistor divider such that the UV voltage reaches 2.5 V when line voltage reaches its minimum operating voltage. This pin is connected to an external capacitor for energy storage. During Turn−On, the startup circuit sources current to charge the capacitor connected to this pin. When the supply voltage reaches VCC(on), the startup circuit turns OFF and the power switch is enabled if no faults are present. An external winding is used to supply power after initial startup to reduce power dissipation. VCC should not exceed 16 V. This pin directly connects the Power Switch and Startup Circuits to one of the transformer windings. The internal High Voltage Power Switch Circuit is connected between this pin and ground. VDRAIN should not exceed 200 V. Description 3 4 5 6 7 VFB COMP OV UV VCC Feedback Input Error Amplifier Compensation Line Overvoltage Shutdown Line Undervoltage Shutdown Supply Voltage 8 VDRAIN Power Switch and Startup Circuits http://onsemi.com 2 + − + − + 2.5 V − OV 10 V NCP1030, NCP1031 COMP Voltage CT Ramp CT Charge Signal PWM Comparator Output PWM Latch Output Power Switch Circuit Gate Drive Current Limit Threshold Normal PWM Operating Range Output Overload Current Limit Propagation Delay Leading Edge Blanking Output Figure 2. Pulse Width Modulation Timing Diagram VCC(on) VCC(off) VCC(reset) 0V ISTART 0 mA 3.0 V VUV 0V 2.5 V VFB 0V VDRAIN 0V Power−up & standby Operation Normal Operation Output Overload Figure 3. Auxiliary Winding Operation with Output Overload Timing Diagram http://onsemi.com 3 NCP1030, NCP1031 MAXIMUM RATINGS Rating Power Switch and Startup Circuits Voltage Power Switch and Startup Circuits Input Current − NCP1030 − NCP1031 VCC Voltage Range All Other Inputs/Outputs Voltage Range VCC and All Other Inputs/Outputs Current Operating Junction Temperature Storage Temperature Power Dissipation (TJ = 25°C, 2.0 Oz., 1.0 Sq Inch Printed Circuit Copper Clad) DM Suffix, Plastic Package Case 846A D Suffix, Plastic Package Case 751 Thermal Resistance, Junction to Air (2.0 Oz. Printed Circuit Copper Clad) DM Suffix, Plastic Package Case 846A 0.36 Sq. Inch 1.0 Sq. Inch D Suffix, Plastic Package Case 751 0.36 Sq. Inch 1.0 Sq. Inch RqJA 181 162 135 117 Symbol VDRAIN IDRAIN 1.0 2.0 VCC VIO IIO TJ Tstg −0.3 to 16 −0.3 to 10 100 −40 to 125 −55 to 150 0.69 0.93 °C/W V V mA °C °C W Value −0.3 to 200 Unit V A Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. A. This device contains ESD protection circuitry and exceeds the following tests: Pins 1−7: Human Body Model 2000V per MIL−STD−883, Method 3015. Pins 1−7: Machine Model Method 200 V. Pin 8 is connected to the High Voltage Startup and Power Switch Circuits and rated only to the maximum voltage rating of the part, or 200 V. B. This device contains Latchup protection and exceeds $100 mA per JEDEC Standard JESD78. http://onsemi.com 4 NCP1030, NCP1031 DC ELECTRICAL CHARACTERISTICS (VDRAIN = 48 V, VCC = 12 V, CT = 560 pF, VUV = 3 V, VOV = 2 V, VFB = 2.3 V, VCOMP = 2.5 V, TJ = −40°C to 125°C, typical values shown are for TJ = 25°C unless otherwise noted.) (Note 1) Characteristics STARTUP CONTROL Startup Circuit Output Current (VFB = VCOMP) NCP1030 TJ = 25°C VCC = 0 V VCC = VCC(on) − 0.2 V TJ = −40°C to 125°C VCC = 0 V VCC = VCC(on) − 0.2 V NCP1031 TJ = 25°C VCC = 0 V VCC = VCC(on) − 0.2 V TJ = −40°C to 125°C VCC = 0 V VCC = VCC(on) − 0.2 V VCC Supply Monitor (VFB = 2.7 V) Startup Threshold Voltage (VCC Increasing) Minimum Operating VCC After Turn−on (VCC Increasing) Hysteresis Voltage Undervoltage Lockout Threshold Voltage, VCC Decreasing (VFB = VCOMP) Minimum Startup Voltage (Pin 8) ISTART = 0.5 mA, VCC =VCC(on) − 0.2 V ERROR AMPLIFIER Reference Voltage (VCOMP = VFB, Follower Mode) TJ = 25°C TJ = −40°C to 125°C Line Regulation (VCC = 8 V to 16 V, TJ = 25°C) Input Bias Current (VFB = 2.3 V) COMP Source Current COMP Sink Current (VFB = 2.7 V) COMP Maximum Voltage (ISRC = 0 mA) COMP Minimum Voltage (ISNK = 0 mA, VFB = 2.7 V) Open Loop Voltage Gain Gain Bandwidth Product LINE UNDER/OVERVOLTAGE DETECTOR Undervoltage Lockout (VFB = VCOMP) Voltage Threshold (Vin Increasing) Voltage Hysteresis Input Bias Current Overvoltage Lockout (VFB = VCOMP) Voltage Threshold (Vin Increasing) Voltage Hysteresis Input Bias Current VUV VUV(hys) IUV VOV VOV(hys) IOV 2.400 0.075 − 2.400 0.075 − 2.550 0.175 0 2.550 0.175 0 2.700 0.275 1.0 2.700 0.275 1.0 V V mA V V mA VREF 2.45 2.40 REGLINE IVFB ISRC ISNK VC(max) VC(min) AVOL GBW − − 80 200 4.5 − − − 2.5 2.5 1.0 0.1 110 550 − − 80 1.0 2.55 2.60 5.0 1.0 140 900 − 1.0 − − mV mA mA mA V V dB MHz V ISTART 10 6.0 8.0 2.0 12.5 8.6 − − 15 12 16 13 mA Symbol Min Typ Max Unit 13 8.0 11 4.0 VCC(on) VCC(off) VCC(hys) VCC(reset) VSTART(min) − 9.6 7.0 − 6.0 16 12 − − 10.2 7.6 2.6 6.6 16.8 19 16 21 18 V 10.6 8.0 − 7.0 18.5 V V 1. Production testing for NCP1030DMR2 is performed at 25°C only; limits at −40°C and 125°C are guaranteed by design. http://onsemi.com 5 NCP1030, NCP1031 DC ELECTRICAL CHARACTERISTICS (VDRAIN = 48 V, VCC = 12 V, CT = 560 pF, VUV = 3 V, VOV = 2 V, VFB = 2.3 V, VCOMP = 2.5 V, TJ = −40°C to 125°C, typical values shown are for TJ = 25°C unless otherwise noted.) (Note 2) Characteristics OSCILLATOR Frequency (CT = 560 pF, Note 3) TJ = 25°C TJ = −40°C to 125°C Frequency (CT = 100 pF) Charge Current (VCT = 3.25 V) Discharge Current (VCT = 3.25 V) Oscillator Ramp Peak Valley PWM COMPARATOR Maximum Duty Cycle POWER SWITCH CIRCUIT Power Switch Circuit On−State Resistance (ID = 100 mA) NCP1030 TJ = 25°C TJ = 125°C NCP1031 TJ = 25°C TJ = 125°C Power Switch Circuit and Startup Circuit Breakdown Voltage (ID = 100 mA, TJ = 25°C) Power Switch Circuit and Startup Circuit Off−State Leakage Current (VDRAIN = 200 V, VUV = 2.0 V) TJ = 25°C TJ = −40 to 125°C Switching Characteristics (VDS = 48 V, RL = 100 W) Rise Time Fall Time CURRENT LIMIT AND OVER TEMPERATURE PROTECTION Current Limit Threshold (TJ = 25°C) NCP1030 (di/dt = 0.5 A/ms) NCP1031 (di/dt = 1.0 A/ms) Propagation Delay, Current Limit Threshold to Power Switch Circuit Output (Leading Edge Blanking plus Current Limit Delay) Thermal Protection (Note 4) Shutdown Threshold (TJ Increasing) Hysteresis TOTAL DEVICE Supply Current After UV Turn−On Power Switch Enabled Power Switch Disabled Non−Fault condition (VFB = 2.7 V) Fault Condition (VFB = 2.7 V, VUV = 2.0 V) mA ICC1 ICC2 ICC3 2.0 − − 3.0 1.5 0.65 4.0 2.0 1.2 ILIM 350 700 tPLH − TSHDN THYS 125 − 100 150 45 − °C − − 515 1050 680 1360 ns mA RDS(on) − − − − V(BR)DS 200 IDS(off) − − tr tf − − 13 − 22 24 25 50 ns − − − − mA 4.1 6.0 2.1 3.5 7.0 12 3.0 6.0 V W DCMAX 70 75 80 % fOSC1 275 260 fOSC2 ICT(C) ICT(D) Vrpk Vrvly − − − Symbol Min Typ Max Unit kHz 300 − 800 215 645 3.5 3.0 325 325 − − − − − kHz mA mA V − − 2. Production testing for NCP1030DMR2 is performed at 25°C only; limits at −40°C and 125°C are guaranteed by design. 3. Oscillator frequency can be externally synchronized to the maximum frequency of the device. 4. Guaranteed by design only. http://onsemi.com 6 NCP1030, NCP1031 TYPICAL CHARACTERISTICS 13.0 ISTART, STARTUP CURRENT (mA) 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 0 2 4 6 8 10 VCC, SUPPLY VOLTAGE (V) ISTART, STARTUP CURRENT (mA) NCP1030 VDRAIN = 48 V TJ = 25°C 20 19 18 17 16 15 14 13 12 11 10 0 2 4 6 8 10 VCC, SUPPLY VOLTAGE (V) NCP1031 VDRAIN = 48 V TJ = 25°C Figure 4. NCP1030 Startup Current vs. Supply Voltage 20 ISTART, STARTUP CURRENT (mA) 18 16 14 12 10 8 6 4 2 0 −50 −25 0 25 50 75 100 125 150 VCC = VCC(on) − 0.2 V VCC = 0 V ISTART, STARTUP CURRENT (mA) NCP1030 VDRAIN = 48 V 20 18 16 14 12 10 8 6 4 2 Figure 5. NCP1031 Startup Current vs. Supply Voltage VCC = 0 V NCP1031 VDRAIN = 48 V VCC = VCC(on) − 0.2 V 0 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 6. NCP1030 Startup Current vs. Junction Temperature 12 ISTART, STARTUP CURRENT (mA) ISTART, STARTUP CURRENT (mA) NCP1030 10 8 6 TJ = 125°C 4 2 VCC = VCC(on) − 0.2 V 0 0 25 50 75 100 125 150 175 200 VDRAIN, DRAIN VOLTAGE (V) TJ = −40°C TJ = 25°C 20 18 16 14 12 10 8 6 4 2 0 0 Figure 7. NCP1031 Startup Current vs. Junction Temperature NCP1031 TJ = −40°C TJ = 25°C TJ = 125°C VCC = VCC(on) − 0.2 V 25 50 75 100 125 150 175 200 VDRAIN, DRAIN VOLTAGE (V) Figure 8. NCP1030 Startup Current vs. Drain Voltage Figure 9. NCP1031 Startup Current vs. Drain Voltage http://onsemi.com 7 NCP1030, NCP1031 TYPICAL CHARACTERISTICS VCC(reset), UNDERVOLTAGE LOCKOUT THRESHOLD (V) 100 125 150 11.0 10.5 VCC, SUPPLY VOLTAGE (V) 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 −50 Minimum Operating Threshold Startup Threshold 6.80 6.75 6.70 6.65 6.60 6.55 6.50 6.45 6.40 6.35 6.30 −50 −25 0 25 50 75 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 10. Supply Voltage Thresholds vs. Junction Temperature VSTART(min), MINIMUM STARTUP VOLTAGE (V) 20.0 VREF, REFERENCE VOLTAGE (V) 19.5 19.0 18.5 18.0 17.5 17.0 16.5 16.0 15.5 15.0 −50 VCC = VCC(on) − 0.2 V ISTART = 0.5 mA 2.70 2.65 2.60 2.55 2.50 2.45 2.40 2.35 2.30 2.25 2.20 −50 Figure 11. Undervoltage Lockout Threshold vs. Junction Temperature VCC = 12 V −25 0 25 50 75 100 125 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 12. Minimum Startup Voltage vs. Junction Temperature ISRC, COMP SOURCE CURRENT (mA) 145 140 135 130 125 120 115 110 105 100 95 −50 −25 0 25 50 75 100 125 150 VCC = 12 V VCOMP = 2.5 V VFB = 2.3 V ISNK, COMP SINK CURRENT (mA) 840 790 740 690 640 590 540 490 440 390 340 −50 Figure 13. Reference Voltage vs. Junction Temperature VCC = 12 V VCOMP = 2.5 V VFB = 2.7 V −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 14. COMP Source Current vs. Junction Temperature Figure 15. COMP Sink Current vs. Junction Temperature http://onsemi.com 8 NCP1030, NCP1031 TYPICAL CHARACTERISTICS VUV/OV, LINE UNDER/OVERVOLTAGE THRESHOLDS (V) 2.600 2.575 2.550 2.525 2.500 2.475 2.450 2.425 2.400 2.375 2.350 −50 −25 0 25 50 75 100 125 150 VUV/OV(hys), UNDER/OVERVOLTAGE HYSTERESIS (mV) 220 210 200 190 180 170 160 150 140 130 120 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 TJ, JUNCTION TEMPERATURE (°C) Figure 16. Line Under/Overvoltage Thresholds vs. Junction Temperature 1100 1000 900 800 700 600 500 400 300 200 100 −50 Figure 17. Line Under/Overvoltage Hysteresis vs. Junction Temperature fOSC, OSCILLATOR FREQUENCY (kHz) 900 800 700 600 500 400 300 200 100 0 0 200 400 600 VCC = 12 V TJ = 25°C fOSC, OSCILLATOR FREQUENCY (kHz) 1000 VCC = 12 V CT = 47 pF CT = 220 pF CT = 1000 pF 800 1000 −25 0 25 50 75 100 125 150 CT, TIMING CAPACITOR (pF) TJ, JUNCTION TEMPERATURE (°C) Figure 18. Oscillator Frequency vs. Timing Capacitor 77.0 DCMAX, MAXIMUM DUTY CYCLE (%) RDS(on), POWER SWITCH CIRCUIT ON RESISTANCE (W) 76.5 76.0 75.5 75.0 74.5 74.0 73.5 73.0 72.5 72.0 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 fOSC = 1000 kHz VCC = 12 V fOSC = 200 kHz 8 7 6 5 4 3 2 1 0 −50 Figure 19. Oscillator Frequency vs. Junction Temperature VCC = 12 V ID = 100 mA NCP1030 NCP1031 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 Figure 20. Maximum Duty Cycle vs. Junction Temperature Figure 21. Power Switch Circuit On Resistance vs. Junction Temperature http://onsemi.com 9 NCP1030, NCP1031 TYPICAL CHARACTERISTICS 1000 COUT, OUTPUT CAPACITANCE (pF) IDS(off), POWER SWITCH AND STARTUP CIRCUITS LEAKAGE CURRENT (mA) 40 35 30 25 20 15 10 5 0 0 50 200 100 150 VDRAIN, DRAIN VOLTAGE (V) 250 300 TJ = −40°C TJ = 25°C TJ = 125°C VCC = 12 V NCP1031 100 NCP1030 10 0 40 80 120 160 200 VDRAIN, DRAIN VOLTAGE (V) Figure 22. Power Switch Circuit Output Capacitance vs. Drain Voltage 600 575 550 525 500 475 450 425 400 375 350 −50 −25 0 25 50 75 100 125 150 Current Slew Rate = 500 mA/ms NCP1030 1200 1150 1100 1050 1000 950 900 850 800 750 700 −50 Figure 23. Power Switch Circuit and Startup Circuit Leakage Current vs. Drain Voltage ILIM, CURRENT LIMIT THRESHOLD (mA) ILIM, CURRENT LIMIT THRESHOLD (mA) Current Slew Rate = 1 A/ms NCP1031 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 24. NCP1030 Current Limit Threshold vs. Junction Temperature ILIM, CURRENT LIMIT THRESHOLD (mA) ILIM, CURRENT LIMIT THRESHOLD (mA) 600 575 550 525 500 475 450 425 400 375 350 375 400 425 450 475 500 CURRENT SLEW RATE (mA/mS) TJ = 25°C NCP1030 1200 1150 1100 1050 1000 950 900 850 800 750 700 Figure 25. NCP1031 Current Limit Threshold vs. Junction Temperature TJ = 25°C NCP1031 750 800 850 900 950 1000 CURRENT SLEW RATE (mA/mS) Figure 26. NCP1030 Current Limit Threshold vs. Current Slew Rate Figure 27. NCP1031 Current Limit Threshold vs. Current Slew Rate http://onsemi.com 10 NCP1030, NCP1031 TYPICAL CHARACTERISTICS ICC1, OPERATING SUPPLY CURRENT (mA) 4.1 3.9 3.7 3.5 3.3 3.1 2.9 2.7 2.5 10 11 12 13 14 15 16 VCC, SUPPLY VOLTAGE (V) 4.0 ICC, SUPPLY CURRENT (mA) VDRAIN = 48 V TJ = 25°C CT = 560 pF 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 −50 −25 0 VUV = 2.0 V 25 50 75 100 125 150 VUV = 3.0 V, VFB = 2.7 V VUV = 3.0 V, VFB = 2.3 V VCC = 12 V CT = 560 pF TJ, JUNCTION TEMPERATURE (°C) Figure 28. Operating Supply Current vs. Supply Voltage Figure 29. Supply Current vs. Junction Temperature ICC, POWER SUPPLY CURRENT (mA) 10 9 8 7 6 5 4 3 2 200 300 400 500 NCP1030 NCP1031 TJ = 25 °C 600 700 800 900 1000 fOSC, OSCILLATOR FREQUENCY (kHz) Figure 30. Operating Supply Current vs. Oscillator Frequency http://onsemi.com 11 NCP1030, NCP1031 + Vin − + Vout − NCP103x GND VDRAIN CT VCC VFB UV COMP OV SECONDARY SIDE CONTROL VBIAS GND Figure 31. Secondary Side Bias Supply Configuration + Vin − VCC NCP103x GND VDRAIN VCC CT VFB UV COMP OV VCC + Vout − Figure 32. Boost Circuit Configuration http://onsemi.com 12 NCP1030, NCP1031 OPERATING DESCRIPTION Introduction Forward: CCC + OUT P cos −1 1 * DC@V @@N V N in S The NCP1030 and NCP1031 are a family of miniature monolithic voltage−mode switching regulators designed for isolated and non−isolated bias supply applications. The internal startup circuit and the MOSFET are rated at 200 V, making them ideal for 48 V telecom and 42 V automotive applications. In addition, the NCP103x family can operate from an existing 12 V supply. This controller family is optimized for operation up to 1 MHz. The NCP103x family incorporates in a single IC all the active power, control logic and protection circuitry required to implement, with a minimum of external components, several switching regulator applications, such as a secondary side bias supply or a low power dc−dc converter. The NCP1030 is available in the space saving Micro8t package and is targeted for applications requiring up to 3 W. The NCP1031 is targeted for applications up to 6 W and is available in the SO−8 package. The NCP103x includes an extensive set of features including over temperature protection, cycle by cycle current limit, individual line under and overvoltage detection comparators with hysteresis, and regulator output undervoltage lockout with hysteresis, providing full protection during fault conditions. A description of each of the functional blocks is given below, and the representative block diagram is shown in Figure 2. Startup Circuit and Undervoltage Lockout LOUTCOUT @ Ibias (eq. 1) 2.6 where, Ibias is the bias current supplied by the VCC capacitor including the IC bias current (ICC1) and any additional current used to bias the feedback resistors (if used). After initial startup, the VCC pin should be biased above VCC(off) using an auxiliary winding. This will prevent the startup regulator from turning ON and reduce power dissipation. Also, the load should not be directly connected to the VCC capacitor. Otherwise, the load may override the startup circuit. Figure 33 shows the recommended configuration for a non−isolated flyback converter. + Vin − + Vout − NCP103x GND VDRAIN CT VCC VFB UV COMP OV The NCP103x contains an internal 200 V startup regulator that eliminates the need for external startup components. The startup regulator consists of a constant current source that supplies current from the input line (Vin) to the capacitor on the VCC pin (CCC). Once the VCC voltage reaches approximately 10 V, the startup circuit is disabled and the Power Switch Circuit is enabled if no faults are present. During this self−bias mode, power to the NCP103x is supplied by the VCC capacitor. The startup regulator turns ON again once VCC reaches 7.5 V. This “7.5−10” mode of operation is known as Dynamic Self Supply (DSS). The NCP1030 and NCP1031 startup currents are 12 mA and 16 mA, respectively. If VCC falls below 7.5 V, the device enters a re−start mode. While in the re−start mode, the VCC capacitor is allowed to discharge to 6.5 V while the Power Switch is enabled. Once the 6.5 V threshold is reached, the Power Switch Circuit is disabled and the startup regulator is enabled to charge the VCC capacitor. The Power Switch is enabled again once the VCC voltage reaches 10 V. Therefore, the external VCC capacitor must be sized such that a voltage greater than 7.5 V is maintained on the VCC capacitor while the converter output reaches regulation. Otherwise, the converter will enter the re−start mode. Equation (1) provides a guideline for the selection of the VCC capacitor for a forward converter; Figure 33. Non−Isolated Bias Supply Configuration The maximum voltage rating of the startup circuit is 200 V. Power dissipation should be observed to avoid exceeding the maximum power dissipation of the package. Error Amplifier The internal error amplifier (EA) regulates the output voltage of the bias supply. It compares a scaled output voltage signal to an internal 2.5 V reference (VREF) connected to its non−inverting input. The scaled signal is fed into the feedback pin (VFB) which is the inverting input of the error amplifier. The output of the error amplifier is available for frequency compensation and connection to the PWM comparator through the COMP pin. To insure normal operation, the EA compensation should be selected such that the EA frequency response crosses 0 dB below 80 kHz. The error amplifier input bias current is less than 1 mA over the operating range. The output source and sink currents are typically 110 mA and 550 mA, respectively. Under load transient conditions, COMP may need to move from the bottom to the top of the CT Ramp. A large current is required to complete the COMP swing if small resistors or large capacitors are used to implement the compensation network. In which case, the COMP swing will http://onsemi.com 13 NCP1030, NCP1031 be limited by the EA sink current, typically 110 mA. Optimum transient response is obtained if the compensation components allow COMP to swing across its operating range in 1 cycle. Line Under and Overvoltage Detector is discharging, guaranteeing a maximum duty cycle of 75 % as shown in Figure 35. CT Ramp COMP The NCP103x incorporates individual line undervoltage (UV) and overvoltage (OV) shutdown circuits. The UV and OV thresholds are 2.5 V. A fault is present if the UV is below 2.5 V or if the OV voltage is above 2.5 V. The UV/OV detectors incorporate 175 mV hysteresis to prevent noise from triggering the shutdown circuits. The UV/OV circuits can be biased using an external resistor divider from the input line as shown in Figure 34. The UV/OV pins should be bypassed using a capacitor to prevent triggering the UV or OV circuits during normal switching operation. Vin R1 + R2 + VOV − VUV R3 − Power Switch Enabled CT Charge Signal 75% 25 % Max Duty Cycle Figure 35. Maximum Duty Cycle vs COMP Figure 18 shows the relationship between the operating frequency and CT. If an UV fault is present, both ICT(C) and ICT(D) are reduced by a factor of 7, thus reducing the operating frequency by the same factor. The oscillator can be synchronized to a higher frequency by capacitively coupling a synchronization pulse into the CT pin. In sync mode, the voltage on the CT pin needs to be driven above 3.5 V to trigger the internal comparator and complete the CT charging period. However, pulsing the CT pin before it reaches 3.5 V will reduce the p−p amplitude of the CT Ramp as shown in Figure 36. Sync Pulse 3.0 V/3.5 V Comparator Reset T2 (f2) 3.5 V Figure 34. UV/OV Resistor Divider from the Input Line The resistor divider must be sized to enable the controller once Vin is within the required operating range. While a UV or OV fault is present, switching is not allowed and the COMP pin is effectively grounded. Either of these comparators can be used for a different function if UV or OV functions are not needed. For example, the UV/OV detectors can be used to implement an enable or disable function. If positive logic is used, the enable signal is applied to the UV pin while the OV pin is grounded. If negative logic is used, the disable signal is applied to the OV pin while biasing the UV pin from VCC using a resistor divider. Oscillator CT Ramp 3.0 V T1 (f1) T2 (f2) CT Voltage Range in Sync Free Running Mode Sync Mode Figure 36. External Frequency Synchronization Waveforms The oscillator frequency should be set no more that 25% below the target sync frequency to maintain an adequate voltage range and provide good noise immunity. A possible circuit to synchronize the oscillator is shown in Figure 37. 5V CT 2 CT R1 C1 R2 The oscillator is optimized for operation up to 1 MHz and its frequency is set by the external timing capacitor (CT) connected to the CT pin. The oscillator has two modes of operation, free running and synchronized (sync). While in free running mode, an internal current source sequentially charges and discharges CT generating a voltage ramp between 3.0 V and 3.5 V. Under normal operating conditions, the charge (ICT(C)) and discharge (ICT(D)) currents are typically 215 mA and 645 mA, respectively. The charge:discharge current ratio of 1:3 discharges CT in 25 % of the total period. The Power Switch is disabled while CT Figure 37. External Frequency Synchronization Circuit. http://onsemi.com 14 NCP1030, NCP1031 PWM Comparator and Latch The Pulse Width Modulator (PWM) Comparator compares the error amplifier output (COMP) to the CT Ramp and generates a proportional duty cycle. The Power Switch is enabled while the CT Ramp is below COMP as shown in Figure 35. Once the CT Ramp reaches COMP, the Power Switch is disabled. If COMP is at the bottom of the CT Ramp, the converter operates at minimum duty cycle. While COMP increases, the duty cycle increases, until COMP reaches the peak of the CT Ramp, at which point the controller operates at maximum duty cycle. The CT Charge Signal is filtered through a One Shot Pulse Generator to set the PWM Latch and enable switching at the beginning of each period. Switching is allowed while the CT Ramp is below COMP and a current limit fault is not present. The PWM Latch and Comparator propagation delay is typically 150 ns. If the system is designed to operate with a minimum ON time less than 150 ns, the converter will skip pulses. Skipping pulses is usually not a problem, unless operating at a frequency close to the audible range. Skipping pulses is more likely when operating at high frequencies during high line and minimum load condition. A series resistor is included for ESD protection between the EA output and the COMP pin. Under normal operation, a 220 mV offset is observed between the CT Ramp and the COMP crossing points. This is not a problem as the series resistor does not interact with the error amplifier transfer function. Current Limit Comparator and Power Switch Circuit recovery time. This spike can cause a premature reset of the PWM Latch. A proprietary active Leading Edge Blanking (LEB) Circuit masks the current signal to prevent the voltage spike from resetting the PWM Latch. The active LEB masks the current signal until the Power Switch turn ON transition is complete. The adaptive LEB period provides better current limit control compared to a fixed blanking period. The current limit propagation delay time is typically 100 ns. This time is measured from when an overcurrent fault appears at the Power Switch Circuit drain, to the start of the turn−off transition. Propagation delay must be factored in the transformer design to avoid transformer saturation. Thermal Shutdown Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. When activated, typically at 150_C, the Power Switch Circuit is disabled. Once the junction temperature falls below 105_C, the NCP103x is allowed to resume normal operation. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a substitute for proper heatsinking. Application Considerations The NCP103x monolithically integrates a 200 V Power Switch Circuit with control logic circuitry. The Power Switch Circuit is designed to directly drive the converter transformer. The characteristics of the Power Switch Circuit are well known. Therefore, the gate drive is tailored to control switching transitions and help limit electromagnetic interference (EMI). The Power Switch Circuit is capable of switching 200 V. The Power Switch Circuit incorporates SENSEFET™ technology to monitor the drain current. A sense voltage is generated by driving a sense element, RSENSE, with a current proportional to the drain current. The sense voltage is compared to an internal reference voltage on the non−inverting input of the Current Limit Comparator. If the sense voltage exceeds the reference level, the comparator resets the PWM Latch and switching is terminated. The NCP1030 and NCP1031 drain current limit thresholds are 0.5 A and 1.0 A, respectively. Each time the Power Switch Circuit turns ON, a narrow voltage spike appears across RSENSE. The spike is due to the Power Switch Circuit gate to source capacitance, transformer interwinding capacitance, and output rectifier A 2 W bias supply for a 48 V telecom system was designed using the NCP1030. The bias supply generates an isolated 12 V output. The circuit schematic is shown in Figure 38. Application Note AND8119/D describes the design of the bias supply. 2.2 MURA110T3 + 35−76V − 0.022 2.2 499 1:2.78 MBRA160T3 22 1M 100 p MBRA160T3 2.2 + 12V − 680p NCP1030 GND VDRAIN VCC CT UV VFB OV COMP 10 4k99 45k3 0.01 1k30 34k 680p 0.033 10k 0.01 Figure 38. 2 W Isolated Bias Supply Schematic http://onsemi.com 15 NCP1030, NCP1031 PACKAGE DIMENSIONS Micro8 DM SUFFIX CASE 846A−02 ISSUE F −A− − K −B− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A−01 OBSOLETE, NEW STANDARD 846A−02. DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 −−− 1.10 0.25 0.40 0.65 BSC 0.05 0.15 0.13 0.23 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 −−− 0.043 0.010 0.016 0.026 BSC 0.002 0.006 0.005 0.009 0.187 0.199 0.016 0.028 PIN 1 ID G D 8 PL 0.08 (0.003) M TB S A S −T− PLANE 0.038 (0.0015) H SEATING C J L SOLDERING FOOTPRINT 8X 1.04 0.041 0.38 0.015 8X 3.20 0.126 4.24 0.167 5.28 0.208 6X 0.65 0.0256 SCALE 8:1 mm inches http://onsemi.com 16 NCP1030, NCP1031 PACKAGE DIMENSIONS SO−8 D SUFFIX CASE 751−07 ISSUE AC −X− A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 4 S 0.25 (0.010) M Y M −Y− G C −Z− H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches http://onsemi.com 17 NCP1030, NCP1031 Micro8 is a trademark of International Rectifier. SENSEFET is a trademark of Semiconductor Components Industries, LLC. The products described herein (NCP1030 and NCP1031) may be covered by one or more of the following U.S. patents: 5,418,410; 5,477,175. There may be other patents pending. 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