DATA SHEET
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Integrated DC-DC
Converter - Power over
Ethernet and Telecom
MARKING
DIAGRAMS
8
Micro8
DM SUFFIX
CASE 846A
8
1
NCP1030, NCP1031
1030
AYWG
G
1
8
The NCP1030 and NCP1031 are a family of miniature high−voltage
monolithic switching regulators with on−chip Power Switch and Startup
Circuits. The NCP103x family incorporates in a single IC all the active
power, control logic and protection circuitry required to implement, with
minimal external components, several switching regulator applications,
such as a secondary side bias supply or a low power dc−dc converter.
This controller family is ideally suited for 48 V telecom, 42 V automotive
and 12 V input applications. The NCP103x can be configured in any
single−ended topology such as forward or flyback. The NCP1030 is
targeted for applications requiring up to 3 W, and the NCP1031 is
targeted for applications requiring up to 6 W.
The internal error amplifier allows the NCP103x family to be easily
configured for secondary or primary side regulation operation in
isolated and non−isolated configurations. The fixed frequency oscillator
is optimized for operation up to 1 MHz and is capable of external
frequency synchronization, providing additional design flexibility. In
addition, the NCP103x incorporates individual line undervoltage and
overvoltage detectors, cycle by cycle current limit and thermal
shutdown to protect the controller under fault conditions. The preset
current limit thresholds eliminate the need for external sensing
components.
1
On Chip High 200 V Power Switch Circuit and Startup Circuit
Internal Startup Regulator with Auxiliary Winding Override
Operation up to 1 MHz
External Frequency Synchronization Capability
Frequency Fold−down Under Fault Conditions
Trimmed ±2% Internal Reference
Line Undervoltage and Overvoltage Detectors
Cycle by Cycle Current Limit Using SENSEFET®
Active LEB Circuit
Overtemperature Protection
Internal Error Amplifier
Pb−Free Packages are Available
N1031
ALYW
G
1
NCP
1031
ALYW G
G
DFN−8
MN SUFFIX
CASE 488AF
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
GND
CT
VFB
COMP
Features
•
•
•
•
•
•
•
•
•
•
•
•
SO−8
D SUFFIX
CASE 751
8
1
8
2
7
3
6
4
5
VDRAIN
VCC
UV
OV
(Top View)
GND
CT
VFB
COMP
Ç
Ç
Ç
Ç
ÇÇ
ÇÇ
ÇÇ
ÇÇ
VDRAIN
EP Flag
VCC
UV
OV
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
Typical Applications
•
•
•
•
•
POE (Power Over Ethernet)/PD. Refer to Application Note AND8247.
Secondary Side Bias Supply for Isolated dc−dc Converters
Stand Alone Low Power dc−dc Converter
Low Power Bias Supply
Low Power Boost Converter
© Semiconductor Components Industries, LLC, 2014
August, 2021 − Rev. 12
1
Publication Order Number:
NCP1030/D
NCP1030, NCP1031
RSENSE
GND
VDRAIN
Disable
I1
+
−
CT Ramp
CT
LEB
ISTART
VCC
Thermal
Shutdown
+
50 mV
−
S
Reset
Dominant
Q
Latch
R
10 V
+
3.0 V/3.5 V −
10 V
+
−
Internal Bias
+
7.5 V/10 V
−
−
+
Current Limit
Comparator
I2 = 3I1
10 V +
S
Reset Q
Dominant
R Latch
−
+
−
+
2.5 V
−
+
−
VFB
Error Amplifier
+
−
One Shot
I Pulse O
PWM Latch
PWM Comparator
+
2.5 V
−
16 V
+
−
+
6.5 V
−
UV
10 V
OV
10 V
4.5 V
COMP
2 kW
10 V
Figure 1. NCP1030/31 Functional Block Diagram
FUNCTIONAL PIN DESCRIPTION
Pin
Name
Function
Description
1
GND
Ground
2
CT
Oscillator Frequency
Selection
3
VFB
Feedback Input
4
COMP
Error Amplifier Compensation
Requires external compensation network between COMP and VFB pins. This pin is
effectively grounded if faults are present.
5
OV
Line Overvoltage Shutdown
Line voltage (Vin) is scaled down using an external resistor divider such that the OV
voltage reaches 2.5 V when line voltage reaches its maximum operating voltage.
6
UV
Line Undervoltage Shutdown
Line voltage is scaled down using an external resistor divider such that the UV
voltage reaches 2.5 V when line voltage reaches its minimum operating voltage.
7
VCC
Supply Voltage
8
VDRAIN
Power Switch and
Startup Circuits
Ground reference pin for the circuit.
An external capacitor connected to this pin sets the oscillator frequency up to 1 MHz.
The oscillator can be synchronized to a higher frequency by charging or discharging
CT to trip the internal 3.0 V/3.5 V comparator. If a fault condition exists, the power
switch is disabled and the frequency is reduced by a factor of 7.
The regulated voltage is scaled down to 2.5 V by means of a resistor divider.
Regulation is achieved by comparing the scaled voltage to an internal 2.5 V reference.
This pin is connected to an external capacitor for energy storage. During Turn−On, the
startup circuit sources current to charge the capacitor connected to this pin. When the
supply voltage reaches VCC(on), the startup circuit turns OFF and the power switch is
enabled if no faults are present. An external winding is used to supply power after
initial startup to reduce power dissipation. VCC should not exceed 16 V.
This pin directly connects the Power Switch and Startup Circuits to one of the
transformer windings. The internal High Voltage Power Switch Circuit is connected
between this pin and ground. VDRAIN should not exceed 200 V.
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2
NCP1030, NCP1031
COMP Voltage
CT Ramp
CT Charge
Signal
PWM
Comparator
Output
Current Limit
Propagation Delay
PWM Latch
Output
Power Switch
Circuit Gate Drive
Current Limit
Threshold
Leading Edge
Blanking Output
Normal PWM Operating Range
Output Overload
Figure 2. Pulse Width Modulation Timing Diagram
VCC(on)
VCC(off)
VCC(reset)
0V
ISTART
0 mA
3.0 V
VUV
0V
2.5 V
VFB
0V
VDRAIN
0V
Power−up &
standby Operation
Normal Operation
Output Overload
Figure 3. Auxiliary Winding Operation with Output Overload Timing Diagram
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3
NCP1030, NCP1031
MAXIMUM RATINGS
Symbol
Value
Unit
Power Switch and Startup Circuits Voltage
Rating
VDRAIN
−0.3 to 200
V
Power Switch and Startup Circuits Input Current
− NCP1030
− NCP1031
IDRAIN
1.0
2.0
A
VCC Voltage Range
VCC
−0.3 to 16
V
All Other Inputs/Outputs Voltage Range
VIO
−0.3 to 10
V
VCC and All Other Inputs/Outputs Current
IIO
100
mA
Operating Junction Temperature
TJ
−40 to 150
°C
Storage Temperature
Tstg
−55 to 150
°C
Power Dissipation (TJ = 25°C, 2.0 Oz., 1.0 Sq Inch Printed Circuit Copper Clad)
DM Suffix, Plastic Package Case 846A
D Suffix, Plastic Package Case 751
MN Suffix, Plastic Package Case 488AF
Thermal Resistance, Junction to Air (2.0 Oz., 1.0 Sq Inch Printed Circuit Copper Clad)
DM Suffix, Plastic Package Case 846A
D Suffix, Plastic Package Case 751
MN Suffix, Plastic Package Case 488AF
0.582
0.893
1.453
RqJA
172
112
69
W
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
A. This device contains ESD protection circuitry and exceeds the following tests:
Pins 1−7: Human Body Model 2000V per MIL−STD−883, Method 3015.
Pins 1−7: Machine Model Method 200 V.
Pin 8 is connected to the High Voltage Startup and Power Switch Circuits and rated only to the maximum voltage rating of the part, or 200 V.
B. This device contains Latchup protection and exceeds $100 mA per JEDEC Standard JESD78.
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NCP1030, NCP1031
DC ELECTRICAL CHARACTERISTICS (VDRAIN = 48 V, VCC = 12 V, CT = 560 pF, VUV = 3 V, VOV = 2 V, VFB = 2.3 V,
VCOMP = 2.5 V, TJ = −40°C to 125°C, typical values shown are for TJ = 25°C unless otherwise noted.) (Note 1)
Symbol
Characteristics
Min
Typ
Max
Unit
STARTUP CONTROL
Startup Circuit Output Current (VFB = VCOMP)
NCP1030
TJ = 25°C
VCC = 0 V
VCC = VCC(on) − 0.2 V
TJ = −40°C to 125°C
VCC = 0 V
VCC = VCC(on) − 0.2 V
NCP1031
TJ = 25°C
VCC = 0 V
VCC = VCC(on) − 0.2 V
TJ = −40°C to 125°C
VCC = 0 V
VCC = VCC(on) − 0.2 V
ISTART
mA
10
6.0
12.5
8.6
15
12
8.0
2.0
−
−
16
13
13
8.0
16
12
19
16
11
4.0
−
−
21
18
VCC Supply Monitor (VFB = 2.7 V)
Startup Threshold Voltage (VCC Increasing)
Minimum Operating VCC After Turn−on (VCC Increasing)
Hysteresis Voltage
VCC(on)
VCC(off)
VCC(hys)
9.6
7.0
−
10.2
7.6
2.6
10.6
8.0
−
Undervoltage Lockout Threshold Voltage, VCC Decreasing (VFB = VCOMP)
VCC(reset)
6.0
6.6
7.0
−
16.8
18.5
2.45
2.40
2.5
2.5
2.55
2.60
REGLINE
−
1.0
5.0
mV
Input Bias Current (VFB = 2.3 V)
IVFB
−
0.1
1.0
mA
COMP Source Current
ISRC
80
110
140
mA
Minimum Startup Voltage (Pin 8)
ISTART = 0.5 mA, VCC =VCC(on) − 0.2 V
VSTART(min)
V
V
V
ERROR AMPLIFIER
Reference Voltage (VCOMP = VFB, Follower Mode)
TJ = 25°C
TJ = −40°C to 125°C
VREF
Line Regulation (VCC = 8 V to 16 V, TJ = 25°C)
COMP Sink Current (VFB = 2.7 V)
V
ISNK
200
550
900
mA
COMP Maximum Voltage (ISRC = 0 mA)
VC(max)
4.5
−
−
V
COMP Minimum Voltage (ISNK = 0 mA, VFB = 2.7 V)
VC(min)
−
−
1.0
V
Open Loop Voltage Gain
AVOL
−
80
−
dB
Gain Bandwidth Product
GBW
−
1.0
−
MHz
Undervoltage Lockout (VFB = VCOMP)
Voltage Threshold (Vin Increasing)
Voltage Hysteresis
Input Bias Current
VUV
VUV(hys)
IUV
2.400
0.075
−
2.550
0.175
0
2.700
0.275
1.0
V
V
mA
Overvoltage Lockout (VFB = VCOMP)
Voltage Threshold (Vin Increasing)
Voltage Hysteresis
Input Bias Current
VOV
VOV(hys)
IOV
2.400
0.075
−
2.550
0.175
0
2.700
0.275
1.0
V
V
mA
LINE UNDER/OVERVOLTAGE DETECTOR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Production testing for NCP1030DMR2 is performed at 25°C only; limits at −40°C and 125°C are guaranteed by design.
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NCP1030, NCP1031
DC ELECTRICAL CHARACTERISTICS (VDRAIN = 48 V, VCC = 12 V, CT = 560 pF, VUV = 3 V, VOV = 2 V, VFB = 2.3 V,
VCOMP = 2.5 V, TJ = −40°C to 125°C, typical values shown are for TJ = 25°C unless otherwise noted.) (Note 2)
Symbol
Characteristics
Min
Typ
Max
275
260
300
−
325
325
Unit
OSCILLATOR
Frequency (CT = 560 pF, Note 3)
TJ = 25°C
TJ = −40°C to 125°C
fOSC1
kHz
Frequency (CT = 100 pF)
fOSC2
−
800
−
kHz
Charge Current (VCT = 3.25 V)
ICT(C)
−
215
−
mA
Discharge Current (VCT = 3.25 V)
ICT(D)
−
645
−
mA
Oscillator Ramp
Peak
Valley
Vrpk
Vrvly
−
−
3.5
3.0
−
−
DCMAX
70
75
80
V
PWM COMPARATOR
Maximum Duty Cycle
%
POWER SWITCH CIRCUIT
Power Switch Circuit On−State Resistance (ID = 100 mA)
NCP1030
TJ = 25°C
TJ = 125°C
NCP1031
TJ = 25°C
TJ = 125°C
RDS(on)
Power Switch Circuit and Startup Circuit Breakdown Voltage
(ID = 100 mA, TJ = 25°C)
V(BR)DS
Power Switch Circuit and Startup Circuit Off−State Leakage Current
(VDRAIN = 200 V, VUV = 2.0 V)
TJ = 25°C
TJ = −40 to 125°C
Switching Characteristics (VDS = 48 V, RL = 100 W)
Rise Time
Fall Time
W
−
−
4.1
6.0
7.0
12
−
−
2.1
3.5
3.0
6.0
200
−
−
IDS(off)
mA
−
−
13
−
25
50
−
−
22
24
−
−
350
700
515
1050
680
1360
−
100
−
TSHDN
THYS
−
−
150
45
−
−
ICC1
2.0
3.0
4.0
ICC2
ICC3
−
−
1.5
0.65
2.0
1.2
tr
tf
V
ns
CURRENT LIMIT AND OVER TEMPERATURE PROTECTION
Current Limit Threshold (TJ = 25°C)
NCP1030 (di/dt = 0.5 A/ms)
NCP1031 (di/dt = 1.0 A/ms)
ILIM
Propagation Delay, Current Limit Threshold to Power Switch Circuit Output
(Leading Edge Blanking plus Current Limit Delay)
tPLH
Thermal Protection (Note 4)
Shutdown Threshold (TJ Increasing)
Hysteresis
mA
ns
°C
TOTAL DEVICE
Supply Current After UV Turn−On
Power Switch Enabled
Power Switch Disabled
Non−Fault condition (VFB = 2.7 V)
Fault Condition (VFB = 2.7 V, VUV = 2.0 V)
2. Production testing for NCP1030DMR2 is performed at 25°C only; limits at −40°C and 125°C are guaranteed by design.
3. Oscillator frequency can be externally synchronized to the maximum frequency of the device.
4. Guaranteed by design only.
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mA
NCP1030, NCP1031
TYPICAL CHARACTERISTICS
20
NCP1030
VDRAIN = 48 V
TJ = 25°C
12.5
12.0
ISTART, STARTUP CURRENT (mA)
ISTART, STARTUP CURRENT (mA)
13.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
0
2
4
6
8
13
12
11
0
2
4
6
8
20
ISTART, STARTUP CURRENT (mA)
NCP1030
VDRAIN = 48 V
14
12
VCC = 0 V
10
8
6
VCC = VCC(on) − 0.2 V
4
2
−25
0
25
50
75
100
125
10
NCP1031
VDRAIN = 48 V
18
VCC = 0 V
16
14
12
10
VCC = VCC(on) − 0.2 V
8
6
4
2
0
−50
150
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. NCP1030 Startup Current vs.
Junction Temperature
Figure 7. NCP1031 Startup Current vs.
Junction Temperature
20
NCP1030
ISTART, STARTUP CURRENT (mA)
ISTART, STARTUP CURRENT (mA)
14
Figure 5. NCP1031 Startup Current vs. Supply
Voltage
0
−50
ISTART, STARTUP CURRENT (mA)
15
Figure 4. NCP1030 Startup Current vs. Supply
Voltage
16
TJ = −40°C
10
8
TJ = 25°C
6
TJ = 125°C
4
2
VCC = VCC(on) − 0.2 V
0
16
VCC, SUPPLY VOLTAGE (V)
18
0
17
VCC, SUPPLY VOLTAGE (V)
20
12
18
10
10
NCP1031
VDRAIN = 48 V
TJ = 25°C
19
25
50
75
100
125
150
175
NCP1031
18
TJ = −40°C
16
14
TJ = 25°C
12
10
TJ = 125°C
8
6
4
2
0
200
VCC = VCC(on) − 0.2 V
0
25
50
75
100
125
150
175
VDRAIN, DRAIN VOLTAGE (V)
VDRAIN, DRAIN VOLTAGE (V)
Figure 8. NCP1030 Startup Current vs. Drain
Voltage
Figure 9. NCP1031 Startup Current vs. Drain
Voltage
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150
200
NCP1030, NCP1031
TYPICAL CHARACTERISTICS
10.0
9.5
9.0
8.5
8.0
VSTART(min), MINIMUM STARTUP VOLTAGE (V)
Minimum Operating Threshold
7.5
7.0
6.5
6.0
−50
−25
0
25
50
75
100
125 150
6.75
6.70
6.65
6.60
6.55
6.50
6.45
6.40
6.35
6.30
−50
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Supply Voltage Thresholds vs.
Junction Temperature
Figure 11. Undervoltage Lockout Threshold
vs. Junction Temperature
150
2.70
VCC = VCC(on) − 0.2 V
ISTART = 0.5 mA
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
0
−25
25
50
75
100
125
150
2.65
VCC = 12 V
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Minimum Startup Voltage vs.
Junction Temperature
Figure 13. Reference Voltage vs. Junction
Temperature
150
840
145
VCC = 12 V
VCOMP = 2.5 V
VFB = 2.3 V
140
135
130
125
120
115
110
105
100
95
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
20.0
15.5
15.0
−50
6.80
ISNK, COMP SINK CURRENT (mA)
ISRC, COMP SOURCE CURRENT (mA)
Startup Threshold
VREF, REFERENCE VOLTAGE (V)
VCC, SUPPLY VOLTAGE (V)
10.5
VCC(reset), UNDERVOLTAGE LOCKOUT
THRESHOLD (V)
11.0
−25
0
25
50
75
100
740
690
640
590
540
490
440
390
340
−50
125 150
VCC = 12 V
VCOMP = 2.5 V
VFB = 2.7 V
790
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 14. COMP Source Current vs. Junction
Temperature
Figure 15. COMP Sink Current vs. Junction
Temperature
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NCP1030, NCP1031
TYPICAL CHARACTERISTICS
220
VUV/OV(hys), UNDER/OVERVOLTAGE
HYSTERESIS (mV)
VUV/OV, LINE UNDER/OVERVOLTAGE THRESHOLDS (V)
2.600
2.575
2.550
2.525
2.500
2.475
2.450
2.425
2.400
2.375
2.350
−50
−25
0
25
50
75
100
125 150
200
190
180
170
160
150
140
130
120
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
Figure 16. Line Under/Overvoltage Thresholds
vs. Junction Temperature
fOSC, OSCILLATOR FREQUENCY (kHz)
VCC = 12 V
TJ = 25°C
900
800
700
600
500
400
300
200
100
0
0
200
400
600
800
1000
VCC = 12 V
CT = 47 pF
900
800
700
600
CT = 220 pF
500
400
300
CT = 1000 pF
200
100
−50
−25
RDS(on), POWER SWITCH CIRCUIT
ON RESISTANCE (W)
DCMAX, MAXIMUM DUTY CYCLE (%)
75.0
74.5
fOSC = 1000 kHz
74.0
73.5
73.0
72.5
72.0
−50
−25
50
75
100
125
150
8
fOSC = 200 kHz
75.5
25
Figure 19. Oscillator Frequency vs. Junction
Temperature
VCC = 12 V
76.0
0
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. Oscillator Frequency vs. Timing
Capacitor
76.5
150
1100
1000
CT, TIMING CAPACITOR (pF)
77.0
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. Line Under/Overvoltage Hysteresis
vs. Junction Temperature
1000
fOSC, OSCILLATOR FREQUENCY (kHz)
210
100
125
0
25
50
75
TJ, JUNCTION TEMPERATURE (°C)
150
Figure 20. Maximum Duty Cycle vs. Junction
Temperature
VCC = 12 V
ID = 100 mA
7
NCP1030
6
5
4
3
NCP1031
2
1
0
−50
−25
100
125
0
25
50
75
TJ, JUNCTION TEMPERATURE (°C)
150
Figure 21. Power Switch Circuit On Resistance
vs. Junction Temperature
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NCP1030, NCP1031
TYPICAL CHARACTERISTICS
40
IDS(off), POWER SWITCH AND STARTUP
CIRCUITS LEAKAGE CURRENT (mA)
COUT, OUTPUT CAPACITANCE (pF)
1000
NCP1031
100
NCP1030
10
0
40
80
120
160
VDRAIN, DRAIN VOLTAGE (V)
200
VCC = 12 V
35
30
25
TJ = −40°C
20
15
TJ = 25°C
10
TJ = 125°C
5
0
0
600
575
NCP1030
Current Slew Rate = 500 mA/ms
550
525
500
475
450
425
400
375
350
−50
−25
0
25
50
75
100
125
150
1150
NCP1031
Current Slew Rate = 1 A/ms
1100
1050
1000
950
900
850
800
750
700
−50
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 24. NCP1030 Current Limit Threshold
vs. Junction Temperature
Figure 25. NCP1031 Current Limit Threshold
vs. Junction Temperature
600
1200
575
NCP1030
TJ = 25°C
550
525
ILIM, CURRENT LIMIT THRESHOLD (mA)
ILIM, CURRENT LIMIT THRESHOLD (mA)
300
1200
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
1150
NCP1031
1100
1050
500
1000
475
450
425
400
375
350
250
Figure 23. Power Switch Circuit and Startup
Circuit Leakage Current vs. Drain Voltage
ILIM, CURRENT LIMIT THRESHOLD (mA)
ILIM, CURRENT LIMIT THRESHOLD (mA)
Figure 22. Power Switch Circuit Output
Capacitance vs. Drain Voltage
200
100
150
VDRAIN, DRAIN VOLTAGE (V)
50
375
400
425
450
475
500
950
900
850
800
750
700
750
CURRENT SLEW RATE (mA/mS)
800
850
900
950
1000
CURRENT SLEW RATE (mA/mS)
Figure 26. NCP1030 Current Limit Threshold
vs. Current Slew Rate
Figure 27. NCP1031 Current Limit Threshold
vs. Current Slew Rate
www.onsemi.com
10
NCP1030, NCP1031
3.9
3.7
4.0
VDRAIN = 48 V
TJ = 25°C
CT = 560 pF
ICC, SUPPLY CURRENT (mA)
4.1
3.5
3.3
3.1
2.9
2.7
2.5
10
11
12
13
14
15
3.0
2.5
VUV = 3.0 V, VFB = 2.3 V
2.0
1.5
VUV = 3.0 V, VFB = 2.7 V
1.0
0.5
0
−50
16
VCC = 12 V
CT = 560 pF
3.5
VUV = 2.0 V
−25
VCC, SUPPLY VOLTAGE (V)
0
25
TJ = 25 °C
9
8
7
6
5
NCP1031
4
NCP1030
3
300
75
100
125
Figure 29. Supply Current vs. Junction
Temperature
10
2
200
50
TJ, JUNCTION TEMPERATURE (°C)
Figure 28. Operating Supply Current vs.
Supply Voltage
ICC, POWER SUPPLY CURRENT (mA)
ICC1, OPERATING SUPPLY CURRENT (mA)
TYPICAL CHARACTERISTICS
400
500
600
700
800
900
fOSC, OSCILLATOR FREQUENCY (kHz)
Figure 30. Operating Supply Current vs.
Oscillator Frequency
www.onsemi.com
11
1000
150
NCP1030, NCP1031
+
Vout
−
+
Vin
−
SECONDARY
SIDE CONTROL
NCP103x
GND VDRAIN
CT
VCC
VFB
UV
COMP OV
VBIAS
GND
Figure 31. Secondary Side Bias Supply Configuration
VCC
+
Vin
−
NCP103x
GND VDRAIN
VCC
CT
VFB
UV
COMP OV
VCC
+
Vout
−
Figure 32. Boost Circuit Configuration
www.onsemi.com
12
NCP1030, NCP1031
OPERATING DESCRIPTION
Introduction
Forward:
The NCP1030 and NCP1031 are a family of miniature
monolithic voltage−mode switching regulators designed for
isolated and non−isolated bias supply applications. The
internal startup circuit and the MOSFET are rated at 200 V,
making them ideal for 48 V telecom and 42 V automotive
applications. In addition, the NCP103x family can operate
from an existing 12 V supply. This controller family is
optimized for operation up to 1 MHz.
The NCP103x family incorporates in a single IC all the
active power, control logic and protection circuitry required
to implement, with a minimum of external components,
several switching regulator applications, such as a
secondary side bias supply or a low power dc−dc converter.
The NCP1030 is available in the space saving Micro8t
package and is targeted for applications requiring up to 3 W.
The NCP1031 is targeted for applications up to 6 W and is
available in the SO−8 package.
The NCP103x includes an extensive set of features
including over temperature protection, cycle by cycle
current limit, individual line under and overvoltage
detection comparators with hysteresis, and regulator output
undervoltage lockout with hysteresis, providing full
protection during fault conditions. A description of each of
the functional blocks is given below, and the representative
block diagram is shown in Figure 2.
OUT@ P Ǔ
cos −1 ǒ1 * DC@V
@N
V
CCC +
N
in
S
2.6
ǸL C
OUT OUT @ Ibias
(eq. 1)
where, Ibias is the bias current supplied by the VCC capacitor
including the IC bias current (ICC1) and any additional
current used to bias the feedback resistors (if used).
After initial startup, the VCC pin should be biased above
VCC(off) using an auxiliary winding. This will prevent the
startup regulator from turning ON and reduce power
dissipation. Also, the load should not be directly connected
to the VCC capacitor. Otherwise, the load may override the
startup circuit. Figure 33 shows the recommended
configuration for a non−isolated flyback converter.
+
Vout
−
+
Vin
−
NCP103x
GND VDRAIN
CT
VCC
VFB
UV
COMP OV
Startup Circuit and Undervoltage Lockout
The NCP103x contains an internal 200 V startup regulator
that eliminates the need for external startup components.
The startup regulator consists of a constant current source
that supplies current from the input line (Vin) to the capacitor
on the VCC pin (CCC). Once the VCC voltage reaches
approximately 10 V, the startup circuit is disabled and the
Power Switch Circuit is enabled if no faults are present.
During this self−bias mode, power to the NCP103x is
supplied by the VCC capacitor. The startup regulator turns
ON again once VCC reaches 7.5 V. This “7.5−10” mode of
operation is known as Dynamic Self Supply (DSS). The
NCP1030 and NCP1031 startup currents are 12 mA and 16
mA, respectively.
If VCC falls below 7.5 V, the device enters a re−start mode.
While in the re−start mode, the VCC capacitor is allowed to
discharge to 6.5 V while the Power Switch is enabled. Once
the 6.5 V threshold is reached, the Power Switch Circuit is
disabled and the startup regulator is enabled to charge the
VCC capacitor. The Power Switch is enabled again once the
VCC voltage reaches 10 V. Therefore, the external VCC
capacitor must be sized such that a voltage greater than 7.5
V is maintained on the VCC capacitor while the converter
output reaches regulation. Otherwise, the converter will
enter the re−start mode. Equation (1) provides a guideline
for the selection of the VCC capacitor for a forward
converter;
Figure 33. Non−Isolated Bias Supply Configuration
The maximum voltage rating of the startup circuit is
200 V. Power dissipation should be observed to avoid
exceeding the maximum power dissipation of the package.
Error Amplifier
The internal error amplifier (EA) regulates the output
voltage of the bias supply. It compares a scaled output
voltage signal to an internal 2.5 V reference (VREF)
connected to its non−inverting input. The scaled signal is fed
into the feedback pin (VFB) which is the inverting input of the
error amplifier.
The output of the error amplifier is available for frequency
compensation and connection to the PWM comparator
through the COMP pin. To insure normal operation, the EA
compensation should be selected such that the EA frequency
response crosses 0 dB below 80 kHz.
The error amplifier input bias current is less than 1 mA
over the operating range. The output source and sink
currents are typically 110 mA and 550 mA, respectively.
Under load transient conditions, COMP may need to
move from the bottom to the top of the CT Ramp. A large
current is required to complete the COMP swing if small
resistors or large capacitors are used to implement the
compensation network. In which case, the COMP swing will
www.onsemi.com
13
NCP1030, NCP1031
be limited by the EA sink current, typically 110 mA.
Optimum transient response is obtained if the compensation
components allow COMP to swing across its operating
range in 1 cycle.
is discharging, guaranteeing a maximum duty cycle of 75 %
as shown in Figure 35.
COMP
CT Ramp
Line Under and Overvoltage Detector
The NCP103x incorporates individual line undervoltage
(UV) and overvoltage (OV) shutdown circuits. The UV and
OV thresholds are 2.5 V. A fault is present if the UV is below
2.5 V or if the OV voltage is above 2.5 V. The UV/OV
detectors incorporate 175 mV hysteresis to prevent noise
from triggering the shutdown circuits.
The UV/OV circuits can be biased using an external
resistor divider from the input line as shown in Figure 34.
The UV/OV pins should be bypassed using a capacitor to
prevent triggering the UV or OV circuits during normal
switching operation.
Power Switch
Enabled
CT Charge
Signal
Figure 35. Maximum Duty Cycle vs COMP
Figure 18 shows the relationship between the operating
frequency and CT. If an UV fault is present, both ICT(C) and
ICT(D) are reduced by a factor of 7, thus reducing the
operating frequency by the same factor.
The oscillator can be synchronized to a higher frequency
by capacitively coupling a synchronization pulse into the CT
pin. In sync mode, the voltage on the CT pin needs to be
driven above 3.5 V to trigger the internal comparator and
complete the CT charging period. However, pulsing the CT
pin before it reaches 3.5 V will reduce the p−p amplitude of
the CT Ramp as shown in Figure 36.
R1
+
R2
R3
75%
25 %
Vin
+
VOV
−
Max
Duty Cycle
VUV
−
3.0 V/3.5 V
Comparator
Reset
Sync Pulse
Figure 34. UV/OV Resistor Divider
from the Input Line
T2 (f2)
3.5 V
The resistor divider must be sized to enable the controller
once Vin is within the required operating range. While a UV
or OV fault is present, switching is not allowed and the
COMP pin is effectively grounded.
Either of these comparators can be used for a different
function if UV or OV functions are not needed. For example,
the UV/OV detectors can be used to implement an enable or
disable function. If positive logic is used, the enable signal
is applied to the UV pin while the OV pin is grounded. If
negative logic is used, the disable signal is applied to the OV
pin while biasing the UV pin from VCC using a resistor
divider.
CT
Ramp
3.0 V
T1 (f1)
T2 (f2)
Free Running
Mode
CT Voltage
Range in Sync
Sync Mode
Figure 36. External Frequency Synchronization
Waveforms
The oscillator frequency should be set no more that 25%
below the target sync frequency to maintain an adequate
voltage range and provide good noise immunity. A possible
circuit to synchronize the oscillator is shown in Figure 37.
Oscillator
The oscillator is optimized for operation up to 1 MHz and
its frequency is set by the external timing capacitor (CT)
connected to the CT pin. The oscillator has two modes of
operation, free running and synchronized (sync). While in
free running mode, an internal current source sequentially
charges and discharges CT generating a voltage ramp
between 3.0 V and 3.5 V. Under normal operating
conditions, the charge (ICT(C)) and discharge (ICT(D))
currents are typically 215 mA and 645 mA, respectively. The
charge:discharge current ratio of 1:3 discharges CT in 25 %
of the total period. The Power Switch is disabled while CT
5V
CT
CT
R1
C1
2
R2
Figure 37. External Frequency Synchronization
Circuit.
www.onsemi.com
14
NCP1030, NCP1031
PWM Comparator and Latch
provides better current limit control compared to a fixed
blanking period.
The current limit propagation delay time is typically
100 ns. This time is measured from when an overcurrent
fault appears at the Power Switch Circuit drain, to the start
of the turn−off transition. Propagation delay must be
factored in the transformer design to avoid transformer
saturation.
The Pulse Width Modulator (PWM) Comparator
compares the error amplifier output (COMP) to the CT
Ramp and generates a proportional duty cycle. The Power
Switch is enabled while the CT Ramp is below COMP as
shown in Figure 35. Once the CT Ramp reaches COMP, the
Power Switch is disabled. If COMP is at the bottom of the
CT Ramp, the converter operates at minimum duty cycle.
While COMP increases, the duty cycle increases, until
COMP reaches the peak of the CT Ramp, at which point the
controller operates at maximum duty cycle.
The CT Charge Signal is filtered through a One Shot Pulse
Generator to set the PWM Latch and enable switching at the
beginning of each period. Switching is allowed while the CT
Ramp is below COMP and a current limit fault is not present.
The PWM Latch and Comparator propagation delay is
typically 150 ns. If the system is designed to operate with a
minimum ON time less than 150 ns, the converter will skip
pulses. Skipping pulses is usually not a problem, unless
operating at a frequency close to the audible range. Skipping
pulses is more likely when operating at high frequencies
during high line and minimum load condition.
A series resistor is included for ESD protection between the
EA output and the COMP pin. Under normal operation, a 220
mV offset is observed between the CT Ramp and the COMP
crossing points. This is not a problem as the series resistor
does not interact with the error amplifier transfer function.
Thermal Shutdown
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event the maximum
junction temperature is exceeded. When activated, typically
at 150_C, the Power Switch Circuit is disabled. Once the
junction temperature falls below 105_C, the NCP103x is
allowed to resume normal operation. This feature is
provided to prevent catastrophic failures from accidental
device overheating. It is not intended to be used as a
substitute for proper heatsinking.
Application Considerations
A 2 W bias supply for a 48 V telecom system was designed
using the NCP1030. The bias supply generates an isolated
12 V output. The circuit schematic is shown in Figure 38.
Application Note AND8119/D describes the design of the
bias supply.
1:2.78 MBRA160T3
+
35−76V
−
The NCP103x monolithically integrates a 200 V Power
Switch Circuit with control logic circuitry. The Power
Switch Circuit is designed to directly drive the converter
transformer. The characteristics of the Power Switch Circuit
are well known. Therefore, the gate drive is tailored to
control switching transitions and help limit electromagnetic
interference (EMI). The Power Switch Circuit is capable of
switching 200 V.
The Power Switch Circuit incorporates SENSEFET™
technology to monitor the drain current. A sense voltage is
generated by driving a sense element, RSENSE, with a current
proportional to the drain current. The sense voltage is
compared to an internal reference voltage on the
non−inverting input of the Current Limit Comparator. If the
sense voltage exceeds the reference level, the comparator
resets the PWM Latch and switching is terminated. The
NCP1030 and NCP1031 drain current limit thresholds are
0.5 A and 1.0 A, respectively.
Each time the Power Switch Circuit turns ON, a narrow
voltage spike appears across RSENSE. The spike is due to the
Power Switch Circuit gate to source capacitance,
transformer interwinding capacitance, and output rectifier
recovery time. This spike can cause a premature reset of the
PWM Latch. A proprietary active Leading Edge Blanking
(LEB) Circuit masks the current signal to prevent the
voltage spike from resetting the PWM Latch. The active
LEB masks the current signal until the Power Switch turn
ON transition is complete. The adaptive LEB period
2.2
0.022
680p
499
22
NCP1030
GND VDRAIN
VCC
CT
UV
VFB
OV
COMP
2.2
680p
10
4k99
45k3
0.01
0.01
+
12V
−
MBRA160T3
1M
100 p
Current Limit Comparator and Power Switch Circuit
MURA110T3
2.2
1k30
34k
0.033 10k
Figure 38. 2 W Isolated Bias Supply Schematic
VCC Excursion and Compensation
Some applications may regulate nodes that are not directly
connected to VCC, such as the secondary or AUX1 shown
in Figure 39. The regulation of another node can result in
loose regulation of VCC. The result of loose regulation is
that VCC can rise to unacceptable levels when a heavy load
is applied to the regulated node and a relatively light load is
applied to the VCC pin. The large voltage can lead to
damage of the NCP1030/31 or other downstream parts.
www.onsemi.com
15
NCP1030, NCP1031
Cin
Lsec
To reduce the problem, a series resistance can be added to
allow the part to clamp VCC with the characteristic current
draw of the regulator as the voltage increases. The resistor
value required is such that it will not implead normal
operation but will prevent damage to the device during
transients, startup, current limits, and over loads. The proper
sizing of the series resistance starts with an examination of
the current draw by the NCP1031 at the desired operating
frequency as shown in Figure 40. The resistor value should
be such that it does not exceed the VCC maximum voltage
of 16 V during the worst case overshoot. Further, the voltage
must not fall below the VCC minimum operating voltage of
7 V during heavy loading, transients, or line disturbances. A
series resistance calculated example of operation at 310 kHz
is shown in Equation 2. In this case, a 1.96 kW resistor can
be used to make the VCC node more robust.
COUT
D1
D2
Lpri
CAUX1
Lbias
D2
CAUX2
RC
UV
R4
VDRAIN
R3
VCC
OV
CVCC
CC
CT
GND
NCP1032
COMP
RC
R1
CP
VFB
NCP1030/31
CCT
Calculation of RC
R2
16 V w V OUTaux * I C_current @ RC w 7.0 V
(eq. 2)
V OUTaux * 16 V
+ RC
I C_current
Figure 39. Typical Application with the Series
Resistance Added to Control VCC
24 V * 16 V
+ 1.96 kW
4.075 mA
12.5 V * 7.0 V
+ 2.07 kW
2.65 mA
11
VCC Current Draw (mA)
10
560 pF 310kHz
470 pF 350kHz
390 pF 390kHz
330 pF 450kHz
270 pF 500kHz
220 pF 573kHz
180 pF 635 kHz
150 pF 702kHz
100 pF 905kHz
82 pF 1MHz
9
8
7
6
5
4
18
17
16
15
14
13
12
11
10
9
8
2
7
3
VCC Voltage (V)
Figure 40. NCP1031 Current Draw vs. Frequency and VCC Voltage
cannot eliminate the possibility completely. A zener diode
can be added along with the series resistance value
calculated from Equation 2 which can be split into RC1 and
RC2 as shown in Figure 41. If the OV pin is not used, it can
be connected to the VCC node to monitor the voltage and
suspend switching if the voltage exceeds a predefined level.
The addition of the ROV1 and ROV2 will add a current draw
from VAUX and will increase the voltage drop across RC.
The series resistor needs to be coupled with proper sizing
of the auxiliary winding and VCC capacitance. The CAUX1
and CAUX2 should be approximately the same size where
the CVCC should be between 1/10 to 1/100 the value of
CAUX2. The smaller size of CVCC serves to reduce the
amount of energy available to the internal clamping
structures in the event of a large unforeseen over voltage.
Proper sizing of capacitance and adding a series resistance
can reduce the likelihood of an over voltage on the VCC, but
www.onsemi.com
16
NCP1030, NCP1031
Lbias
D2
CAUX1
CAUX2
D2
D2
Lbias
CAUX1
CAUX2
D2
RC1
RC
RC2
NCP1030/31
NCP1030/31
VCC
VCC
CVCC
CVCC
GND
ROV1
OV
ROV2
GND
Figure 41. Zener Clamp or OV Protection
The compensation of the NCP1031/30 should be
completed with the loop response, the transient response,
and the amplifier in mind. The amplifier can source 110 mA
and sink 550 mA typical. Internally the current sink that pulls
down the amplifier has an on resistance of 2.45 kW and an
ESD resistance of 1.74 kW as shown in Figure 42. The two
resistances combine to create a maximum pull down current
that changes with comp voltage as shown in Figure 43 and
Figure 44.
3.5
VOUT
3.0
R1
R2
C1
C2
COMP
5V Rail
Rf
FB
RESD
1.74 kW
EA
2.5V
COMP VOLTAGE (V)
C3
R3
5V Rail
PWM
COMP
2.45 kW
2.5
2.0
1.5
1.0
0.5
0
−25
75
Figure 42. Internal Error Amplifier Structure
175
275
375
SINK CURRENT (mA)
475
700
600
500
400
300
200
100
0
-100
-200
4.5V
3.5V
2.5V
1.5V
2.6
2.59
2.58
2.57
2.56
2.55
VFB(V)
2.54
2.53
2.52
2.51
2.5
2.49
2.48
2.47
2.46
1.0V
2.45
Amplifier Current (uA)
Figure 43. Sink Current vs. Comp Voltage
0.5V
Figure 44. Amplifier Sink Current with Comp at Steady Voltage vs Feedback Voltage
www.onsemi.com
17
575
NCP1030, NCP1031
One source of overshoot in the system can occur during
startup where the reference voltage starts at 2.5 V and the
system PWM regulates to the desired output voltage. The
power is limited to the system by the internally set current
limit. Since the voltage feedback loop sees the output
voltage is lower than it should be, the COMP voltage slews
up to increase the duty cycle, but the duty cycle is controlled
by the pulse by pulse current limit. Once regulated output
voltage is reached, the current loop will maintain control for
the time it takes the COMP pin to slew from 5 V to 3.25 V
where the voltage loop takes control and the pulse by pulse
current limit is no longer limiting the system. The same is
true for an overload or current limit. If the COMP voltage
has reached a steady state value of 5 V, the required
compensation value needed to slew from 5 V to 3.25 V is
shown in Equation 3. Equation 3 is true if the feedback node
has very low impedance at 2.5 V. For comparison, the decay
from 5 V to 3.25 V in network A occurs in 259 ns and
network B occurs in 12.2 ms although they have a very
similar frequency response.
RC1 +
CP
100 pF
I PULL_DOWN
5 V * 3.25 V
500 mA
VAUX
R1
VFB
A
R2
CC
820 pF
NCP1030/31
RC1
432 W
CP
18 nF
COMP
GND
V COMP_INIT * V COMP_FINAL
300 ns + 100 pF @
RC1
2.5 kW
(eq. 3)
5 V * 3.25 V
500 mA
Time + CP @
COMP
GND
I PULL_DOWN
3.5 kW +
CC
22 nF
NCP1030/31
V COMP_INIT * V COMP_FINAL
VAUX
CF
1.5 nF
R1
VFB
B
RF
215 W
R2
Figure 45. Compensation for Good Transient Response
When considering compensation and overshoot, the
designer should follow a few rules for a better result.
1. If the current flowing through R1 and R2 is 10X
larger than 620 mA then the RF and CF
contribution to the large signal is small.
a.) If RF is small (1 W -100 W) there is only a
small DC shift from RC1.
b.) To create a large DC shift down, increase
RF (1 kW -10 kW).
2. Keep CP small (CP < 1 nF) or it will slow the
large signal response of the converter.
3. CF should be less than 22 nF.
4. RC1 should be 2.7 k < RC1 < 100 k.
www.onsemi.com
18
NCP1030, NCP1031
ORDERING INFORMATION
Package
Shipping†
Micro8
4000 / Tape & Reel
Micro8
(Pb−Free)
4000 / Tape & Reel
SOIC−8
2500 / Tape & Reel
NCP1031DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1031MNTXG
DFN8
(Pb−Free)
4000 / Tape & Reel
Device
NCP1030DMR2
NCP1030DMR2G
NCP1031DR2
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SENSEFET is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in
the United States and/or other countries.
www.onsemi.com
19
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8, 4x4
CASE 488AF−01
ISSUE C
1
SCALE 2:1
A
B
D
PIN ONE
REFERENCE
2X
0.15 C
2X
0.15 C
0.10 C
8X
ÉÉ
ÉÉ
ÉÉ
0.08 C
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
EXPOSED Cu
DETAIL B
ÇÇÇÇ
(A3)
A
A1
C
D2
ÇÇÇÇ
e
8X
SEATING
PLANE
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
A1
ALTERNATE
CONSTRUCTIONS
8X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
1.91
2.21
4.00 BSC
2.09
2.39
0.80 BSC
0.20
−−−
0.30
0.50
−−−
0.15
XXXXXX
XXXXXX
ALYWG
G
E2
5
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
GENERIC
MARKING DIAGRAM*
L
4
ÇÇÇÇ
8
MOLD CMPD
DETAIL B
SIDE VIEW
K
ÇÇÇ
ÇÇÇ
ÉÉÉ
TOP VIEW
1
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL CONSTRUCTIONS FOR TERMINALS.
L
L
L1
NOTE 4
DETAIL A
DATE 15 JAN 2009
b
XXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
SOLDERING FOOTPRINT*
2.21
8X
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.63
4.30 2.39
PACKAGE
OUTLINE
8X
0.35
0.80
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON15232D
DFN8, 4X4, 0.8P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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