NCS2553DGEVB

NCS2553 3-Channel Video Amp with Standard Definition Reconstruction Filters Description The NCS2553 is a 3−channel high speed video amplifier with 6th order butterworth standard definition reconstruction filter. All three channels can accommodate either all component and RGB video signals or composite and S−Video signals. All channels can accept DC or AC coupled signals. If AC coupled, the internal clamps are employed. The outputs can drive both AC and DC coupled 150 W loads. It is designed to be compatible with most digital−to−analog converters (DAC) embedded in most video processors. Feature • • • • • • • • Three 6th Order Standard Definition 8 MHz Filters Internally Fixed Gain = 6 dB AC− or DC− Coupled Inputs AC− or DC− Coupled Outputs Integrated Level Shifter Operating Voltage +5 V Available in a SOIC−8 Package These are Pb−Free Devices MARKING DIAGRAM 8 8 1 SOIC−8 NB D SUFFIX CASE 751 A L Y W G N2553 ALYW G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PINOUT 8 SD OUT1 SD IN1 1 Applications • • • • • http://onsemi.com SD IN2 2 Digital Set−Top Box DVD / Video Players and Related SD−TV Video On Demand (VOD) Video Recorders NCS2553 SOIC−8 SD IN3 3 7 SD OUT2 6 SD OUT3 VCC 4 5 GND ORDERING INFORMATION Package Shipping† NCS2553DG SOIC−8 (Pb−Free) 98 Units / Rail NCS2553DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2008 December, 2008 − Rev. 4 1 Publication Order Number: NCS2553/D NCS2553 SD IN1 Transparent Clamp 6dB SD OUT1 6dB SD OUT2 6dB SD OUT3 8 MHz, 6th Order Transparent Clamp SD IN2 8 MHz, 6th Order Transparent Clamp SD IN3 8 MHz, 6th Order Figure 1. Block Diagram PIN FUNCTION AND DESCRIPTION Pin Name Type Description 1 IN1 Input Video Input 1 for Video Signal featuring a frequency bandwidth compatible with Standard Definition Video (8 MHz) − Channel 1 2 IN2 Input Video Input 2 for Video Signal featuring a frequency bandwidth compatible with Standard Definition Video (8 MHz) − Channel 2 3 IN3 Input Video Input 3 for Video Signal featuring a frequency bandwidth compatible with Standard Definition Video (8 MHz) − Channel 3 4 VCC Power Device Power Supply Voltage: +5 V 5 GND GND Connected to Ground 6 OUT3 Output SD Video Output 3 − Channel 3 7 OUT2 Output SD Video Output 2 − Channel 2 8 OUT1 Output SD Video Output 1 − Channel 1 ATTRIBUTES Characteristics ESD Human Body Model Machine Model Value All Pins (Note 1) Pins 1 to 5 (Note 2) All Output Pins (Note 2) 8 kV 400 V 800 V Moisture Sensitivity (Note 3) Level 1 Flammability Rating − Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in 1. Human Body Model (HBM): R = 1500 W, C = 100 pF 2. Machine Model (MM) 3. For additional information, see Application Note AND8003/D. http://onsemi.com 2 NCS2553 MAXIMUM RATINGS Parameter Symbol Rating Unit VCC −0.35 v VCC v 5.5 Vdc Input Voltage Range VI −0.3 v VI v VCC Vdc Input Differential Voltage Range VID VI v VCC Vdc Output Current IO 50 mA Maximum Junction Temperature (Note 4) TJ 150 °C Power Supply Voltages Operating Ambient Temperature TA −40 to +85 °C Storage Temperature Range Tstg −60 to +150 °C Power Dissipation PD (See Graph) mW RqJA 112.7 °C/W Thermal Resistance, Junction−to−Air Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. 1800 The maximum power that can be safely dissipated is limited by the associated rise in junction temperature. For the plastic packages, the maximum safe junction temperature is 150°C. If the maximum is exceeded momentarily, proper circuit operation will be restored as soon as the die temperature is reduced. Leaving the device in the “overheated” condition for an extended period can result in device burnout. To ensure proper operation, it is important to observe the de−rating curves. 1600 POWER DISSIPATION (mW) Maximum Power Dissipation 1400 1200 1000 800 600 400 200 0 −40 −30−20−10 0 10 20 30 40 50 60 70 80 90100 TEMPERATURE (°C) Figure 2. Power Dissipation vs Temperature http://onsemi.com 3 NCS2553 DC ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, TA = 25°C, 0.1 mF AC coupled inputs, Rsource = 37.5 W, 220 mF AC coupled outputs into 150 W load, referenced to 400 kHz, unless otherwise specified) Symbol Characteristics VCC Supply Voltage Range ICC Power Supply Current VIN Input Common Mode Voltage Range PSRR Power Supply Rejection Conditions Min Typ Max Unit 4.75 5.0 5.25 V 23 30 mA No Load Referenced to GND if DC−Coupled GND DC (All Channels) 1.4 −50 dB NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. AC ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, TA = 25°C, 0.1 mF AC coupled inputs, Rsource = 37.5 W,220 mF AC coupled outputs into 150 W load, referenced to 400 kHz, unless otherwise specified) Symbol Characteristics AVOL Voltage Gain (Note 5) BW Low Pass Filter Bandwidth Conditions Min Typ Max Unit VIN = 1 V (All Channels) 5.8 6.0 6.2 dB −1 dB (Note 6) 5.5 7.2 MHz −3 dB 9.0 MHz at 27 MHz 45 dB 0.3 % AR Stop−Band Attenuation (Rejection) dG Differential Gain dq Differential Phase 0.6 _ THD Total Harmonic Distortion VOUT = 1.8 VPP @ 1 MHz 0.4 % Xtalk Channel−to−Channel Crosstalk VOUT = 1.8 VPP @ 1 MHz −60 dB SNR Signal−to−Noise Ratio NTSC−7, 100 kHz to 4.2 MHz (Note 7) 75 dB Tpd Propagation Delay Input−to−Output, 4.5 MHz 60 nsec DGD Group Delay Variation from 100 kHz to 8 MHz 27 ns NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. 100% of tested IC fit to the bandwidth tolerance. 6. Guaranteed by design and characterization. 7. SNR = 20 x log (714 mV/RMS Noise) http://onsemi.com 4 NCS2553 TYPICAL CHARACTERISTICS VCC = +5.0 V, Rsource = 37.5 W, TA = 25°C, 0.1 mF AC−coupled inputs, 220 mF AC−coupled outputs into 150 W referenced to 400 kHz, all channels, unless otherwise specified −35 6.7 MHz, −0.5 dB 6 dB 9.0 MHz, −3 dB 0 GAIN (dB) −10 −45 7.2 MHz, −1 dB −20 −30 −40 −50 27 MHz Stop−band Rejection = 46 dB (6 dB − (−40 dB)) −60 −70 Vin = 4 dBm Zout = 150 W −80 0.01 0.1 1 10 6.7 MHz, −43 dB −40 −50 CROSSTALK (dB) 20 10 −55 −60 1 MHz, −60 dB −65 −70 −75 −80 −85 100k 100 Vin = 4 dBm Zout = 150 W 8M 1M FREQUENCY (MHz) FREQUENCY (Hz) Figure 3. Frequency Response Figure 4. Channel−to−Channel Crosstalk 110 70 60 50 40 20 10 100k 3.0 1.5 2.6 1.25 0.75 1.2 79 ns 0.5 0.8 Output 0.25 0.4 0 −0.75 1M 10M 30M 0 −0.4 50 100 150 200 250 300 350 400 450 500 FREQUENCY (Hz) TIME (ns) Figure 5. Group Delay Figure 6. Propagation Delay −45 −45 −50 −50 −55 −55 −60 −60 −65 −65 −70 −75 −80 −70 −75 −80 −85 −95 100k 1.6 0 Vin = 4 dBm Zout = 150 W −90 2.0 Input 1.0 OUTPUT VOLTAGE (V) 80 30 PSRR (dB) INPUT VOLTAGE (V) 90 1.75 PSRR (dB) GROUP DELAY (ns) 100 −85 Vin = −22 dBm Zout = 150 W −90 1M 10M −95 100k 50M FREQUENCY (Hz) Vin = −22 dBm Zout = 150 W 1M FREQUENCY (Hz) 10M Figure 8. PSRR vs. Frequency (Bypass Capacitor) Figure 7. PSRR vs Frequency (No Bypass Capacitor) http://onsemi.com 5 50M NCS2553 TYPICAL CHARACTERISTICS VCC = +5.0 V, Rsource = 37.5 W, TA = 25°C, 0.1 mF AC−coupled inputs, 220 mF AC−coupled outputs into 150 W referenced to 400 kHz, all channels, unless otherwise specified 6.4 6.2 GAIN (dB) 3.8 MHz, 6.19 dB 400 kHz, 6.04 dB 6 5.5 MHz, 6.00 dB 5.8 5.6 5.4 0.01 6.7 MHz, 5.5 dB Vin = 4 dBm Zout = 150 W 0.1 1 FREQUENCY (Hz) 10 Figure 9. Gain Flatness 0.5 1.2 0.46 0.35 0.35 0.3 0.3 0.25 0.18 0.2 0.15 0.1 0 0.04 2 0.81 0.8 0.61 0.6 0.6 0.44 0.4 0.2 0 0 1 0.96 1 3 4 5 0 6 1 2 3 4 5 6 HARMONIC NUMBERS HARMONIC NUMBERS Figure 10. Differential Gain (NTSC 5 Steps Input Signal) Figure 11. Differential Phase (NTSC 5 Steps Input Signal 120 20 Gain 105 10 90 0 75 −10 60 −20 45 −30 Group Delay 30 −40 15 −50 0 −60 −15 −70 −30 20k 100k 1M FREQUENCY (Hz) 10M GAIN (dB) 0.05 DIFFERENTIAL PHASE (°) 0.4 GROUP DELAY (ns) DIFFERENTIAL GAIN (%) 0.45 −80 40M Figure 12. Normalized Frequency Response and Group Delay vs. Frequency http://onsemi.com 6 NCS2553 APPLICATIONS INFORMATION and allows DC−coupled output to the 150 W video load. In addition, the NCS2553 integrates a 6th order Butterworth filter per channel with a 3 dB frequency bandwidth of 8 MHz. This allows rejecting out the aliases or unwanted over−sampling effects produced by the video DAC. Similarly, in the case of DVD recorders using ADC, this anti−aliasing filter (reconstruction filter) will avoid picture quality issues and will help to filter out parasitic signals caused by EMI interference. A built−in diode−like clamp is used in the chip for each channel to support AC−coupled mode of operation. The clamp is active when the input signal goes below 0 V. The NCS2553 triple video driver has been optimized for Standard Definition video applications covering the requirements of the CVBS, S−Video, 480i/525i & 576i/625i standards. All the 3 channels feature the same specifications and similar behaviors guaranteed by a high channel−to− channel crosstalk isolation (down to 60 dB at 1 MHz). Each channel provides an internal voltage−to−voltage gain of 2 from its input to its output reducing the number of external components usually needed in the case of some discrete approaches (using stand−alone op amps). An internal level shifter is employed shifting up the output voltage by adding an offset of about 280 mV. This avoids sync pulse clipping 2.28V 1V Y, R’, G’, B’ 1VPP 0V 0.1mF IN1 Clamp 0.28V 220mF LS 8MHz 75W OUT1 0.1mF IN2 DAC Clamp 800k RS 0.1mF IN3 Clamp 800k RS 6db 220mF LS 8MHz 6db 280mV LS 8MHz 220mF 280mV 6db ZO = 75W 75W ZO = 75W 75W ZO = 75W 75W 75W OUT2 OUT3 800k RS 280mV 75W 1.68V 0.7V Pb, Pr 0V 0.28V 0.7VPP Figure 13. AC−Coupled Inputs and Outputs The input is AC−coupled if for example the input−signal amplitude goes over the range 0 to 1.4 V or if the video source requires such a coupling. In some circumstances it may be necessary to auto−bias signals by the addition of a pull−up and pull−down resistor or only pull−up resistor (Typical 7.5 MW combined with the internal 800 kW pull−down) making the clamp inactive. The output AC−coupling configuration has the advantage of eliminating DC ground loop with the drawback of making the device more sensitive to video line or field tilt issues in the case of a too low output coupling capacitor. In some cases it may be necessary to increase the nominal 220 mF capacitor value. Figure 13 shows an example for which the external video source coming from the DAC is AC−coupled at the input and output. But thanks to the built−in transparent clamp and level shifter the device can operate in different configuration modes depending essentially on the DAC output signal level High and Low and how it fits the input common mode voltage of the video driver. When the configuration is DC−Coupled at the Inputs and Outputs the 0.1 mF and 220 mF coupling capacitors are no longer used, the clamps are in that case inactive; this configuration has the big advantage of being relatively low cost with the use of less external components. http://onsemi.com 7 NCS2553 DVD Player or STB +5 V 0.1 mF 1 R/Pr 10 mF IN1 OUT1 8 Video SOC 2 IN2 OUT2 NCS2553 RS 3 B/Pd RS R/Pr 75 W RS G/Y 75 W 220 mF 75 W Video Cables IN3 OUT3 7 75 W 220 mF 75 W Video Cables G/Y 75 W 6 75 W 220 mF 75 W Video Cables B/Pd 75 W 4 VCC GND 5 DAC Load Resistors AC−Coupling Caps are Optional Figure 14. Typical Application Circuit http://onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. 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