NUD4001DGEVB

NUD4001, NSVD4001 High Current LED Driver This device is designed to replace discrete solutions for driving LEDs in low voltage AC−DC applications 5.0 V, 12 V or 24 V. An external resistor allows the circuit designer to set the drive current for different LED arrays. This discrete integration technology eliminates individual components by combining them into a single package, which results in a significant reduction of both system cost and board space. The device is a small surface mount package (SO–8). http://onsemi.com PIN CONFIGURATION AND SCHEMATIC Features • • • • • • Supplies Constant LED Current for Varying Input Voltages External Resistor Allows Designer to Set Current – up to 500 mA Offered in Surface Mount Package Technology (SO−8) AEC−Q101 Qualified and PPAP Capable NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements Pb−Free Package is Available Benefits • • • • Vin 1 8 Iout Boost 2 7 Iout Rext 3 6 Iout GND 4 5 Iout Current Set Point Maintains a Constant Light Output During Battery Drain One Device can be used for Many Different LED Products Reduces Board Space and Component Count Simplifies Circuit and System Designs MARKING DIAGRAM Typical Applications • Portables: For Battery Back−up Applications, also Simple Ni−CAD • • Battery Charging Industrial: Low Voltage Lighting Applications and Small Appliances Automotive: Tail Lights, Directional Lights, Back−up Light, Dome Light PIN FUNCTION DESCRIPTION Pin Symbol Description 1 Vin 2 Boost This pin may be used to drive an external transistor as described in the App Note AND8198/D. 3 Rext An external resistor between Rext and Vin pins sets different current levels for different application needs 4 GND Ground 5, 6, 7, 8 Iout 8 SO−8 CASE 751 STYLE 25 8 1 1 4001 A Y WW G 4001 AYWW G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Device Positive input voltage to the device The LEDs are connected from these pins to ground ORDERING INFORMATION Package Shipping† SO−8 2500 / Tape & Reel NUD4001DR2G SO−8 (Pb−Free) 2500 / Tape & Reel NSVD4001DR2G SO−8 (Pb−Free) 2500 / Tape & Reel Device NUD4001DR2 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2011 November, 2011 − Rev. 7 1 Publication Order Number: NUD4001/D NUD4001, NSVD4001 MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Symbol Value Unit Continuous Input Voltage Vin 30 V Non−repetitive Peak Input Voltage (t v 1.0 ms) Vp 60 V Output Current (For Vdrop ≤ 2.2 V) (Note 1) Iout 500 mA Output Voltage Vout 28 V Human Body Model (HBM) ESD 1000 V Rating Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Vdrop = Vin – 0.7 V − VLEDs. THERMAL CHARACTERISTICS Characteristic Symbol Value Unit Operating Ambient Temperature TA −40 to +125 °C Maximum Junction Temperature TJ 150 °C TSTG −55 to +150 °C PD 1.13 9.0 W mW/°C Thermal Resistance, Junction–to–Ambient (Note 2) RqJA 110 °C/W Thermal Resistance, Junction–to–Lead (Note 2) RqJL 77 °C/W Storage Temperature Total Power Dissipation (Note 2) Derating above 25°C (Figure 3) 2. Mounted on FR−4 board, 2 in sq pad, 2 oz coverage. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Output Current1 (Vin = 12 V, Rext = 2.0 W, VLEDs = 10 V) Iout1 305 325 345 mA Output Current2 (Vin = 30 V, Rext = 7.0 W, VLEDs = 24 V) Iout2 95 105 115 mA Bias Current (Vin = 12 V, Rext = Open, VLEDs = 10 V) IBias − 5.0 8.0 mA Voltage Overhead (Note 3) Vover 1.4 − − V 3. Vover = Vin – VLEDs. http://onsemi.com 2 NUD4001, NSVD4001 TYPICAL PERFORMANCE CURVES (TA = 25°C unless otherwise noted) 1000 0.9 0.8 0.7 100 Rext, W Vsense (V) 0.6 10 0.5 0.4 0.3 0.2 0.1 1 1 100 10 0.0 −40 −25 −10 5 1000 IOUT (mA) 20 35 50 65 80 95 110 125 140 155 TJ, JUNCTION TEMPERATURE (°C) Figure 1. Output Current (IOUT) vs. External Resistor (Rext) Figure 2. Vsense vs. Junction Temperature 0.500 1.200 PD, POWER DISSIPATION (W) 0.450 1.000 0.400 PD_control (W) 0.800 0.600 0.400 0.350 0.300 0.250 0.200 0.150 0.100 0.200 0.050 35 45 55 65 75 85 95 105 115 125 0.000 0 5 10 15 20 25 TA, AMBIENT TEMPERATURE (°C) Vin (V) Figure 3. Total Power Dissipation (PD) vs. Ambient Temperature (TA) Figure 4. Internal Circuit Power Dissipation vs. Input Voltage 1.2 OUTPUT CURRENT, NORMALIZED 0.000 25 1.0 0.8 0.6 0.4 0.2 0.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 140 155 TJ, JUNCTION TEMPERATURE (°C) Figure 5. Current Regulation vs. Junction Temperature http://onsemi.com 3 30 NUD4001, NSVD4001 APPLICATION INFORMATION Design Guide NUD4001 Vin 1. Define LED’s current: a. ILED = 350 mA Boost 2. Calculate Resistor Value for Rext: a. Rext = Vsense (see Figure 2) / ILED b. Rext = 0.7 (TJ = 25 °C)/ 0.350 = 2.0 W Rext GND 3. Define Vin: a. Per example in Figure 6, Vin = 12 V 1 8 2 7 3 4 Current Set Point 6 5 12 V 4. Define VLED @ ILED per LED supplier’s data sheet: a. Per example in Figure 6, VLED = 3.5 V + 3.5 V + 3.5 V = 10.5 V Figure 6. 12 V Application (Series LED’s Array) 5. Calculate Vdrop across the NUD4001 device: a. Vdrop = Vin – Vsense – VLED b. Vdrop = 12 V – 0.7 V (TJ = 25 °C) – 10.5 V c. Vdrop = 0.8 V 6. Calculate Power Dissipation on the NUD4001 device’s driver: a. PD_driver = Vdrop * Iout b. PD_driver = 0.8 V x 0.350 A c. PD_driver = 0.280 Watts 7. Establish Power Dissipation on the NUD4001 device’s control circuit per Figure 4: a. PD_control = Figure 4, for 12 V input voltage b. PD_control = 0.055 W 8. Calculate Total Power Dissipation on the device: a. PD_total = PD_driver + PD_control b. PD_total = 0.280 W + 0.055 W = 0.335 W 9. If PD_total > 1.13 W (or derated value per Figure 3), then select the most appropriate recourse and repeat steps 1 through 8: a. Reduce Vin b. Reconfigure LED array to reduce Vdrop c. Reduce Iout by increasing Rext d. Use external resistors or parallel device’s configuration (see application note AND8156) 10. Calculate the junction temperaure using the thermal information on Page 7 and refer to Figure 5 to check the output current drop due to the calculated junction temperature. If desired, compensate it by adjusting the value of Rext. http://onsemi.com 4 Iout Iout Iout Iout NUD4001, NSVD4001 TYPICAL APPLICATION CIRCUITS D1 1N4004 R1 2.7 W, 1/4 W 1 Q1 R3 2.7 W, 1/4 W 8 7 2 3 NUD4001 6 5 4 Vbat + 13.5 Vdc − 1 Q2 8 7 3 NUD4001 6 2 5 4 R4 32 W, 5.0 W R2 32 W, 5.0 W R3 6.7 W, 4.0 W LED1 Luxeon Emitter 550 mA 0 Figure 7. Stop light automotive circuit using the NUD4001 device to drive one high current LED (550 mA). D1 1N4004 R1 7.0 W, 1/4 W 1 2 Q1 R2 7.0 W, 1/4 W 8 7 3 NUD4001 6 4 5 1 Q2 8 7 3 NUD4001 6 2 4 5 Vbat + 13.5 Vdc − R3 27 W, 2.0 W LED1 Luxeon Emitter 220 mA 0 Figure 8. Dome light automotive circuit using the NUD4001 device to drive one LED (220 mA). http://onsemi.com 5 NUD4001, NSVD4001 1 Rext1 2.0 W, 1/4 W Q1 8 7 3 NUD4001 6 2 5 4 Rext2 110 k, 1/4 W LED1 LXHL−MW1D Vbat + 12 Vdc − LED2 LXHL−MW1D Q2 2N2222 LED3 LXHL−MW1D PWM 0 Figure 9. NUD4001 Device Configuration for PWM D1 MURA105T3 D2 MURA105T3 R2 2.0 W, 1/4 W 1 8 7 3 NUD4001 6 2 4 12 Vac from: 60 Hz Transformer or Electronic Transformer Q2 5 C1 220 mF LED1 Luxeon Emitter 350 mA LED2 Luxeon Emitter 350 mA D3 MURA105T3 D4 MURA105T3 LED3 Luxeon Emitter 350 mA 0 Figure 10. 12 Vac landscape lighting application circuit using the NUD4001 device to drive three 350 mA LEDs. http://onsemi.com 6 NUD4001, NSVD4001 THERMAL INFORMATION NUD4001, NSVD4001 Power Dissipation reduce the thermal resistance. Figure 11 shows how the thermal resistance changes for different copper areas. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad®. Using a board material such as Thermal Clad or an aluminum core board, the power dissipation can be even doubled using the same footprint. The power dissipation of the SO−8 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RqJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SO−8 package, PD can be calculated as follows: 180 160 T * TA PD + Jmax RqJA 140 qJA (°C/W) The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 1.13 W. 120 100 PD + 150° C * 25° C + 1.13 W 110° C 80 The 110°C/W for the SO−8 package assumes the use of a FR−4 copper board with an area of 2 square inches with 2 oz coverage to achieve a power dissipation of 1.13 W. There are other alternatives to achieving higher dissipation from the SOIC package. One of them is to increase the copper area to 60 0 1 2 3 4 5 6 7 8 10 9 BOARD AREA (in2) Figure 11. qJA versus Board Area 250 1S −36.9 sq. mm −0.057 in sq. 1S −75.8 sq. mm −0.117 in sq. 200 R(q) (C°/W) 1S −150.0 sq. mm −0.233 in sq. 150 1S −321.5 sq. mm −0.498 in sq. 1S −681.0 sq. mm −1.056 in sq. 100 1S −1255.0 sq. mm −1.945 in sq. 50 0 0.000001 0.00001 0.0001 0.001 0.1 0.01 1 TIME (sec) Figure 12. Transient Thermal Response Thermal Clad is a registered trademark of the Bergquist Company. http://onsemi.com 7 10 100 1000 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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