7052L20PFG8

7052S/L HIGH-SPEED 2K x 8 FourPortTM STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 20/25/35ns (max.) – Industrial: 25ns (max.) – Military: 35ns (max.) Low-power operation – IDT7052S Active: 750mW (typ.) Standby: 7.5mW (typ.) – IDT7052L Active: 750mW (typ.) Standby: 1.5mW (typ.) True FourPort memory cells which allow simultaneous access of the same memory locations Fully asynchronous operation from each of the four ports: P1, P2, P3, P4 Versatile control for write-inhibit: separate BUSY input to control write-inhibit for each of the four ports ◆ ◆ ◆ ◆ ◆ Battery backup operation—2V data retention TTL-compatible; single 5V (±10%) power supply Available in 120 pin Thin Quad Flatpacks and 108 pin PGA Military product compliant to MIL-PRF-38535 QML Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information Description The IDT7052 is a high-speed 2K x 8 FourPort™ Static RAM designed to be used in systems where multiple access into a common RAM is required. This FourPort Static RAM offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. The IDT7052 is also designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those Functional Block Diagram R/WP1 CEP1 R/WP4 CEP4 OEP1 OEP4 I/O0P1-I/O7P1 COLUMN I/O COLUMN I/O BUSYP1 A0P1 - A10P1 A0P2 - A10P2 BUSYP4 PORT 1 ADDRESS DECODE LOGIC MEMORY ARRAY PORT 2 ADDRESS DECODE LOGIC PORT 4 ADDRESS DECODE LOGIC A0P4 - A10P4 PORT 3 ADDRESS DECODE LOGIC A0P3 - A10P3 BUSYP2 I/O0P2-I/O7P2 I/O0P4-I/O7P4 BUSYP3 COLUMN I/O COLUMN I/O I/O0P3-I/O7P3 OEP2 OEP3 CEP2 R/WP2 CEP3 R/WP3 2674 drw 01 JULY 2019 1 DSC 2674/17 7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when all ports simultaneously access the same FourPort RAM location. The IDT7052 provides four independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the user’s responsibility to ensure data integrity when simultaneously accessing the same memory location from all ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low power standby power mode. Fabricated using CMOS high-performance technology, this FourPort SRAM typically operates on only 750mW of power. Low-power (L) versions offer battery backup data retention capability, with each port typically consuming 50µW from a 2V battery. The IDT7052 is packaged in a ceramic 108-pin Pin Grid Array (PGA) and 120-pin Thin Quad Flatpack (TQFP). Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. Pin Configurations(1,2,3) 81 80 R/W P2 84 77 83 BUSY P2 87 78 OE P2 90 88 A5 P1 92 91 95 103 104 105 107 108 58 A6 P3 2 31 4 8 VCC 7 I/O0 P2 6 10 I/O2 P2 NC I/O1 P2 A B C I/O3 P2 17 VCC 13 I/O4 P2 11 9 I/O5 P1 12 GND 21 VCC 16 I/O6 P2 14 25 GND 19 I/O1 P3 15 22 I/O3 P3 18 24 I/O5 P3 20 I/O5 P2 I/O7 P2 I/O0 P3 I/O2 P3 E F G H 23 I/O4 P3 06 R/W P4 05 BUSY P4 04 33 I/O5 P4 I/O6 P4 03 30 I/O3 P4 26 I/O6 P3 A9 P4 36 I/O7 P4 29 I/O7 P3 07 38 OE P4 32 I/O2 P4 A8 P4 41 34 28 VCC 08 NC GND I/O6 P1 A10 P4 42 37 GND GND 5 3 35 09 A7 P4 40 CE P4 A5 P4 45 A6 P4 43 39 108-Pin PGA Top View(5) 10 47 46 GND 11 A2 P4 A3 P4 A4 P4 106 I/O7 P1 49 44 BUSY P3 A1 P4 A0 P4 12 50 51 48 1 OE P3 CE P3 R/W P3 53 56 55 IDT7052G GU108(4) 54 NC A8 P3 A9 P3 I/O0 P1 I/O3 P1 I/O4 P1 59 A10 P3 102 I/O1 P1 I/O2 P1 62 A2 P3 57 A7 P3 52 CE P1 OE P1 BUSY P1 61 A4 P3 98 100 101 66 A2 P2 VCC NC R/W P1 71 A6 P2 64 A1 P3 60 A5 P3 93 97 99 75 A9 P2 67 A1 P2 63 A3 P3 A4 P1 A7 P1 A9 P1 79 70 A4 P2 65 A0 P3 89 94 96 73 A10 P2 68 A0 P2 A0 P1 A6 P1 A8 P1 69 A3 P2 85 A3 P1 A10 P1 76 CE A1 P1 72 A5 P2 A8 P2 82 86 A2 P1 74 A7 P2 NC I/O4 P4 02 27 I/O0 P4 I/O1 P4 L M 01 , D J K 2674 drw 02 INDEX NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately 1.21 in x 1.21 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 2 6.42 7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges N/C N/C BUSYP3 A0P4 A1P4 A2P4 A3P4 A4P4 A5P4 A6P4 A10P4 GND A7P4 A8P4 A9P4 N/C CEP4 R/WP4 OEP4 BUSYP4 GND I/O7P4 I/O6P4 I/O5P4 GND I/O4P4 I/O3P4 I/O2P4 N/C N/C Pin Configurations(1,2,3) (con't.) INDEX 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 91 92 59 58 93 94 57 95 56 96 55 97 54 98 53 99 52 51 100 50 101 102 49 103 48 104 47 105 46 7052 106 45 PNG120(4) 44 107 108 43 109 42 110 41 111 40 112 39 113 38 114 37 115 36 116 35 117 34 118 33 119 32 120 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 N/C N/C OEP2 BUSYP2 A0P1 A1P1 A2P1 A3P1 A4P1 A5P1 A6P1 A10P1 VCC A7P1 A8P1 A9P1 N/C CEP1 R/WP1 OEP1 BUSYP1 I/O0P1 I/O1P1 I/O2P1 I/O3P1 GND I/O4P1 I/O5P1 N/C N/C R/WP3 CEP3 OEP3 N/C A9P3 A8P3 A7P3 A10P3 A6P3 A5P3 A4P3 A3P3 A2P3 A1P3 A0P3 N/C A0P2 A1P2 A2P2 A3P2 A4P2 A5P2 A6P2 A10P2 A7P2 A8P2 A9P2 N/C R/WP2 CEP2 NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. PNG120 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 3 6.42 N/C I/O1P4 I/O0P4 VCC I/O7P3 I/O6P3 I/O5P3 GND I/O4P3 I/O3P3 I/O2P3 VCC I/O1P3 I/O0P3 N/C I/O7P2 I/O6P2 VCC I/O5P2 I/O4P2 I/O3P2 GND I/O2P2 I/O1P2 I/O0P2 VCC N/C I/O7P1 I/O6P1 N/C 2674 drw 04 7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2) Symbol Absolute Maximum Ratings(1) Symbol Pin Name Rating A0 P1 - A10 P1 Address Lines - Port 1 A0 P2 - A10P2 Address Lines - Port 2 A0 P3 - A10 P3 Address Lines - Port 3 A0 P4 - A10 P4 Address Lines - Port 4 I/O0 P1 - I/O7 P1 Data I/O - Port 1 I/O0 P2 - I/O7 P2 Data I/O - Port 2 I/O0 P3 - I/O7 P3 Data I/O - Port 3 I/O0 P4 - I/O7 P4 Data I/O - Port 4 R/W P1 Read/Write - Port 1 R/W P2 Read/Write - Port 2 R/W P3 Read/Write - Port 3 R/W P4 Read/Write - Port 4 GND Ground CE P1 Chip Enable - Port 1 CE P2 Chip Enable - Port 2 CE P3 Chip Enable - Port 3 CE P4 Chip Enable - Port 4 OE P1 Output Enab le - Port 1 OE P2 Output Enab le - Port 2 Military OE P3 Output Enab le - Port 3 Commercial OE P4 Output Enab le - Port 4 Industrial BUSY P1 Write Disable - Port 1 BUSY P2 Write Disable - Port 2 BUSY P3 Write Disable - Port 3 BUSY P4 Write Disable - Port 4 VCC Power Terminal Voltage with Respect to GND -0.5 to +7.0 -0.5 to +7.0 V TBIAS Temperature Under Bias -55 to +125 -65 to +135 o C TSTG Storage Temperature -65 to +150 -65 to +150 o C IOUT DC Output Current 50 50 Maximum Operating Temperature and Supply Voltage(1) Grade (2) Ambient Temperature GND Vcc -55OC to+125OC 0V 5.0V + 10% 0OC to +70OC 0V 5.0V + 10% -40 C to +85 C 0V 5.0V + 10% O O NOTE: 1. This is the parameter TA. This is the "instant on" case temperature. 2674 tbl 01 Conditions Max. Unit Input Capacitance VIN = 0V 9 pF VOUT = 0V 10 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and the output signals switch from 0V to 3V or from 3V to 0V. pF 2674 tbl 04 Recommended DC Operating Conditions Symbol Parameter Output Capacitance mA 2674 tbl 02 (TA = +25°C, f = 1.0MHz) TQFP only COUT Unit VTERM(2) Capacitance(1) CIN Military NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%. NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply Symbol Commercial & Industrial Parameter 4 6.42 Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V V VCC Supply Voltage GND Ground VIH Input High Voltage 2.2 ____ 6.0(2) VIL Input Low Voltage -0.5(1) ____ 0.8 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. 2674 tbl 03 Min. V 2674 tbl 05 7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,5) (VCC = 5.0V ± 10%) 7052X20 Com'l Only Symbol ICC1 ICC2 ISB ISB1 Parameter Condition Operating Power Supply Current (All Ports Active) CE = VIL Outputs Disabled f = 0(3) Dynamic Operating Current (All Ports Active) CE = VIL Outputs Disabled f = fMAX(4) Standby Current (All Ports - TTL Level Inputs) CE = VIH f = fMAX(4) Full Standby Current (All Ports - All CMOS Level Inputs) All Ports CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3) Version 7052X25 Com'l, Ind & Military 7052X35 Com'l & Military Typ.(2) Max. Typ. (2) Max. Typ. (2) Max. Unit mA COM'L. S L 150 150 300 250 150 150 300 250 150 150 300 250 MIL. & IND. S L ____ ____ ____ ____ 150 150 360 300 150 150 360 300 COM'L. S L 240 210 370 325 225 195 350 305 210 180 335 290 MIL. & IND. S L ____ ____ ____ ____ 225 195 400 340 210 180 395 330 COM'L. S L 70 60 95 80 45 40 85 70 40 35 75 60 MIL. & IND. S L ____ ____ ____ ____ 45 40 115 85 40 35 110 80 COM'L. S L 1.5 0.3 15 1.5 1.5 0.3 15 1.5 1.5 0.3 15 1.5 MIL. & IND. S L ____ ____ ____ ____ 1.5 0.3 30 4.5 1.5 0.3 30 4.5 mA mA mA 2674 tbl 06 NOTES: 1. 'X' in part number indicates power rating (S or L). 2. VCC = 5V, TA = +25°C and are not production tested. 3. f = 0 means no address or control lines change. 4. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 5. For the case of one port, divide the appropriate current above by four. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 7052S Symbol Parameter Min. Max. Min. Max. Unit VCC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA Output Leakage Current CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA VOL Output Low Voltage IOL = 4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ |ILI| (1) Input Leakage Current |ILO| Test Conditions 7052L V 2674 tbl 07 NOTE: 1. At Vcc < 2.0V input leakages are undefined. 5 6.42 7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Data Retention Characteristics Over All Temperature Ranges(4) (L Version Only) VLC = 0.2V, VHC = VCC - 0.2V Symbol Parameter Test Condition Min. Typ. (1) Max. Unit 2.0 ___ ___ V 25 600 µA VDR VCC for Data Retention VCC = 2V ICCDR Data Retention Current CE > VHC Com'l. ___ VIN > VHC or < VLC Mil. & Ind. ___ 25 1800 0 ___ ___ ns ___ ___ ns tCDR (3) (3) tR Chip Deselect to Data Retention Time (2) Operation Recovery Time tRC 2674 tbl 08a NOTES: 1. VCC = 2V, TA = +25°C 2. tRC = Read Cycle Time 3. This parameter is guaranteed but not production tested. 4. Industrial temperature: For other speeds, packages and powers contact your sales office. Low VCC Data Retention Waveform DATA RETENTION MODE VCC VDR ≥ 2V 4.5V 4.5V tCDR CE tR VDR VIH VIH 2674 drw 05 AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5V 5ns Max. 1.5V 5V 893Ω 1.5V DATAOUT Figures 1 and 2 347Ω 893Ω DATAOUT 30pF 347Ω 5pF* 2674 tbl 08b 2674 drw 06 Figure 1. AC Output Test Load 6 6.42 Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) *Including scope and jig 7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(3) 7052X20 Com'l Only Symbol Parameter 7052X25 Com'l, Ind & Military 7052X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ 35 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ns tACE Chip Enable Access Time ____ 20 ____ 25 ____ 35 ns tAOE Output Enable Access Time ____ 10 ____ 15 ____ 25 ns tOH Output Hold from Address Change 0 ____ 0 ____ 0 ____ ns tLZ Output Low-Z Time (1,2) 5 ____ 5 ____ 5 ____ ns tHZ (1,2) ____ 12 ____ 15 .____ 15 ns 0 ____ 0 ____ 0 ____ ns ____ 20 ____ 25 ____ 35 ns tPU tPD Output High-Z Time Chip Enable to Power Up Time (2) Chip Disable to Power Down Time (2) 2674 tbl 09 NOTES: 1. Transition is measured 0mV from Low or High-Impedance voltage with the Output Test Load (Figure 2) 2. This parameter is guaranteed by device characterization but is not production tested. 3. 'X' in part number indicates power rating (S or L) Timing Waveform of Read Cycle No. 1, Any Port(1) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATA VALID DATA VALID 2674 drw 07 NOTE: 1. R/W = VIH, OE = VIL and CE = VIL. Timing Waveform of Read Cycle No. 2, Any Port(1,2) tACE CE tAOE tHZ OE tLZ DATAOUT tHZ VALID DATA tLZ tPU tPD ICC CURRENT 50% 50% ISB NOTES: 1. R/W = VIH for Read Cycles. 2. Addresses valid prior to or coincident with CE transition LOW. 2674 drw 08 7 6.42 7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(7) 7052X20 Com'l Only Symbol Parameter 7052X25 Com'l & Military 7052X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit 20 ____ 25 ____ 35 ____ ns tEW Chip Enable to End-of-Write (3) 15 ____ 20 ____ 30 ____ ns tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width(3) 15 ____ 20 ____ 30 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 15 ____ 15 ____ 20 ____ ns ____ 15 ____ 15 ____ 15 ns 0 ____ 0 ____ 0 ____ ns ____ 12 ____ 15 ____ 15 ns 0 ____ 0 ____ 0 ____ ns ____ 35 ____ 45 ____ 55 ns ____ 30 ____ 35 ____ 45 ns WRITE CYCLE tWC Write Cycle Time (1,2) tHZ Output High-Z Time tDH Data Hold Time tWZ Write Enable to Output in High-Z(1,2) tOW tWDD tWDD Output Active from End-of-Write Write Pulse to Data Delay (1,2) (4) Write Data Valid to Read Data Delay (4) BUSY INPUT TIMING tWB Write to BUSY(5) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(6) 15 ____ 15 ____ 20 ____ ns 2674 tbl 10 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Specified for OE = VIH (refer to “Timing Waveform of Write Cycle”, Note 8). 4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”. 5. To ensure that the write cycle is inhibited on port "A" during contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port. 6. To ensure that a write cycle is completed on port "A" after contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port. 7. 'X' in part number indicates power rating. 8 6.42 7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5,8) tWC ADDRESS (6) tAS OE tAW tWR (3) (9) CE tHZ tWP (2) (7) R/W tWZ (7) tLZ tHZ tOW (4) (4) DATAOUT (7) tDW tDH DATAIN 2674 drw 09 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5) tWC ADDRESS tAW CE (9) (6) tAS tEW(2) tWR (3) R/W tDW tDH DATAIN 2674 drw 10 NOTES: 1. R/W or CE = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL. 3. tWR is measured from the earlier of CE or R/W = VIH to the end of write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed but is not production tested. 8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9 6.42 7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read(1,2,3) tWC MATCH ADDR"A" tWP R/W"A" tDW DATAIN"A" tDH VALID ADDR"B" MATCH tWDD DATA"B" VALID tDDD NOTES: 1. Assume BUSY input = VIH and CE = VIL for the writing port. 2. OE = VIL for the reading ports. 3. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port. 2674 drw 11 Timing Waveform of Write with BUSY Input tWP R/W"A" tWH tWB BUSY"B" R/W"B" (1) , NOTE: 1. BUSY is asserted on Port "B" blocking R/W"B" until BUSY"B" goes HIGH. Functional Description 2674 drw 12 The IDT7052 provides four ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port’s OE turns on the output drivers when set LOW. READ/ WRITE conditions are illustrated in the table below. Truth Table I – Read/Write Control(3) Any Port(1) R/W CE OE D0-7 X H X Z Port Deselected: Power-Down X H X Z CEP1 =CEP2 =CEP3=CEP4=VIH Power Down Mode ISB or ISB1 L L X DATAIN H L L DATAOUT X X H Z Function Data on port written into memory (2) Data in memory output on port Outputs Disabled 2674 tbl 11 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don’t Care, "Z "= High Impedance 2. If BUSY = VIL, write is blocked. 3. For valid write operation, no more than one port can write to the same address location at the same time. 10 6.42 7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Ordering Information A XXXX A 999 A Device Type Power Speed Package A A Process/ Temperature Range Blank 8 Tray Tape and Reel Blank I(1) B Commercial (0°C to +70°C) Industrial (-40°C to +85°C Military (-55°C to +125°C) Compliant to MIL-PRF-38535 QML G(2) Green G PF 108-Pin Pin Grid Array (GU108) 120-Pin Thin Quad Plastic Flatpack (PNG120) 20 25 35 Commercial Only Commercial & Industrial Commercial & Military L S Low Power Standard Power 7052 16K (2K x 8) FourPort RAM Speed in nanoseconds 2674 drw 13 NOTES: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. Orderable Part Information Speed (ns) 20 25 35 Pkg. Code Pkg. Type Temp. Grade Speed (ns) GU108 PGA C 20 7052L20PFG PNG120 TQFP C 7052L20PFG8 PNG120 TQFP C GU108 PGA C 7052L25PFGI PNG120 TQFP I 7052L25PFGI8 Orderable Part ID 7052L20G 7052L25G PNG120 TQFP I 7052L35G GU108 PGA C 7052L35GB GU108 PGA M 11 6.42 Pkg. Code Pkg. Type Temp. Grade 7052S20G GU108 PGA C 25 7052S25G GU108 PGA C 35 7052S35G GU108 PGA C 7052S35GB GU108 PGA M Orderable Part ID 7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Datasheet Document History 01/18/99: 06/04/99: 11/10/99: 11/18/99: 05/23/00: 10/22/01: 07/24/06: 01/19/09: 02/05/15: 07/08/16: 06/07/18: 07/11/19: Initiated datasheet document history Converted to new format Cosmetic typographical corrections Added additional notes to pin configurations Changed drawing format Page1 Corrected DSC number Replaced IDT logo Page 10 Fixed typo in caption for BUSY Input waveform Page 4 Increased storage temperature parameter Clarified TA parameter Page 5DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes Pages 2 & 3 Added date revision for pin configurations Page 5, 7 & 8 Added Industrial temp to column heading for 25ns speed to DC & AC Electrical Characteristics Page 11 Added Industrial temp offering to 25ns ordering information Page 4, 5, 7 & 8 Removed Industrial temp footnote from all tables Page 1 & 11 Replace TM logo with ® logo Page 1 Added green availability to features Page 11 Added green indicator to ordering information Page 11 Removed "IDT" from orderable part number Page 2 Removed IDT in reference to fabrication Page 2,3 & 11 The package codes G108-1 & PN120-1changed to G108 & PN120 respectively to match standard package codes Page 11 Added Tape and Reel to Ordering Information Page 1&3 Removed 132-pin PQF offering from the Features & the pin configuration Page 11 Removed the 132-pin PQF package from the Ordering Information Page 3 Changed diagram for the PN120 pin configuration by rotating package pin labels and pin numbers 90 degrees counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1 Added the IDT logo to the PN120 pin configurations and changed the text to be in alignment with new diagram marking specs and removed the date revision indicator from all pin configurations Updated footnote references for PN120 pin configuration by removing footnote 4 & 5 Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Page 2 & 3 Updated package codes G108 to GU108 and PN180 to PNG180 Page 11 Added Orderable Part Information tables CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 12 6.42 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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