840001BGI-25LF

840001I-25 FemtoClock® LVCMOS/LVTTL Clock Generator Data Sheet GENERAL DESCRIPTION FEATURES The 840001I-25 is a General Purpose Clock Generator and a member of the family of high performance devices from IDT. The 840001I-25 can accept frequency from a 22.4MHz to 170MHz and generate a 22.4MHz to 170MHz output. The 840001I-25 has excellent phase jitter performance, from 637kHz – 10MHz integration range. The 840001I-25 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • One LVCMOS/LVTTL output, 15Ω output impedence • Output frequency range: 22.4MHz – 170MHz • VCO range: 560MHz to 680MHz • RMS phase jitter @ 125MHz (637kHz - 10MHz): 0.36ps (typical) • Full 3.3V or 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package COMMONLY USED FREQUENCY TABLE Inputs M Divider Output Frequency (MHz) SEL2 SEL1 SEL0 N Divider REF_IN (MHz) Q 0 0 0 25 0 0 1 10 25 25 25 25 62.5 0 1 0 4 25 25 156.25 25 0 1 1 5 25 125 25 1 0 0 10 10 62.5 62.5 1 0 1 5 5 125 125 1 1 0 4 4 156.25 156.25 1 1 1 10 25 62.5 25 (default) BLOCK DIAGRAM PIN ASSIGNMENT N REF_IN Pullup Phase Detector VCO 560-680MHz ÷4 ÷5 ÷10 ÷25 Q 8 7 6 5 Q VDDO GND SEL_2 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View 3 ©2016 Integrated Device Technology, Inc 1 2 3 4 840001I-25 M ÷4, ÷5, ÷10, ÷25 SEL_[0:2] Pullup VDD REF_IN SEL_0 SEL_1 1 Revision A January 15, 2016 840001I-25 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name 1 V Power 2 REF_IN Input DD Type Description Positive supply pin. Pullup Reference input frequency. LVCMOS/LVTTL interface levels. Pullup M and N configuration select pins. LVCMOS/LVTTL interface levels. 3, 4, 5 SEL_0, SEL_1, SEL_2 Input 6 GND Power Power supply ground. Power Output supply pin. Output Single-ended clock output. LVCMOS/LVTTL interface levels. 15Ω output impedance. 7 V 8 DDO Q NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP ROUT Test Conditions Minimum Typical Maximum Units 4 pF VDD, VDDO = 3.465V 6 pF VDD, VDDO = 2.625V 5 pF Input Pullup Resistor 51 kΩ Output Impedance 15 Ω ©2016 Integrated Device Technology, Inc 2 Revision A January 15, 2016 840001I-25 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 129.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD VDDO Positive Supply Voltage 3.135 3.3 3.465 V Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 83 mA IDDO Output Supply Current 2 mA No Load TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO =2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Positive Supply Voltage Test Conditions 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 80 mA IDDO Output Supply Current 2 mA No Load TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 REF_IN, SEL_[0:2] REF_IN, SEL_[0:2] Test Conditions Minimum Maximum Units VDD = 3.465V 2 Typical VDD + 0.3 V VDD = 2.625V 1.7 VDD + 0.3 V VDD = 3.465V -0.3 0.8 V VDD = 2.625V -0.3 0.7 V 5 µA VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -150 µA VDDO = 3.465V 2.6 V VDDO = 2.625V 1.8 V VDDO = 3.465V or 2.625V 0.6 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, “Output Load Test Circuit” diagrams. ©2016 Integrated Device Technology, Inc 3 Revision A January 15, 2016 840001I-25 Data Sheet TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 22.4 125MHz, Integration Range: 637kHz - 10MHz 156.25MHz, Integration Range: 637kHz - 10MHz 20% to 80% Maximum Units 170 MHz 0.37 ps 0.38 ps 150 650 ps 47 53 % Maximum Units 170 MHz NOTE 1: Please refer to the Phase Noise Plot. TABLE 4B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 22.4 125MHz, Integration Range: 637kHz - 10MHz 156.25MHz, Integration Range: 637kHz - 10MHz 20% to 80% 0.36 ps 0.35 ps 150 650 ps 47 53 % NOTE 1: Please refer to the Phase Noise Plot. ©2016 Integrated Device Technology, Inc 4 Revision A January 15, 2016 840001I-25 Data Sheet TYPICAL PHASE NOISE AT 125MHZ @ 3.3V 125MHz ➤ RMS Phase Jitter (Random) 637kHz to 10MHz = 0.37ps (typical) NOISE POWER dBc Hz Filter Raw Phase Noise Data ➤ ➤ Phase Noise Result by adding a Filter to raw data OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V 156.25MHz NOISE POWER dBc Hz ➤ RMS Phase Jitter (Random) 637kHz to 10MHz = 0.38ps (typical) Filter Raw Phase Noise Data ➤ ➤ Phase Noise Result by adding a Filter to raw data OFFSET FREQUENCY (HZ) ©2016 Integrated Device Technology, Inc 5 Revision A January 15, 2016 840001I-25 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT 80% 80% 20% 20% Q RMS PHASE JITTER tR tF OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ©2016 Integrated Device Technology, Inc 6 Revision A January 15, 2016 840001I-25 Data Sheet APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: LVCMOS CONTROL PINS: All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ©2016 Integrated Device Technology, Inc 7 Revision A January 15, 2016 840001I-25 Data Sheet POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 840001I-25. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 840001I-25 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and Output Power Dissipation • Power (core, output) = VDD_MAX * (IDD + IDDO) = 3.465V * (83mA + 2mA) = 294.5mW LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 15Ω)] = 26.6mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15Ω * (26.6mA)2 = 10.6mW per output • Dynamic Power Dissipation at 156.25MHz Power (156.25MHz) = CPD * Frequency * (VDDO)2 = 6pF * 156.25MHz * (3.465V)2 = 11.26mW per output Total Power Dissipation • Total Power = Power (core, output) + Power Dissipation (ROUT) + Dyamic Power Dissipation (156.25MHz) = 294.5mW + 10.6mW + 11.26mW = 316.4mW ©2016 Integrated Device Technology, Inc 8 Revision A January 15, 2016 840001I-25 Data Sheet 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1meter per second and a multi-layer board, the appropriate value is 125.5°C/W per Table 5. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.316W * 125.5°C/W = 124.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (multi-layer). TABLE 5. THERMAL RESISTANCE θJA FOR 8-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Meters Per Second) Multi-Layer PCB, JEDEC Standard Test Boards ©2016 Integrated Device Technology, Inc 0 1 2.5 129.5°C/W 125.5°C/W 123.5°C/W 9 Revision A January 15, 2016 840001I-25 Data Sheet RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters Per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 129.5°C/W 125.5°C/W 123.5°C/W TRANSISTOR COUNT The transistor count for 840001I-25 is: 2588 PACKAGE OUTLINE AND PACKAGE DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 ©2016 Integrated Device Technology, Inc 10 Revision A January 15, 2016 840001I-25 Data Sheet TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package 840001BGI-25LF BI25L 840001BGI-25LFT BI25L ©2016 Integrated Device Technology, Inc Shipping Packaging Temperature 8 lead “Lead Free” TSSOP tube -40°C to 85°C 8 lead “Lead Free” TSSOP tape & reel -40°C to 85°C 11 Revision A January 15, 2016 840001I-25 Data Sheet REVISION HISTORY SHEET Rev A A Table Page T8 11 T8 1 11 Description of Change Date Ordering Information - removed leaded devices. Updated data sheet format. General Description - removed Hiperclocks. Ordering Information - removed Lead Free note below the table. Updated header and footer. ©2016 Integrated Device Technology, Inc 12 7/29/15 1/15/16 Revision A January 15, 2016 840001I-25 Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.