IDTCV183-2APAG8

IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FEATURES: KEY FEATURES OUTPUTS: KEY SPECIFICATIONS: • • • • • • • Compliant with Intel CK505 Gen II spec One high precision PLL for CPU, SSC and N programming One high precision PLL for SRC, SSC and N programming One high precision PLL for SATA/PCI, and SSC One high precision PLL for 96MHz/48MHz Push-pull IOs for differential outputs Support spread spectrum modulation, –0.5 down spread and others • Support SMBus block read/write, byte read/write • Available in TSSOP package • • • • • • • • • Internal serial resistor can be enabled by SMBus control register B19b7 to save the board space and material cost • Direct CPU and SRC clock frequency programming—write the Hex number into Byte [16:18], 1 MHz stepping. • Linear and smooth transition for the CPU and SRC frequency programming. • Four Power On hardware modes – see page 6, CFG configuration table 2. • When CFG[1:0] = 11, SATA clock power on default is from SRC PLL. 2*0.7V differential CPU CLK pair 10*0.7V differential SRC CLK pair One CPU_ITP/SRC differential clock pair One SRC0/DOT96 differential clock pair 6*PCI, 33.3MHz 1*48MHz 1*REF 1*SATA • • • • CPU/SRC CLK cycle to cycle jitter < 85ps PCI CLK cycle to cycle jitter < 500ps All SRC, SRC[0:11] phase noise < 3.10s RMS, PCIE Gen II SRC3, 4, 6, 7, designated PCIE Gen II outputs, nominal interpair skew = 0 ps IDTCV183-2A is not recommended for new designs. LTB for the -2A product is 10/28/2014. Refer to PDN CQ-13-02. Replacement part is 9LRS3165. FUNCTIONAL BLOCK DIAGRAM REF XTAL_IN XTAL Osc Amp PLL1 SSC N Programmable XTAL_OUT SDATA SCLK SM Bus Controller CPU[1:0] CPU Output Buffer Stop Logic PLL3 SSC SRC1/SE PCI/SATA SRC CLK Output Buffer Stop Logic PLL4 SSC N Programmable CKPWRGD/PD# CPU_ITP/SRC8 SRC CLK Output Buffer Stop Logic PCI[4:0], PCIF5 SATA/SRC2 SRC[7:3], [11:9] CPU_STOP# PCI_STOP# SRC5_EN, TME Control Logic 48MHz Fixed PLL PLL2 ITP_EN 48MHz/96MHz Output BUffer DOT96/SRC0 CR_[H:A]# FSC,B,A COMMERCIAL TEMPERATURE RANGE JANUARY, 2014 1 © 2014 Integrated Device Technology, Inc. DSC 7030/4 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION PCI0/CR#_A 1 64 SCL VDD_PCI 2 63 SDA PCI1/CR#_B 3 62 REF/FSC/TEST_SEL PCI2/TME 4 61 VDD_REF PCI3/CFGP 5 60 XTAL_IN PCI4/SRC5_EN 6 59 XTAL_OUT PCIF5/ITP_EN 7 58 VSS_REF VSS_PCI 8 57 FSB/TEST_MODE VDD_48MHz 9 56 CKPWRGD/PD# USB_48/FSA 10 55 VDD_CPU VSS_48MHz 11 54 CPUT0 VDD_IO 12 53 CPUC0 DOT96T/SRCT0 13 52 VSS_CPU DOT96C/SRCC0 14 51 CPUT1 VSS_IO 15 50 CPUC1 VDD_PLL3 16 49 VDD_CPU_IO SRCT1/SE1 17 48 IO_VOUT SRCC1/SE2 18 47 SRCT8/CPU_ITPT VSS_PLL3 19 46 SRCC8/CPU_ITPC VDD_PLL3_IO 20 45 VDD_SRC_IO SATAT/SRCT2 21 44 SRCT7/CR#_F SATAC/SRCC2 22 43 SRCC7/CR#_E VSS_SRC 23 42 VSS_SRC SRCT3/CR#_C 24 41 SRCT6 SRCC3/CR#_D 25 40 SRCC6 VDD_SRC_IO 26 39 VDD_SRC SRCT4 27 38 PCI_STOP#/SRCT5 SRCC4 28 37 CPU_STOP#/SRCC5 VSS_SRC 29 36 VDD_SRC_IO SRCT9 30 35 SRCC10 SRCC9 31 34 SRCT10 SRCC11/CR#_G 32 33 SRCT11/CR#_H TSSOP TOP VIEW 2 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Pin # 1 Name PCI0/CR#_A Type I/O 2 3 VDD_PCI PCI1/CR#_B PWR I/O 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PCI2/TME PCI3/CFGP PCI4/SRC5_EN PCIF5/ITP_EN VSS_PCI VDD_48 USB 48/FS_A VSS_48 VDD_IO SRCT0/DOT96T SRCC0/DOT96C VSS_IO VDD_PLL3 SRCT1/SE1 SRCC1/SE2 VSS_PLL3 VDD_PLL3_IO SATAT/SRCT2 SATAC/SRCC2 VSS_SRC SRCT3/CR#_C I/O OUT I/O I/O GND PWR I/O GND PWR OUT OUT GND PWR OUT OUT GND PWR OUT OUT GND I/O 25 SRCC3/CR#_D I/O 26 27 28 29 30 31 32 VDD_SRC_IO SRCT4 SRCC4 VSS_SRC SRCT9 SRCC9 SRCC11/CR#_G PWR OUT OUT GND OUT OUT I/O 33 SRCT11/CR#_H I/O 34 35 36 37 38 39 40 41 42 SRCT10 SRCC10 VDD_SRC_IO CPU_Stop#/SRCC5 PCI_Stop#/SRCT5 VDD_SRC SRCC6 SRCT6 VSS_SRC OUT OUT PWR I/O I/O PWR OUT OUT GND Description 33.33MHz. SRC0, 2 Differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode is selected by SMBus control register. Default is PCI clock mode. 3.3V 33.33MHz. SRC1, 4 Differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode is selected by SMBus control register. Default is PCI clock mode. 33.33MHz. Trust mode enable. HIGH = overclocking disabled. Power-on latch. 33.33MHz. Clock configuration bit, combined with pin 4 (see CFG Table), power on latch 33.33MHz. Pin 37, 38 mode selection. Power on latch, HIGH = SRC5, LOW = CPU and PCI Stop#. 33.33MHz. Pin 46, 47 mode selection. Power on latch, HIGH = CPU_ITP, LOW = SRC8. GND 3.3V 48MHz, frequency select, power on latch GND 0.8V Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0. Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0. GND 3.3V Differential or single end clock output. Mode selected by SMBus control register. Default is SRC1. Differential or single end clock output. Mode selected by SMBus control register. Default is SRC1. GND 0.8V Differential output clock Differential output clock GND SRC clock. SRC differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode selected by SMBus control register. Default is SRC3. SRC clock. SRC differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode selected by SMBus control register. Default is SRC3. 0.8V Differential output clock Differential output clock GND Differential output clock Differential output clock SRC clock. SRC differential clock output enable, control SRC9, 0 = enable. Mode selected by SMBus control register. Default is SRC11. SRC clock. SRC differential clock output enable, control SRC10, 0 = enable. Mode selected by SMBus control register. Default is SRC11. Differential output clock Differential output clock 0.8V CPU stop, LOW = stop. SRC clock. Mode selected by pin6, SRC5_EN. PCI stop, LOW = stop. SRC clock. Mode selected by pin6, SRC5_EN. 3.3V Differential output clock Differential output clock GND 3 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION, CONTINUED Pin # 43 Name SRCC7/CR#_E Type I/O 44 SRCT7/CR#_F I/O 45 46 47 VDD_SRC_IO SRCC8/CPU_ ITPC SRCT8/CPU_ ITPT PWR OUT OUT 48 49 50 51 52 53 54 55 56 IO_VOUT VDD_CPU_IO CPUC1 CPUT1 VSS_CPU CPUC0 CPUT0 VDD_CPU CKPWRGD/PD# OUT PWR OUT OUT GND OUT OUT PWR IN 57 58 59 60 61 62 FS_B/TestMode VSS_REF XTAL_OUT XTAL_IN VDD_REF REF/FS_C/TestSel IN GND OUT IN PWR I/O 63 64 SDA SCL I/O IN Description SRC clock. SRC differential clock output enable, control SRC6, 0 = enable. Mode selected by SMBus control register. Default is SRC7. SRC clock. SRC differential clock output enable, control SRC8, 0 = enable. Mode selected by SMBus control register. Default is SRC7. 0.8V SRC clock. CPU clock. Mode selected by pin7. SRC clock. CPU clock. Mode selected by pin7. V_IO adjustment 0.8V Differential output clock Differential output clock GND Differential output clock Differential output clock 3.3V CKPWRGD power good, active LOW, used to latch FSA,B,C, ITP_EN, TME, and SRC5_EN , active HIGH. After, becomes power down, LOW active. Frequency Select at CKPWRGD assertion. Test Mode selection, see TEST_MODE selection table.q GND XTAL out XTAL in 3.3V 14.318MHz. Frequency Select at CKPWRGD assertion. Selects test mode if pulled above 2V at CKPWRGD assertion. SMBus clock SMBus data TEST MODE SELECTION(1) If TEST_SEL sampled above 2V at CKPWRGD active LOW Test_Mode CPU SRC PCI/F REF DOT_96/DOT_SSC USB 1 REF/N REF/N REF/N REF REF/N REF/N 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z NOTE: 1. Once test clock operation has been invoked, TEST_MODE pin will select between the Hi-Z and REF/N, with VIH_FS and VIL_FS thresholds. FREQUENCY SELECTION FSC, B, A CPU SRC[7:0] PCI USB DOT REF 101 100 100 33.3 48 96 14.318 001 133 100 33.3 48 96 14.318 011 166 100 33.3 48 96 14.318 010 200 100 33.3 48 96 14.318 000 266 100 33.3 48 96 14.318 100 333 100 33.3 48 96 14.318 110 400 100 33.3 48 96 14.318 111 Reserve 100 33.3 48 96 14.318 4 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Min INDEX BLOCK READ PROTOCOL Max Unit VDDA 3.3V Core Supply Voltage 4.6 V VDD 3.3V Logic Input Supply Voltage GND - 0.5 4.6 V TSTG Storage Temperature TAMBIENT Ambient Operating Temperature TCASE Case Temperature ESD Prot Input ESD Protection –65 +150 °C 0 +70 °C +115 °C 2000 Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit 30-37). V Human Body Model NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. SM PROTOCOL # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master # of bits 1 8 1 8 1 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave 38 39-46 47 48-55 1 8 1 8 Master Slave Master Slave Master Slave INDEX BLOCK WRITE PROTOCOL Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop Master 5 Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE CFGP (PIN5) VOLTAGE DECODING TABLE state Min Typ Max Low 0V 0.55V 0.9V Mid 1.3V 1.65V 2V High 2.4V 2.75V VDD CFG CONFIGURATION TABLE 1 CFGP, TME (pin5, pin4) CFG1, CFG0 Byte11 bit[7:6] N programming enable Byte16 bit 3 Low, 0 0, 0 1 Low, 1 Mid, 0 0, 0 0, 1 0 1 Mid, 1 0, 1 0 High, 0 1, 0 1 High, 1 1, 1 1 CFG CONFIGURATION TABLE 2 CFG[1: 0] CPU SATA (pin21, 22) 00 PLL1(1) 01 10 11 PCI Pin17/ 18 SRC 48/96 PLL4 SRC (1) PLL4 (from SRC PLL)(1) CFB table (default SRC) PLL4 (1) PLL2 (3) PLL1(1) PLL3(1) PLL3(1) CFB table (default SRC) PLL4 (1) PLL2 (3) PLL1(2) PLL3(1) PLL3(1) CFB table (default SRC) PLL4 (1) PLL2 (3) PLL4(1) Pin17 = 25MHz, PLL2 Pin18 = 1394A, PLL3 (3) PLL4 (1) PLL2 (3) PLL1(2) PLL2 (CV183-1) (3) PLL4 (CV183-2)(1) Note: 1. SSC 0.5% dow n spread 2. SSC 0.5% denter spread 3. No SSC 6 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE CFB TABLE (PIN 17-18) CFB[3,2,1,0] B1b[4:1] 0000 0001 0010 0011 0100 0101 110 0111 Pin17, 18 Comments SRC (PLL4) SRC (PLL4) 100MHz 0.5% SSC (PLL3) 100MHz 1.0% SSC (PLL3) 100MHz 1.5% SSC (PLL3) 100MHz 2.0% SSC (PLL3) 100MHz 2.5% SSC (PLL3) Reserved 1000 1394A 3.3V, SSC off Byte4 bit0 lose control 1001 1394A&B 3.3V, SSC off Byte4 bit0 lose control 1010 1394B 3.3V, SSC off Byte4 bit0 lose control 27MHz, 3.3V, Byte4 bit0 control the SSC enable, Byte1 bit5 control the down/center 25MHz 3.3V, SSC off Byte4 bit0 lose control Pin17 = 25MHz, PLL2 Pin18 = 1394A, PLL3 Both no SSC Reserved Reserved SATA/PCI from PLL3 or PLL4 (see CFG table) default, SATA/PCI from PLL3 or PLL4 (see CFG table) From PLL3 , SATA/PCI from PLL4 From PLL3 , SATA/PCI from PLL4 From PLL3 , SATA/PCI from PLL4 From PLL3 , SATA/PCI from PLL4 From PLL3 , SATA/PCI from PLL4 From PLL3 , SATA/PCI from PLL4 From PLL3 , SATA/PCI from PLL4 From PLL3, pin17 = 1394A, pin18 = 1394B, SATA/PCI from PLL4 From PLL3 , SATA/PCI from PLL4 1011 1100 1101 1110 1111 From PLL3 , SATA/PCI from PLL4 25MHz from PLL2 1394 from PLL3, SATA/PCI from PLL4 Reserved Reserved IO_VOUT [2:0] TABLE DEVICE ID TABLE ID3,ID2,ID1,ID0 From PLL3 , SATA/PCI from PLL4 Comments 000 0.3V 0000 CK505 56 pin TSSOP CK505 YC 001 0.4V 0001 CK505 64 pin TSSOP CK505 YC 010 0.5V 0010 48 pin QFN CK505 YC 011 0.6V 0011 56 pin QFN CK505 YC 100 0.7V 0100 64 pin QFN CK505 YC 101 0.8V 0101 72 pin QFN CK505 YC 110 0.9V CK505 YC 111 1V 0110 48 pin SSOP 0111 56 pin SSOP CK505 YC 1000 Reserved CK505 Derivative (non YC) 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved 7 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE N-PROGRAMMING PROCEDURE •. User writes the desired CPU frequency in HEX form into CPUN [8:0], Byte 16, 17. • User writes the desired SRC frequency in HEX form into PN [7:0], Byte 18. • Byte 16 bit 3 has to be "1". This bit will decode the power on latched value of pins 4, 5 (see CFG table 1). CONTROL REGISTERS BYTE 0 Bit Output(s) Affected Description/Function 7 6 5 4 3 FSC FSB FSA iAMT_EN Reserved Latched FSC Latched FSB Latched FSA iAMT Mode 2 CFB table enable 1 SATA source 0 PD_Restore 0 1 Legacy Mode Enable CFB table Normal, depend on CFB and CGF table SMBUS control registers setting after the power down Power on default, With some exceptions Type Power On R R R RW RW Latched Value Latched Value Latched Value HW M1 setting(1) 0 Disable CFB table (pin 17, 18 is SRC) RW 0 PLL2 RW 0 Save register contents RW 1 Enabled NOTES: 1. Sticky 1, can only be reset by power off. BYTE 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 SRC0_sel PLL1_SSC_DC PLL3_SSC_DC PLL3_CFB3 PLL3_CFB2 PLL3_CFB1 PLL3_CFB0 PCI Pin13/14 mode select SSC mode selection SSC mode selection SRC0 Down spread Down spread DOT96 Center spread Center spread Only valid if Byte0 bit2 = 0 See PLL3_CFB table, configure pin17, 18 output mode Reflect PCI PLL status 0 0 0 0 0 0 1 PLL3 PLL4 RW RW RW RW RW RW RW R BYTE 2 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 REF USB_48 PCIF5 PCI4 PCI3 PCI2 PCI1 PCI0 Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 8 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 3 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 SRC11 SRC10 SRC9 SRC8/ITP SRC7 SRC6 SRC5 SRC4 Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 BYTE 4 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 SRC3 SATA/SRC2 SRC1 SRC0/DOT96 CPU1 CPU0 PLL1_SSC_ON PLL3_SSC_ON Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable SSC Enable SSC Enable Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 CR#_A CR#_A control CR#_B CR#_B control CR#_C CR#_C control CR#_D CR#_D control Pin1 mode selection CR#_A control selection Pin3 mode selection CR#_B control selection Pin24 mode selection CR#_C control selection Pin25 mode selection CR#_D control selection PCI0 mode SRC0 PCI1mode SRC1(1) SRCT3 mode SRC0 SRCC3 mode SRC1 CR#_A mode SRC2 CR#_B mode SRC4 CR#_C mode SRC2 CR#_D mode SRC4 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 BYTE 5 NOTE: 1. Only when SRC1 is SRC Clock. 9 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 6(1) Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 CR#_E CR#_F CR#_G CR#_H Reserved Reserved SSCD_STP_CRTL SRC_STP_CRTL Pin43 mode selection, control SRC6 Pin44 mode selection, control SRC8 Pin32 mode selection, control SRC9 Pin33 mode selection, control SRC10 SRCC7 mode SRCT7 mode SRCC11 mode SRCT11 mode CR#_E mode, Control SRC 6 CR#_F mode, Control SRC 8 CR#_G mode, Control SRC 9 CR#_H mode, Control SRC 10 If set, SSCD stop with PCI_STOP# If set, SRCs stop with PCI_STOP# Free running Free running Stoppable Stoppable RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 1 Type NOTE: 1. STOP - CPUT and SRCT stay high, CPUC and SRCC stay low. BYTE 7 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Description / Function 0 Revision ID Revision ID Revision ID Revision ID Vendor ID Vendor ID Vendor ID Vendor ID Power On 1 0 0 1 0 1 0 1 BYTE 8 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Device_ID3 Device_ID2 Device_ID1 Device_ID0 SE1_OE SE2_OE Description / Function 0 1 Type Power On Enabled Enabled R R R R RW RW RW RW 0 0 1 1 See device ID table Output Enable Output Enable Disabled Disabled BYTE 9 Bit Output(s) Affected Description / Function 0 1 Type Power On 7 PCIF5 with PCI_STOP# Free running Free running stoppable RW 0 6 5 4 3 TME_STRAP REF Drive Strength TME pin 4 power on latch read back Strength control Only valid when Byte9 bit3 is 1 Test Mode entry control normal 1x Hi-Z Normal operation No overclocking 2x REF/N mode Test mode, controlled by byte9 bit 4 R RW RW RW 1 0 0 2 1 0 IO_VOUT2 IO_VOUT1 IO_VOUT0 RW RW RW 1 0 1 Programmable IO_VOUT voltage 10 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 10 Bit Output(s) affected Description/ Function 0 1 Type 7 6 5 4 3 2 1 0 PLL3 PLL2 SRC_DIV PCI_DIV CPU_DIV CPU1 Free run CPU0 Free run SRC5_EN_Strap PLL3 enable PLL2 enable SRC divider disable PCI divider disable CPU divider disable Controlled by CPU_STP# Controlled by CPU_STP# PLL3 pwr dwn PLL2 pwr dwn disable disable disable Free run Free run Pwr up Pwr up enable enable enable Controllable Controllable R RW RW RW RW RW RW RW Power On The latch of SRC5_EN 1 1 1 1 1 1 1 BYTE 11 Bit Output(s) affected 7 CFG1 6 CFG0 0 1 Type R Power On See CFG table 1, 2 See CFG table 1, 2 RW RW 0 1 enable enable GEN II RW RW R 0 1 1 Controlled RW 1 R 5 4 25MHz-EN Reserved 3 2 1 CPU_ITP_AMT EN CPU1_AMT_EN PCI GEN II CPU_ITP_STOP EN 0 Description/ Function 25MHz disabled in PD/ M1 (for both PLL3 and PLL2 25MHZ) disabled Enabled (Can not be reset by PD restore at power down) M1 mode CLK enable at M1 mode Only if ITP_EN = 1 M1 mode CLK enable at M1 mode GEN II compliance disable disable None GEN II Free run control Free run BYTE 12 - BYTE COUNT - DEFAULT 0x13H BYTE 13 Bit Output(s) Affected Description / Function 0 1 Type Power On 7 6 5 4 3 2 1 0 48M REF PCIF5 PCI4 PCI3 PCI2 PCI1 PCI0 Strength control Strength control Strength control Strength control Strength control Strength control Strength control Strength control 1 1 1 1 1 1 1 1 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 RW RW RW RW RW RW RW RW 1 1 0 0 0 0 0 0 BYTE 14 RESERVED 11 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 15, WATCH DOG(1) Bit Output(s) Affected 7 6 5 4 3 2 1 0 Description / Function 0 1 Watch Dog Enable Watch Dog Alarm Enable Disabled Enabled Watch Dog Select Watch Dog Hard/Soft Alarm Select Hard Alarm Only Hard and Soft Alarm Watch Dog Hard Alarm Status Watch Dog Hard Alarm Status Normal Alarm Watch Dog Soft Alarm Status Watch Dog Soft Alarm Status Normal Alarm Watch Dog control Watch Dog Time Base Control 290ms base 1160ms base WD_1_ Timer 2 WatchDog_1_Alarm Timer WD_1_ Timer 1 Default is 7*290ms WD_1_ Timer 0 Type Power On RW RW R R RW RW RW RW 0 0 0 1 1 1 NOTE: 1. Hard Alarm switch to HW FS frequency. BYTE 16 Bit Output(s) Affected 7 6 5 WDEAPD 27MHz SSC1 27MHz SSC0 4 3 2 1 0 Description / Function 0 1 Type Power On Set Byte15 bit7 = 1 after Power Down to enable the watch dog after the power down Disabled Enabled RW RW RW 0 0 0 RW RW RW RW RW 0 Power on latch 0 0 FS latch Test _scl N programming Reserved Reserved CPUN8 See 27MHz SSC Table See 27MHz SSC Table On chip test mode enable See CFG table 1 normal Disabled SCLK=1, clk outputs = 1 SCLK=0, clk outputs=0 Enabled 27MHZ SSC TABLE 27MHz SSC1, SSC0 Spread (Byte1 bit5 control center or down spread) 00 01 10 11 0.5% 1.0% 1.5% 2.0% BYTE 17 (PLL1) Bit Output(s) Affected 7 6 5 CPUN7 CPUN6 CPUN5 4 3 2 1 0 CPUN4 CPUN3 CPUN2 CPUN1 CPUN0 Description / Function 0 1 Type Power On RW RW RW CPU clock frequency = CPUN [8:0] (Hex) RW RW RW RW RW 12 FS latch IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 18 (PLL3) Bit Output(s) Affected 7 6 5 4 3 2 1 0 PN 7 PN 6 PN 5 PN 4 PN 3 PN 2 PN 1 PN 0 Description / Function 0 1 Type Power On RW RW RW RW RW RW RW RW SRC clock frequency = PNC [7:0] (Hex) 100MHz BYTE 19 CLOCK SOURCE SELECTION, WRITTEN AFTER STOP BIT Bit Output(s) Affected 7 6 5 4 Output serial resistor PLL1 SSC PLL3 SSC PLL4 SSC 3 2 1 0 PLL4_SSC_DC Reserved Reserved Reserved Description / Function 0 0 ohm (External resistor needed) spread % selection 0.5% (p-p) SSC mode selection Down spread centered at 99.75MHz 1 33 ohm (No external resistor needed) 0.45%(p-p) 0.45%(p-p) 0.45%(p-p) center spread Type Power On 0 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 BYTE 30 Bit 7 6 5 4 3 2 1 0 Output(s) affected Description/ Function Don’t change the default Don’t change the default Don’t change the default Don’t change the default Don’t change the default Don’t change the default 0 1 PLL4 (SRC) SSC on/off control Don’t change the default disable enable 13 Type RW RW RW RW RW RW RW RW Power On 1 0 0 0 0 0 1 0 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes 1,7 Maximum Supply Voltage VDDxxx Supply Voltage 4.6 V Maximum Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 3.8 V 1,7 Maximum Input Voltage V IH 3.3V LVCMOS Inputs 4.6 V 1,7,8 Minimum Input Voltage V IL Any Input GND - 0.5 V 1,7 Storage Temperature Ts - -65 150 ° C 1,7 Input ESD protection ESD prot Human Body Model 2000 V 1,7 ELECTRICAL CHARACTERISTICS - INPUT/SUPPLY/COMMON OUTPUT PARAMETERS PARAMETER SYMBO L CO NDITIO NS MIN MAX UNITS Ambient O perating Temp Tambient - 0 70 °C 1 Supply Voltage VDDx x x Supply Voltage 3.135 3.465 V 1 Supply Voltage VDDx x x _IO Low-Voltage Differential I/O Supply 0.70 0.88 V 1 Input High Voltage V IHS E Single-ended inputs 2 V DD + 0.3 V 1 Input Low Voltage V ILS E Single-ended inputs V S S - 0.3 0.8 V 1 Input Leak age Current IIN -5 5 uA 1 Input Leak age Current IINRE S V IN = V DD , V IN = G ND Inputs with pull or pull down res is tors V IN = V DD , V IN = G ND -200 200 uA 1 O utput High Voltage V OHS E Single-ended outputs , IOH = -1mA V 1 O utput Low Voltage V OLS E Single-ended outputs , IOL = 1 mA O utput High Voltage V OHDIF Differential O utputs , IOH = TBD mA O utput Low Voltage Low Thres hold InputHigh Voltage (Tes t Mode) Low Thres hold InputHigh Voltage Low Thres hold InputLow Voltage O perating Supply Current V OLDIF Differential O utputs , IOL = TBD mA V IH_FS _TE S T 3.3 V +/-5% V IH_FS 0.4 V 1 0.9 V 1 0.4 V 1 2 V DD + 0.3 V 1 3.3 V +/-5% 0.7 1.5 V 1 V IL_FS 3.3 V +/-5% V S S - 0.3 0.35 V 1 I DD_DP 140 mA 1 30 mA 1 IDD_P D3.3 3.3V s upply , PLL3 off 0.8V s upply , Differential IO c urrent, all outputs enabled 3.3V s upply , Power Down Mode 5 mA 1 IDD_P DIO 0.8V IO s upply , Power Down Mode 0 mA 1 1 IDD_IO Power Down Current 2.4 Notes 0.7 IDD_iA M T3.3 3.3V s upply , iAMT Mode 30 mA IDD_iA M T0.8 0.8V IO s upply , iAMTMode 10 mA 1 Input Frequenc y Fi V DD = 3.3 V 14.31818 MHz 2 Pin Induc tanc e L pin iAMT Mode Current Input Capac itanc e Spread Spec trum Modulation Frequenc y 7 nH 1 5 pF 1 O utput pin c apac itanc e 6 pF 1 C INX X1 & X2 pins TBD pF 1 fS S M OD Triangular Modulation 33 k Hz 1 C IN Logic Inputs C OUT 14 1.5 30 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - INPUT/COMMON PARAMETERS PARAMETER SYMBOL Clk Stabilization TSTAB Tdrive_SRC TDRSRC Tdrive_PD# TDRPD Tdrive_CPU TDRSRC Tfall_PD# TFALL Trise_PD# TRISE CONDITIONS MIN From VDD Power-Up or de-assertion of PD# to 1st clock SRC output enable after PCI_STOP# de-assertion Differential output enable after PD# de-assertion CPU output enable after CPU_STOP# de-assertion MAX UNITS Notes 1.8 ms 1 15 ns 1 300 us 1 10 ns 1 5 ns 1 5 ns 1 Fall/rise time of PD#, PCI_STOP# and CPU_STOP# inputs AC ELECTRICAL CHARACTERISTICS - LOW POWER DIFFERENTIAL OUTPUTS PARAMETER SYMBOL CONDITIONS MIN MAX Rising Edge Slew Rate tSLR Differential Measurement 2.5 5 UNITS NOTES V/ns 1,2 2.5 Falling Edge Slew Rate tFLR Differential Measurement 5 V/ns 1,2 Slew Rate Variation tSLVAR Single-ended Measurement 20 % 1 Maximum Output Voltage VHIGH Includes overshoot 1150 mV 1 1 Minimum Output Voltage VLOW Includes undershoot -300 mV Differential Voltage Swing VSWING Differential Measurement 300 mV 1 Crossing Point Voltage VXABS Single-ended Measurement 300 550 mV 1,3,4 Crossing Point Variation VXABSVAR Single-ended Measurement 140 mV 1,3,5 Duty Cycle D CYC Differential Measurement 55 % 1 CPU Jitter - Cycle to Cycle CPUJ C2C Differential Measurement 85 ps 1 SRC Jitter - Cycle to Cycle SRCJ C2C Differential Measurement 125 ps 1 DOT Jitter - Cycle to Cycle DOTJ C2C Differential Measurement 250 ps 1 CPU[1:0] Skew CPU SKEW 10 Differential Measurement 100 ps 1 CPU[2_ITP:0] Skew CPU SKEW 20 Differential Measurement 150 ps 1 SRC[10:0] Skew SRC SKEW Differential Measurement 250 ps 1,10 45 ELECTRICAL CHARACTERISTICS - PCICLK/PCICLK_F UNITS NOTES PARAMETER SYMBOL CONDITIONS MIN MAX Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,6 Clock period Tperiod 30.00900 ns 6 30.15980 ns 6 Absolute min/max period Tabs 33.33MHz output nominal/spread 29.49100 30.65980 ns 6 Output High Voltage VOH I OH = -1 mA 2.4 V 1 Output Low Voltage VOL I OL = 1 mA 0.4 V 1 mA 1 -33 mA 1 mA 1 38 mA 1 4 V/ns 1 33.33MHz output nominal 33.33MHz output spread V OH @MIN = 1.0 V 29.99100 -33 Output High Current I OH Output Low Current I OL Rising Edge Slew Rate t SLR Measured from 0.8 to 2.0 V Falling Edge Slew Rate t FLR Measured from 2.0 to 0.8 V 1 4 V/ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 VT = 1.5 V 250 ps 1 ps 1,9 ps 1 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V 30 VOL @ MAX = 0.4 V Skew t skew Intentional PCI-PCI delay t delay VT = 1.5 V Jitter, Cycle to cycle t jcyc-cyc VT = 1.5 V 15 1 200 nominal 500 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - USB48MHZ UNITS NOTES PARAMETER SYMBOL CONDITIONS MIN MAX Long Accuracy ppm see Tperiod min-max values -100 100 ppm 1,2 Clock period Tperiod 48.00MHz output nominal 20.83125 20.83542 ns 2 Absolute min/max period Tabs 48.00MHz output nominal 20.48130 21.18540 ns 2 Output High Voltage VOH I OH = -1 mA 2.4 V 1 Output Low Voltage VOL I OL = 1 mA V 1 mA 1 Output High Current I OH Output Low Current I OL V OH @MIN = 1.0 V 0.4 -29 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V -23 mA 1 mA 1 27 mA 1 1 29 VOL @ MAX = 0.4 V Rising Edge Slew Rate t SLR Measured from 0.8 to 2.0 V 1 2 V/ns Falling Edge Slew Rate t FLR Measured from 2.0 to 0.8 V 1 2 V/ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Jitter, Cycle to cycle t jcyc-cyc VT = 1.5 V 350 ps 1 MIN MAX UNITS Notes 2.7 5.5 V 1 0.4 V 1 mA 1 1000 ns 1 300 ns 1 100 kHz 1 ELECTRICAL CHARACTERISTICS - SMBUS INTERFACE PARAMETER SYMBOL CONDITIONS SMBus Voltage VDD Low-level Output Voltage V OLSMB @ I PULLUP I PULLUP SMB Data Pin Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency TRI2C TFI2C FSMBUS (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Block Mode 16 4 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - REF-14.318MHZ PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2 Clock period Tperiod 14.318MHz output nominal 69.8203 69.8622 ns 2 Absolute min/max period Tabs 14.318MHz output nominal 69.8203 70.86224 ns 2 Output High Voltage VOH I OH = -1 mA 2.4 Output Low Voltage VOL I OL = 1 mA Output High Current I OH Output Low Current I OL Rising Edge Slew Rate t SLR Falling Edge Slew Rate t FLR Duty Cycle Jitter V 1 0.4 V 1 -33 -33 mA 1 30 38 mA 1 Measured from 0.8 to 2.0 V 1 4 V/ns 1 Measured from 2.0 to 0.8 V 1 4 V/ns 1 dt1 VT = 1.5 V 45 55 % 1 t jcyc-cyc VT = 1.5 V 1000 ps 1 VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Notes on Electrical Characteristics: 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 7 Operation under these conditions is neither implied, nor guaranteed. 8 Maximum input voltage is not to exceed maximum VDD 9 See PCI Clock-to-Clock Delay Figure 10 SRC 3,4,6,7, are 0 ps nominal interpair skew 17 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PCI STOP FUNCTIONALITY PCI_STOP# SRC SRC# PCI 1 Normal Normal 33MHz 0 High Low Low PCI_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’) tSU PCI_STOP# PCIF5 33MHz PCI[4:0] 33MHz SRC 100MHz SRC# 100MHz PCI_STOP# - DE-ASSERTION (TRANSITION FROM '0' TO '1') tSU tDRIVE_SRC PCI_STOP# PCIF5 33MHz PCI[4:0] 33MHz SRC 100MHz SRC# 100MHz 18 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE CPU STOP FUNCTIONALITY The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously. CPU_STOP# CPU CPU# 1 Normal Normal 0 High Low CPU_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’) Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the SMBus CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a ‘0’, CPU output will stop CPU_True = High and CPU_Complement = Low. When the SMBus CPU_STOP# tri-state bit corresponding to the CPU output of interest is programmed to a ‘1’, CPU outputs will be tri-stated. CPU_STOP# CPU CPU# CPU_STOP# - DE-ASSERTION (TRANSITION FROM ‘0’ TO ‘1’) With the de-assertion of CPU_STOP# all stopped CPU outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is two to six CPU clock periods. If the control register tristate bit corresponding to the output of interest is programmed to ‘1’, then the stopped CPU outputs will be driven High within 10nS of CPU_STOP# de-assertion to a voltage greater than 200mV. CPU_STOP# CPU CPU# CPU Internal tDRIVE_CPU_Stop 10nS > 200mV 19 IDTCV183-2A PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PD# ASSERTION PD# CPU 133MHz CPU# 133MHz SRC 100MHz SRC# 100MHz USB 48MHz PCI 33MHz REF 14.31818 PD# DE-ASSERTION tSTABLE