MSM51V17400F-60TDKX

FEDD51V17400F-03 Issue Date: Nov. 27, 2014 MSM51V17400F 4,194,304-Word × 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM51V17400F is a 4,194,304-word × 4-bit dynamic RAM fabricated in LAPIS Semiconductor’s silicon-gate CMOS technology. The MSM51V17400F achieves high integration, high-speed operation, and low-power consumption because LAPIS Semiconductor manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM51V17400F is available in a 26/24-pin plastic TSOP. FEATURES · 4,194,304-word × 4-bit configuration · Single 3.3V power supply, ±0.3V tolerance · Input : LVTTL compatible, low input capacitance · Output : LVTTL compatible, 3-state · Refresh : 2048 cycles/32ms · Fast page mode, read modify write capability · CAS before RAS refresh, hidden refresh, RAS-only refresh capability · Packages: 26/24-pin 300mil plastic TSOP (P-TSOP(2)26/24-300-1.27-Z3K) PRODUCT FAMILY Access Time (Max.) Family MSM51V17400F-60 tRAC tAA tCAC tOEA Cycle Time (Min.) 60ns 30ns 15ns 15ns 110ns Power Dissipation Operating (Max.) Standby (Max.) 324mW 1.8mW 1/15 FEDD51V17400F-03 MSM51V17400F PIN CONFIGURATION (TOP VIEW) VCC 1 26 VSS DQ1 2 25 DQ4 DQ2 3 24 DQ3 WE 4 23 CAS RAS 5 22 OE NC 6 21 A9 A10 8 19 A8 A0 9 18 A7 A1 10 17 A6 A2 11 16 A5 A3 12 15 A4 VCC 13 14 VSS 26/24-Pin Plastic TSOP (K Type) Pin Name Function A0–A10 Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1–DQ4 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (3.3V) VSS Ground (0V) NC No Connection Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/15 FEDD51V17400F-03 MSM51V17400F ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on Any Pin Relative to VSS VIN, VOUT –0.5 to VCC+ 0.5 V Voltage VCC Supply relative to VSS VCC –0.5 to 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C *: Ta = 25°C RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70°C) Parameter Power Supply Voltage Symbol Min. Typ. Max. Unit VCC 3.0 3.3 3.6 V VSS 0 0 0 Input High Voltage VIH 2.0 ⎯ Input Low Voltage VIL − 0.3*2 ⎯ V *1 VCC + 0.3 0.8 V V Notes: *1. The input voltage is VCC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS − 1.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied). PIN CAPACITANCE (Vcc = 3.3V ± 0.3V, Ta = 25°C, f = 1 MHz) Parameter Symbol Min. Min. Unit CIN1 — 5 pF (RAS, CAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ1 – DQ4) CI/O — 7 pF Input Capacitance (A0 – A10) Input Capacitance 3/15 FEDD51V17400F-03 MSM51V17400F DC CHARACTERISTICS (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Parameter Symbol 2.4 VCC V 0 0.4 V − 10 10 μA − 10 10 μA ⎯ 90 mA 1,2 RAS, CAS = VIH ⎯ 2 RAS, CAS ≥ VCC − 0.2V ⎯ mA 1 0.5 ⎯ 90 mA 1,2 ⎯ 5 mA 1 ⎯ 90 mA 1,2 ⎯ 70 mA 1,3 IOH = −2.0mA Output Low Voltage VOL IOL = 2.0mA 0V ≤ VI ≤ VCC +0.3V; Input Leakage Current ILI Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) ICC2 (Standby) ICC3 (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) DQ disable 0V ≤ VO ≤ VCC RAS, CAS cycling, tRC = Min. CAS = VIH, tRC = Min. RAS = VIH, ICC5 (Standby) Average Power Supply Current All other pins not under test = 0V RAS cycling, (RAS-only Refresh) Power Supply Current Note Max. VOH Average Power Supply Current Unit Min. Output High Voltage Power Supply Current MSM51V17400 F-60 Condition CAS = VIL, DQ = enable ICC6 RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 4/15 FEDD51V17400F-03 MSM51V17400F AC CHARACTERISTICS (1/2) (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3,11,12 Parameter MSM51V17400 F-60 Symbol Unit Note Min. Max. tRC 110 ⎯ ns tRWC 155 ⎯ ns tPC 40 ⎯ ns Fast Page Mode Read Modify Write tPRWC Cycle Time 85 ⎯ ns Access Time from RAS tRAC ⎯ 60 ns 4, 5, 6 Access Time from CAS tCAC ⎯ 15 ns 4, 5 Access Time from Column Address tAA ⎯ 30 ns 4, 6 Access Time from CAS Precharge tCPA ⎯ 35 ns 4 Access Time from OE tOEA ⎯ 15 ns 4 Output Low Impedance Time from CAS tCLZ 0 ⎯ ns 4 CAS to Data Output Buffer Turnoff Delay Time tOFF 0 15 ns 7 OE to Data Output Buffer Turn-off Delay Time tOEZ 0 15 ns 7 Transition Time tT 3 50 ns 3 Refresh Period tREF ⎯ 32 ms RAS Precharge Time tRP 40 ⎯ ns RAS Pulse Width tRAS 60 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 60 100,000 ns RAS Hold Time tRSH 15 ⎯ ns RAS Hold Time referenced to OE tROH 15 ⎯ ns CAS Precharge Time (Fast Page Mode) tCP 10 ⎯ ns CAS Pulse Width tCAS 15 10,000 ns CAS Hold Time tCSH 60 ⎯ ns CAS to RAS Precharge Time tCRP 5 ⎯ ns RAS Hold Time from CAS Precharge tRHCP 35 ⎯ ns RAS to CAS Delay Time tRCD 20 45 ns 5 RAS to Column Address Delay Time tRAD 15 30 ns 6 Row Address Set-up Time tASR 0 ⎯ ns Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time 5/15 FEDD51V17400F-03 MSM51V17400F AC CHARACTERISTICS (2/2) (VCC = 3.3V ± 0.3V ,Ta = 0 to 70°C) Note1,2,3,11,12 Parameter MSM51V17400 F-60 Symbol Unit Min. Max. Note Row Address Hold Time tRAH 10 ⎯ ns Column Address Set-up Time tASC 0 ⎯ ns Column Address Hold Time tCAH 10 ⎯ ns Column Address to RAS Lead Time tRAL 30 ⎯ ns Read Command Set-up Time tRCS 0 ⎯ ns Read Command Hold Time tRCH 0 ⎯ ns 8 Read Command Hold Time referenced to RAS tRRH 0 ⎯ ns 8 Write Command Set-up Time tWCS 0 ⎯ ns 9 Write Command Hold Time tWCH 10 ⎯ ns Write Command Pulse Width tWP 10 ⎯ ns OE Command Hold Time tOEH 15 ⎯ ns Write Command to RAS Lead Time tRWL 15 ⎯ ns Write Command to CAS Lead Time tCWL 15 ⎯ ns Data-in Set-up Time tDS 0 ⎯ ns 10 Data-in Hold Time tDH 10 ⎯ ns 10 OE to Data-in Delay Time tOED 15 ⎯ ns CAS to WE Delay Time tCWD 40 ⎯ ns 9 Column Address to WE Delay Time tAWD 55 ⎯ ns 9 RAS to WE Delay Time tRWD 85 ⎯ ns 9 tCPWD 60 ⎯ ns 9 CAS Active Delay Time from RAS Precharge tRPC 5 ⎯ ns RAS to CAS Set-up Time (CAS before RAS) tCSR 10 ⎯ ns RAS to CAS Hold Time (CAS before RAS) tCHR 10 ⎯ ns WE to RAS Precharge Time (CAS before RAS) tWRP 10 ⎯ ns WE Hold Time from RAS (CAS before RAS) tWRH 10 ⎯ ns RAS to WE Set-up Time (Test Mode) tWTS 10 ⎯ ns RAS to WE Hold Time (Test Mode) tWTH 10 ⎯ ns CAS Precharge WE Delay Time 6/15 FEDD51V17400F-03 MSM51V17400F Notes: 1. A start-up delay of 200μs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1TTL load and 100pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test CA9 and CA10 are not used and each DQ pin now access 4-bit locations. Since all 4 DQ pins are used, a total 16 data bits can be written in parallel into the memory array. In a read cycle, if 4 data bits are equal, the DQ pin will indicate a high level. If the 4 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameter is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 7/15 FEDD51V17400F-03 MSM51V17400F TIMING CHART Read Cycle RAS tRC tRAS VIH tRP VIL tCSH tCRP CAS WE tCRP tRSH tCAS VIH tRAD VIL tRAL tASR Address tRCD VIH VIL tRAH tASC Row tCAH Column tRRH tRCS VIH tAA VIL tRCH tROH tOEA OE VIH VIL tCAC tRAC DQ tOFF tOEZ tCLZ VOH Valid Data-out Open VOL “H” or “L” Write Cycle (Early Write) RAS tRC tRAS VIH tRP VIL tCSH tCRP CAS tRAD VIL tRAL VIH VIL tRAH tASC Row tCAH Column tCWL tWCS tWP WE OE DQ tCRP tRSH tCAS VIH tASR Address tRCD tWCH VIH VIL tRWL VIH VIL VIH VIL tDS tD Valid Data-in Open “H” or “L” 8/15 FEDD51V17400F-03 MSM51V17400F Read Modify Write Cycle tRWC tRAS RAS VIH tRP VIL tCSH tCRP CAS tRAD VIL VIH VIL tCRP tRSH tCAS VIH tASR Address tRCD tRAH tASC Row tCWL tRWL tCAH Colum tRCS tCWD tWP tRWD WE OE VIH VIL tAWD tAA tOEH tOE VIH tOED VIL tCAC tDH tRAC DQ VI/OH VI/OL tOEZ tCLZ Valid Data-out tDS Valid Data-in “H” or “L” 9/15 FEDD51V17400F-03 MSM51V17400F Fast Page Mode Read Cycle tRASP RAS VIH VIL tRCD tCRP CAS tCP tCP tRAD tCSH VIL VIH VIL tRAH Row tASC tCAH Column tCAH tASC Column tRCH tCAH Column tRCS tRCH tRCS tRCH VIH VIL tAA tAA tAA tOEA tRRH tOEA VIH VIL tRAC tCAC DQ tCRP tRAL tASC tOEA OE tRSH tCAS tCAS VIH tRCS WE tRHCP tCAS tASR Address tRP tPC tCAC tCPA tOFF tOEZ Valid Data-out Valid Data-out VOL tOFF tCAC tOEZ t CLZ tCLZ tCLZ VOH tCPA tOFF tOEZ Valid Data-out “H” or “L” Fast Page Mode Write Cycle (Early Write) tRP tRASP RAS VIH VIL tCRP tCP tRCD tCP tCAS CAS tCAS VIH VIH VIL tRAH tASC Row tCSH tCAH tASC Column tCRP tASC tRAL tCAH Column tRWL tWCS tWCH tWP tCWL tWCS VIH tWCH tWP tCWL tWCS tWP tWCH VIL tDS VIH DQ tCAH Column tCWL WE tRSH tCAS tRAD VIL tASR Address tRHPC tPC VIL tDH Valid * Data-in tDS tDH Valid * Data-in tDS tDH Valid * Data-in Note: OE = “H” or “L” “H” or “L” 10/15 FEDD51V17400F-03 MSM51V17400F Fast Page Mode Read Modify Write Cycle tRASP tCSH tPRWC tRP tRSH VIH RAS VIL tRCD tCP tCAS tRAH tASR VIH VIL tCAH tRAD VIL Address tCR tCAS tCAH VIH CAS tCP tCAS tCAH tCWL tASC Row tASC Column Column tRCS tRWD tCWD tRCS tASC tRAL tCWL Column tRC tCPWD tCWL tCPWD tCWD tCWD tAWD tAWD tRWL VIH WE tAWD VIL tWP tRAC tAA tDH tOEA VIH OE tCAC tAA VI/OL Out tCLZ tCAC tDS tOED tOEZ tDS tCAC Out In tDH tOEA tOED tOEZ tOEZ VI/OH DQ tCPA tOEA tOED VIL tROH tDH tAA tDS tWP tWP tCPA In Out In tCLZ tCLZ Note: In = Valid Data-in, Out = Valid Data-out “H” or “L” RAS-only Refresh Cycle tRC tRAS RAS VIH tRP VIL tCRP CAS Address DQ tRPC VIH VIL VIH VIL VOH VOL tASR tRA Row tOFF Open Note: WE, OE = “H” or “L” “H” or “L” 11/15 FEDD51V17400F-03 MSM51V17400F CAS before RAS Refresh Cycle tRP RAS tRC tRAS VIH tRPC tCP VIL tRP tCSR tRPC tCHR CAS WE VIH VIL tWRP tWRH tWRP VIH VIL tOFF DQ VOH Open VOL Note: OE, Address = “H” or “L” “H” or “L” Hidden Refresh Read Cycle tRC tRC tRAS RAS tRAS VIH VIL tCRP tRCD tRSH tRP tRP tCHR CAS VIH tRAD VIL tASR Address VIH VIL tRAH tASC Row tCAH Column tRCS WE tCAC VIH VIL tRAL tAA tROH OE DQ VIL VOL tWRP tWRH tOFF tOEA VIH VOH tRRH tRAC tOEZ tCLZ Open Valid Data-out “H” or “L” 12/15 FEDD51V17400F-03 MSM51V17400F Hidden Refresh Write Cycle tRC tRC tRAS RAS tRAS VIH VIL tCRP tRCD tRSH tRP tRP tCHR CAS VIH tRAD VIL tASR Address VIH VIL tRAH tASC Row tCAH Column tRAL tRWL tWP WE VIH VIL tWCH tWCS OE DQ tWRP tWRH VIH VIL tDS VIH tDH Valid Data-in VIL “H” or “L” Test Mode-in Cycle tRC tRP RAS tRAS VIH VIL tRPC tCP tCSR CAS VIL tWTS WE DQ tCHR VIH tWTH VIH VIL VIH VIL tOFF Open Note: OE, Address = “H” or “L” “H” or “L” 13/15 FEDD51V17400F-03 MSM51V17400F REVISION HISTORY Page Previous Current Edition Edition Document No. Date FEDD51V17400F-01 Mar.23, 2004 – – FEDD51V17400F-02 Feb.01, 2012 1,2 1 3 1,2 1 – FEDD51V17400F-03 Nov. 27, 2014 1 1 Description Final edition 1 from FEDD5117400F-04 Deleted SOJ26/24 Changed pb-free device name Deleted Block diagram Changed package code(Cu frame) Added ROHM logo mark Changed company Logo 14/15 FEDD51V17400F-03 MSM51V17400F NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. 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