74AVCH2T45DC,125

74AVCH2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 7 — 20 February 2018 1 Product data sheet General description The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state. The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2 Features and benefits • Wide supply voltage range: – VCC(A): 0.8 V to 3.6 V – VCC(B): 0.8 V to 3.6 V • High noise immunity • Complies with JEDEC standards: – JESD8-12 (0.8 V to 1.3 V) – JESD8-11 (0.9 V to 1.65 V) – JESD8-7 (1.2 V to 1.95 V) – JESD8-5 (1.8 V to 2.7 V) – JESD8-B (2.7 V to 3.6 V) • ESD protection: – HBM JESD22-A114F Class 3B exceeds 8000 V – MM JESD22-A115-A exceeds 200 V – CDM JESD22-C101C exceeds 1000 V • Maximum data rates: – 500 Mbps (1.8 V to 3.3 V translation) – 320 Mbps (< 1.8 V to 3.3 V translation) – 320 Mbps (translate to 2.5 V or 1.8 V) – 280 Mbps (translate to 1.5 V) – 240 Mbps (translate to 1.2 V) • Suspend mode • Bus hold on data inputs 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state • • • • • • 3 Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74AVCH2T45DC -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm 74AVCH2T45GT -40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm 74AVCH2T45GF -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1 × 0.5 mm SOT1089 74AVCH2T45GN -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.2 × 1.0 × 0.35 mm SOT1116 74AVCH2T45GS -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1.0 × 0.35 mm SOT1203 4 Version Marking Table 2. Marking Type number Marking code 74AVCH2T45DC K45 74AVCH2T45GT K45 74AVCH2T45GF K5 74AVCH2T45GN K5 74AVCH2T45GS K5 [1] [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 2 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state 5 Functional diagram DIR 1A 5 DIR 2 1A 7 2A 1B 1B 3 2A 6 VCC(A) 2B 2B VCC(B) VCC(A) VCC(B) 001aag577 Figure 1. Logic symbol 6 001aag578 Figure 2. Logic diagram Pinning information 6.1 Pinning 74AVCH2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 DIR 74AVCH2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 DIR 001aag583 Figure 3. Pin configuration SOT765-1 74AVCH2T45 Product data sheet 001aag584 Transparent top view Figure 4. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 3 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state 6.2 Pin description Table 3. Pin description Symbol Pin Description VCC(A) 1 supply voltage port A and DIR 1A 2 data input or output 2A 3 data input or output GND 4 ground (0 V) DIR 5 direction control 2B 6 data input or output 1B 7 data input or output VCC(B) 8 supply voltage port B 7 Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Supply voltage Input VCC(A), VCC(B) DIR 0.8 V to 3.6 V [2] Input/output [1] nA nB L nA = nB input 0.8 V to 3.6 V H input nB = nA [3] X Z Z GND [1] The input circuit of the data I/O is always active. [2] The DIR input circuit is referenced to VCC(A). [3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 4 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state 8 Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC(A) Min Max Unit supply voltage A -0.5 +4.6 V VCC(B) supply voltage B -0.5 +4.6 V IIK input clamping current -50 - -0.5 +4.6 -50 - VI input voltage IOK output clamping current VO Conditions VI < 0 V [1] VO < 0 V output voltage Active mode Suspend or 3-state mode mA V mA [1] [2] [3] -0.5 [1] -0.5 +4.6 V VCCO + 0.5 V IO output current VO = 0 V to VCCO - ±50 mA ICC supply current ICC(A) or ICC(B) - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C - 250 mW Min Max Unit Ptot [1] [2] [3] [4] total power dissipation Tamb = -40 °C to +125 °C [4] The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output port. VCCO + 0.5 V should not exceed 4.6 V. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9 Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC(A) supply voltage A 0.8 3.6 V VCC(B) supply voltage B 0.8 3.6 V VI input voltage 0 3.6 V 0 VCCO V 0 3.6 V -40 +125 °C - 5 VO Conditions output voltage Active mode Suspend or 3-state mode Tamb ambient temperature Δt/ΔV input transition rise and fall rate VCCI = 0.8 V to 3.6 V [1] ns/V [1] VCCO is the supply voltage associated with the output port. 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 5 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state 10 Static characteristics [1] [2] Table 7. Typical static characteristics at Tamb = 25 °C At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max VOH HIGH-level output voltage VI = VIH or VIL - 0.69 - V LOW-level output voltage VI = VIH or VIL - 0.07 - V II input leakage current DIR input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V - ±0.025 ±0.25 μA IBHL bus hold LOW current VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V [3] - 26 - μA bus hold HIGH current VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V [4] - -24 - μA IBHLO bus hold LOW overdrive current VI = GND to VCCI; VCC(A) = VCC(B) = 1.2 V [5] - 28 - μA IBHHO bus hold HIGH overdrive current VI = GND to VCCI; VCC(A) = VCC(B) = 1.2 V [6] - -26 - μA IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V [7] - ±0.5 ±2.5 μA IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - ±0.1 ±1 μA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - ±0.1 ±1 μA VOL IBHH IO = -1.5 mA; VCC(A) = VCC(B) = 0.8 V IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V Unit CI input capacitance DIR input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V - 1.0 - pF CI/O input/output capacitance A and B port; Suspend mode; VO = VCCO or GND; VCC(A) = VCC(B) = 3.3 V - 4.0 - pF [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. [3] The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND and then raising it to VIL max. [4] The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC and then lowering it to VIH min. [5] An external driver must source at least IBHLO to switch this node from LOW to HIGH. [6] An external driver must sink at least IBHHO to switch this node from HIGH to LOW. [7] For I/O ports, the parameter IOZ includes the input leakage current. 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 6 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Static characteristics [1] [2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIH Parameter HIGH-level input voltage Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max VCCI = 0.8 V 0.70VCCI - 0.70VCCI - V VCCI = 1.1 V to 1.95 V 0.65VCCI - 0.65VCCI - V VCCI = 2.3 V to 2.7 V 1.6 - 1.6 - V VCCI = 3.0 V to 3.6 V 2 - 2 - V VCC(A) = 0.8 V 0.70VCC(A) - 0.70VCC(A) - V VCC(A) = 1.1 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V VCC(A) = 2.3 V to 2.7 V 1.6 - 1.6 - V VCC(A) = 3.0 V to 3.6 V 2 - 2 - V VCCI = 0.8 V - 0.30VCCI - 0.30VCCI V VCCI = 1.1 V to 1.95 V - 0.35VCCI - 0.35VCCI V VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V VCCI = 3.0 V to 3.6 V - 0.9 - 0.9 V VCC(A) = 0.8 V - 0.30VCC(A) - 0.30VCC(A) V VCC(A) = 1.1 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V VCC(A) = 2.3 V to 2.7 V - 0.7 - 0.7 V VCC(A) = 3.0 V to 3.6 V - 0.9 - 0.9 V VCCO - 0.1 - VCCO - 0.1 - V IO = -3 mA; VCC(A) = VCC(B) = 1.1 V 0.85 - 0.85 - V IO = -6 mA; VCC(A) = VCC(B) = 1.4 V 1.05 - 1.05 - V IO = -8 mA; VCC(A) = VCC(B) = 1.65 V 1.2 - 1.2 - V IO = -9 mA; VCC(A) = VCC(B) = 2.3 V 1.75 - 1.75 - V IO = -12 mA; VCC(A) = VCC(B) = 3.0 V 2.3 - 2.3 - V data input DIR input VIL LOW-level input voltage data input DIR input VOH VI = VIH or VIL HIGH-level output voltage IO = -100 μA; VCC(A) = VCC(B) = 0.8 V to 3.6 V 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 7 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state Symbol VOL Parameter Conditions -40 °C to +85 °C Max Min Max - 0.1 - 0.1 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V - 0.25 - 0.25 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V - 0.35 - 0.35 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V - 0.45 - 0.45 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V - 0.55 - 0.55 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V - 0.7 - 0.7 V - ±1 - ±1.5 μA 15 - 15 - μA VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V 25 - 25 - μA VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V 45 - 45 - μA VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V 100 - 90 - μA VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V -15 - -15 - μA VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V -25 - -25 - μA VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V -45 - -45 - μA -100 - -100 - μA 125 - 125 - μA 200 - 200 - μA 300 - 300 - μA 500 - 500 - μA VCC(A) = VCC(B) = 1.6 V -125 - -125 - μA VCC(A) = VCC(B) = 1.95 V -200 - -200 - μA VCC(A) = VCC(B) = 2.7 V -300 - -300 - μA -500 - -500 - μA - ±5 - ±7.5 μA VI = VIH or VIL LOW-level output voltage IO = 100 μA; VCC(A) = VCC(B) = 0.8 V to 3.6 V input leakage current IBHL bus hold LOW A or B port current VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V bus hold HIGH current DIR input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V [3] [4] A or B port VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V IBHLO bus hold LOW A or B port overdrive VCC(A) = VCC(B) = 1.6 V current VCC(A) = VCC(B) = 1.95 V [5] VCC(A) = VCC(B) = 2.7 V VCC(A) = VCC(B) = 3.6 V IBHHO bus hold HIGH overdrive current [6] A or B port VCC(A) = VCC(B) = 3.6 V IOZ OFF-state A or B port; VO = 0 V or VCCO; output current VCC(A) = VCC(B) = 0.8 to 3.6 V 74AVCH2T45 Product data sheet Unit Min II IBHH -40 °C to +125 °C [7] All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 8 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state Symbol IOFF ICC Parameter power-off leakage current Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - ±5 - ±35 μA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - ±5 - ±35 μA VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 8 - 11.5 μA VCC(A) = 3.6 V; VCC(B) = 0 V - 8 - 11.5 μA VCC(A) = 0 V; VCC(B) = 3.6 V -2 - -8 - μA VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 8 - 11.5 μA VCC(A) = 3.6 V; VCC(B) = 0 V -2 - -8 - μA VCC(A) = 0 V; VCC(B) = 3.6 V - 8 - 11.5 μA - 16 - 23 μA supply current A port; VI = 0 V or VCCI; IO = 0 A B port; VI = 0 V or VCCI; IO = 0 A A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. [3] The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND and then raising it to VIL max. [4] The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC and then lowering it to VIH min. [5] An external driver must source at least IBHLO to switch this node from LOW to HIGH. [6] An external driver must sink at least IBHHO to switch this node from HIGH to LOW. [7] For I/O ports, the parameter IOZ includes the input leakage current. 11 Dynamic characteristics [1] [2] Table 9. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol tpd tdis ten Parameter propagation delay disable time enable time Conditions VCC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V A to B 15.8 8.4 8.0 8.0 8.7 9.5 ns B to A 15.8 12.7 12.4 12.2 12.0 11.8 ns DIR to A 12.2 12.2 12.2 12.2 12.2 12.2 ns DIR to B 11.7 7.9 7.6 8.2 8.7 10.2 ns DIR to A 27.5 20.6 20.0 20.4 20.7 22.0 ns DIR to B 28.0 20.6 20.2 20.2 20.9 21.7 ns [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. [2] ten is a calculated value using the formula shown in Section 12.4 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 9 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 10. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C [1] [2] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol tpd tdis ten Parameter propagation delay disable time enable time Conditions VCC(A) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V A to B 15.8 12.7 12.4 12.2 12.0 11.8 ns B to A 15.8 8.4 8.0 8.0 8.7 9.5 ns DIR to A 12.2 4.9 3.8 3.7 2.8 3.4 ns DIR to B 11.7 9.2 9.0 8.8 8.7 8.6 ns DIR to A 27.5 17.6 17.0 16.8 17.4 18.1 ns DIR to B 28.0 17.6 16.2 15.9 14.8 15.2 ns [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. [2] ten is a calculated value using the formula shown in Section 12.4 Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V). Symbol CPD Parameter Conditions [1] [2] VCC(A) and VCC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V power dissipation A port: (direction A to B); B port: (direction B to A) capacitance 1 2 2 2 2 2 pF A port: (direction B to A); B port: (direction A to B) 9 11 11 12 14 17 pF [1] CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of the outputs. [2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 10 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 12. Dynamic characteristics for temperature range -40 °C to +85 °C [1] [2] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6. Symbol Parameter Conditions VCC(B) 1.2 V ±0.1 V 1.5 V ±0.1 V 1.8 V ±0.15 V Min Max Min Max Min Unit 2.5 V ±0.2 V 3.3 V ±0.3 V Max Min Max Min Max VCC(A) = 1.1 V to 1.3 V tpd tdis ten propagation delay A to B 1.0 9.0 0.7 6.8 0.6 6.1 0.5 5.7 0.5 6.1 ns B to A 1.0 9.0 0.8 8.0 0.7 7.7 0.6 7.2 0.5 7.1 ns disable time DIR to A 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 ns DIR to B 2.2 8.4 1.8 6.7 2.0 6.9 1.7 6.2 2.4 7.2 ns DIR to A - 17.4 - 14.7 - 14.6 - 13.4 - 14.3 ns DIR to B - 17.8 - 15.6 - 14.9 - 14.5 - 14.9 ns enable time VCC(A) = 1.4 V to 1.6 V tpd tdis ten propagation delay A to B 1.0 8.0 0.7 5.4 0.6 4.6 0.5 3.7 0.5 3.5 ns B to A 1.0 6.8 0.8 5.4 0.7 5.1 0.6 4.7 0.5 4.5 ns disable time DIR to A 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 ns DIR to B 2.0 7.6 1.8 5.9 1.6 6.0 1.2 4.8 1.7 5.5 ns DIR to A - 14.4 - 11.3 - 11.1 - 9.5 - 10.0 ns DIR to B - 14.3 - 11.7 - 10.9 - 10.0 - 9.8 ns enable time VCC(A) = 1.65 V to 1.95 V tpd tdis ten propagation delay A to B 1.0 7.7 0.6 5.1 0.5 4.3 0.5 3.4 0.5 3.1 ns B to A 1.0 6.1 0.7 4.6 0.5 4.4 0.5 3.9 0.5 3.7 ns disable time DIR to A 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 ns DIR to B 1.8 7.8 1.8 5.7 1.4 5.8 1.0 4.5 1.5 5.2 ns DIR to A - 13.9 - 10.3 - 10.2 - 8.4 - 8.9 ns DIR to B - 13.2 - 10.6 - 9.8 - 8.9 - 8.6 ns enable time VCC(A) = 2.3 V to 2.7 V tpd tdis ten propagation delay A to B 1.0 7.2 0.5 4.7 0.5 3.9 0.5 3.0 0.5 2.6 ns B to A 1.0 5.7 0.6 3.8 0.5 3.4 0.5 3.0 0.5 2.8 ns disable time DIR to A 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 ns DIR to B 1.7 7.3 2.0 5.2 1.5 5.1 0.6 4.2 1.1 4.8 ns DIR to A - 13.0 - 9.0 - 8.5 - 7.2 - 7.6 ns DIR to B - 11.4 - 8.9 - 8.1 - 7.2 - 6.8 ns enable time 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 11 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state Symbol Parameter Conditions VCC(B) 1.2 V ±0.1 V 1.5 V ±0.1 V 1.8 V ±0.15 V Min Max Min Max Min Unit 2.5 V ±0.2 V 3.3 V ±0.3 V Max Min Max Min Max VCC(A) = 3.0 V to 3.6 V tpd tdis ten propagation delay A to B 1.0 7.1 0.5 4.5 0.5 3.7 0.5 2.8 0.5 2.4 ns B to A 1.0 6.1 0.6 3.6 0.5 3.1 0.5 2.6 0.5 2.4 ns disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns DIR to B 1.7 7.2 0.7 5.5 0.6 5.5 0.7 4.1 1.7 4.7 ns DIR to A - 13.3 - 9.1 - 8.6 - 6.7 - 7.1 ns DIR to B - 11.8 - 9.2 - 8.4 - 7.5 - 7.1 ns enable time [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. [2] ten is a calculated value using the formula shown in Section 12.4 [1] [2] Table 13. Dynamic characteristics for temperature range -40 °C to +125 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter Conditions VCC(B) 1.2 V ±0.1 V 1.5 V ±0.1 V 1.8 V ±0.15 V Min Max Min Max Min Unit 2.5 V ±0.2 V 3.3 V ±0.3 V Max Min Max Min Max VCC(A) = 1.1 V to 1.3 V tpd tdis ten propagation delay A to B 1.0 9.9 0.7 7.5 0.6 6.8 0.5 6.3 0.5 6.8 ns B to A 1.0 9.9 0.8 8.8 0.7 8.5 0.6 8.0 0.5 7.9 ns disable time DIR to A 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 ns DIR to B 2.2 9.2 1.8 7.4 2.0 7.6 1.7 6.9 2.4 8.0 ns DIR to A - 19.1 - 16.2 - 16.1 - 14.9 - 15.9 ns DIR to B - 19.6 - 17.2 - 16.5 - 16.0 - 16.5 ns enable time VCC(A) = 1.4 V to 1.6 V tpd tdis ten propagation delay A to B 1.0 8.8 0.7 6.0 0.6 5.1 0.5 4.1 0.5 3.9 ns B to A 1.0 7.5 0.8 6.0 0.7 5.7 0.6 5.2 0.5 5.0 ns disable time DIR to A 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 ns DIR to B 2.0 8.3 1.8 6.5 1.6 6.6 1.2 5.3 1.7 6.1 ns DIR to A - 15.8 - 12.5 - 12.3 - 10.5 - 11.1 ns DIR to B - 15.8 - 13.0 - 12.7 - 11.1 - 10.9 ns enable time VCC(A) = 1.65 V to 1.95 V tpd tdis ten propagation delay A to B 1.0 8.5 0.6 5.7 0.5 4.8 0.5 3.8 0.5 3.5 ns B to A 1.0 6.8 0.7 5.1 0.5 4.9 0.5 4.3 0.5 4.1 ns disable time DIR to A 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 ns DIR to B 1.8 8.6 1.8 6.3 1.4 6.4 1.0 5.0 1.5 5.8 ns DIR to A - 15.4 - 11.4 - 11.3 - 9.3 - 9.9 ns DIR to B - 14.6 - 11.8 - 10.9 - 9.9 - 9.6 ns enable time 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 12 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state Symbol Parameter Conditions VCC(B) 1.2 V ±0.1 V 1.5 V ±0.1 V 1.8 V ±0.15 V Min Max Min Max Min Unit 2.5 V ±0.2 V 3.3 V ±0.3 V Max Min Max Min Max VCC(A) = 2.3 V to 2.7 V tpd tdis ten propagation delay A to B 1.0 8.0 0.5 5.2 0.5 4.3 0.5 3.3 0.5 2.9 ns B to A 1.0 6.3 0.6 4.2 0.5 3.8 0.5 3.3 0.5 3.1 ns disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns DIR to B 1.7 8.0 2.0 5.8 1.5 5.7 0.6 4.7 1.1 5.3 ns DIR to A - 14.3 - 10.0 - 9.5 - 8.0 - 8.4 ns DIR to B - 12.7 - 9.9 - 9.0 - 8.0 - 7.6 ns enable time VCC(A) = 3.0 V to 3.6 V tpd tdis ten propagation delay A to B 1.0 7.9 0.5 5.0 0.5 4.1 0.5 3.1 0.5 2.7 ns B to A 1.0 6.8 0.6 4.0 0.5 3.5 0.5 2.9 0.5 2.7 ns disable time DIR to A 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 ns DIR to B 1.7 7.9 0.7 6.1 0.6 6.1 0.7 4.6 1.7 5.2 ns DIR to A - 14.7 - 10.1 - 9.6 - 7.5 - 7.9 ns DIR to B - 13.1 - 10.2 - 9.3 - 8.3 - 7.9 ns enable time [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. [2] ten is a calculated value using the formula shown in Section 12.4 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 13 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state 11.1 Waveforms and test circuit VI VM nA, nB input GND tPHL tPLH VOH nB, nA output VM 001aak114 VOL Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Figure 5. The data input (nA, nB) to output (nB, nA) propagation delay times VI DIR input VM GND t PLZ output LOW-to-OFF OFF-to-LOW t PZL VCCO VM VX VOL t PHZ output HIGH-to-OFF OFF-to-HIGH t PZH VOH VY VM GND outputs enabled outputs disabled outputs enabled 001aae968 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Figure 6. 3-state enable and disable times Table 14. Measurement points [1] [2] Supply voltage Input Output VCC(A), VCC(B) VM VM VX VY 1.1 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH - 0.1 V 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH - 0.15 V 3.0 V to 3.6 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH - 0.3 V [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 14 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 15. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Figure 7. Test circuit for measuring switching times Table 15. Test data Supply voltage Input [1] VCC(A), VCC(B) VI 1.1 V to 1.6 V VCCI 1.65 V to 2.7 V 3.0 V to 3.6 V Load Δt/ΔV [2] VEXT CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO [3] [1] VCCI is the supply voltage associated with the data input port. [2] dV/dt ≥ 1.0 V/ns [3] VCCO is the supply voltage associated with the output port. 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 15 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state 12 Application information 12.1 Unidirectional logic level-shifting application The circuit given in Figure 8 is an example of the 74AVCH2T45 being used in an unidirectional logic level-shifting application. VCC1 VCC(A) VCC1 1A 2A GND VCC1 VCC2 74AVCH2T45 1 8 2 7 3 6 4 5 system-1 VCC(B) VCC2 1B 2B DIR VCC2 system-2 001aag585 Figure 8. Unidirectional logic level-shifting application Table 16. Unidirectional logic level-shifting application 74AVCH2T45 Product data sheet Pin Name Function Description 1 VCC(A) VCC1 supply voltage of system-1 (0.8 V to 3.6 V) 2 1A OUT1 output level depends on VCC1 voltage 3 2A OUT2 output level depends on VCC1 voltage 4 GND GND device GND 5 DIR DIR the GND (LOW level) determines B port to A port direction 6 2B IN2 input threshold value depends on VCC2 voltage 7 1B IN1 input threshold value depends on VCC2 voltage 8 VCC(B) VCC2 supply voltage of system-2 (0.8 V to 3.6 V) All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 16 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state 12.2 Bidirectional logic level-shifting application Figure 9 shows the 74AVCH2T45 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. VCC1 VCC1 VCC2 VCC2 74AVCH2T45 VCC(A) I/O-1 1A 2A GND 1 8 2 7 3 6 4 5 VCC(B) I/O-2 1B 2B DIR DIR CTRL system-1 system-2 001aag586 Figure 9. Bidirectional logic level-shifting application Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Table 17. Bidirectional logic level-shifting application [1] State DIR CTRL I/O-1 I/O-2 Description 1 H output input system-1 data to system-2 2 H Z Z system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on bus hold. 3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on bus hold. 4 L input output system-2 data to system-1 [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 17 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state 12.3 Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 18. Typicaltotal supply current (ICC(A) + ICC(B)) VCC(A) VCC(B) Unit 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0V 0 0.1 0.1 0.1 0.1 0.1 0.1 μA 0.8 V 0.1 0.1 0.1 0.1 0.1 0.7 2.3 μA 1.2 V 0.1 0.1 0.1 0.1 0.1 0.3 1.4 μA 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.9 μA 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.5 μA 2.5 V 0.1 0.7 0.3 0.1 0.1 0.1 0.1 μA 3.3 V 0.1 2.3 1.4 0.9 0.5 0.1 0.1 μA 12.4 Enable times The enable times for the 74AVCH2T45 are calculated from the following formulas: • ten (DIR to nA) = tdis (DIR to nB) + tpd (nB to nA) • ten (DIR to nB) = tdis (DIR to nA) + tpd (nA to nB) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74AVCH2T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 18 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state 13 Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D SOT765-1 E A X c y HE v A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 detail X 4 e L w bp 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A max. max nom min 1 A1 A2 0.15 0.85 0.00 0.60 A3 0.12 D(1) E(2) 0.27 0.23 2.1 2.4 0.17 0.08 1.9 2.2 bp c e HE 0.5 3.2 3.0 L 0.4 Lp Q 0.40 0.21 0.15 0.19 v w y 0.2 0.08 0.1 Z(1) θ 0.4 8° 0.1 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. Outline version SOT765-1 References IEC JEDEC JEITA sot765-1_po European projection Issue date 07-06-02 16-05-31 MO-187 Figure 10. Package outline SOT765-1 (VSSOP8) 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 19 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Figure 11. Package outline SOT883-1 (XSON8) 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 20 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 terminal 1 index area 8 L1 X 0 0.5 scale Dimensions Unit mm max nom min 1 mm A(1) 0.5 A1 b D E e e1 L L1 0.04 0.20 1.40 1.05 0.35 0.40 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1089 sot1089_po References IEC JEDEC JEITA European projection Issue date 10-04-09 10-04-12 MO-252 Figure 12. Package outline SOT1089 (XSON8) 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 21 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm 1 2 SOT1116 b 4 3 (4×)(2) L L1 e 8 7 e1 6 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e e1 max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1116_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1116 Figure 13. Package outline SOT1116 (XSON8) 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 22 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 1 2 3 (4×)(2) 4 L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1203_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1203 Figure 14. Package outline SOT1203 (XSON8) 74AVCH2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 23 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state 14 Abbreviations Table 19. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15 Revision history Table 20. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AVCH2T45 v.7 20180220 Product data sheet - 74AVCH2T45 v.6 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Removed type number 74AVCH2T45GD (SOT996-2/XSON8) 74AVCH2T45 v.6 20130402 Modifications: • For type number 74AVCH2T45GD XSON8U has changed to XSON8. 74AVCH2T45 v.5 20111214 Modifications: • Legal pages updated. 74AVCH2T45 v.4 20101124 74AVCH2T45 v.3 Product data sheet 74AVCH2T45 v.5 - 74AVCH2T45 v.4 Product data sheet - 74AVCH2T45 v.3 20090506 Product data sheet - 74AVCH2T45 v.2 74AVCH2T45 v.2 20090203 Product data sheet - 74AVCH2T45 v.1 74AVCH2T45 v.1 20070703 Product data sheet - - 74AVCH2T45 Product data sheet Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 24 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state 16 Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical 74AVCH2T45 Product data sheet systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 25 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer 74AVCH2T45 Product data sheet design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 February 2018 © Nexperia B.V. 2018. All rights reserved. 26 / 27 74AVCH2T45 Nexperia Dual-bit, dual-supply voltage level translator/transceiver; 3-state Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 11.1 12 12.1 12.2 12.3 12.4 13 14 15 16 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 2 Marking .................................................................2 Functional diagram ............................................. 3 Pinning information ............................................ 3 Pinning ............................................................... 3 Pin description ................................................... 4 Functional description ........................................4 Limiting values .................................................... 5 Recommended operating conditions ................ 5 Static characteristics .......................................... 6 Dynamic characteristics .....................................9 Waveforms and test circuit .............................. 14 Application information .................................... 16 Unidirectional logic level-shifting application .... 16 Bidirectional logic level-shifting application ...... 17 Power-up considerations ................................. 18 Enable times ....................................................18 Package outline .................................................19 Abbreviations .................................................... 24 Revision history ................................................ 24 Legal information .............................................. 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2018. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 20 February 2018 Document identifier: 74AVCH2T45