LC65E1104

Ordering number : EN*5221 CMOS LSI LC65E1104 On-Chip UVEPROM 4-Bit Single-Chip Microcontroller Preliminaly Overview The LC65E1104 is an on-chip UVEPROM version of Sanyo’s LC651104N/F/L and LC651102N/F/L CMOS 4-bit single-chip microcontrollers. The LC65E1104 has the same functions and pin assignment as the LC651104N/F/L and LC651102N/F/L mask ROM products, although the A/D characteristics and certain other characteristics differ somewhat. It includes a 4-KB on-chip EPROM. The LC65E1104 is provided in DIC30S and MFC30S window packages and is ideal for program development and evaluation since program data can be rewritten multiple times. Package Dimensions unit: mm 3212-MFC30S [LC65E1104] Features • EPROM data option switching The following four LC65E1104 functions can be specified by EPROM data: — Port C and D output levels at reset — Clock oscillator option — Clock predivider option — Watchdog reset option However, note that the port output circuit type cannot be changed. These circuits are always open-drain outputs. • Internal UVEPROM capacity: 4096 bytes • The LC65E1104 on-chip UVEPROM can be programmed and verified using a general-purpose EPROM programmer. Sanyo provides special-purpose 30-to-28-pin adapters (the W65EP1104D for the DIC package and the W65EP1104M for the MFC package) to allow commercial EPROM programmers to be used with the LC65E1104. • Data security function • Pin compatible with the LC651104/1102 mask ROM devices • Instruction cycle time: 0.92 µs to 20 µs (A/D converter cycle time: 0.98 µs to 12 µs) • Factory shipment: DIC-30S (with window), MFC-30S (with window) SANYO: MFC30S unit: mm 3215-DIC30S [LC65E1104] SANYO: DIC30S Note: These figures are provided for reference purposes and do not include tolerance specifications. Official drawings are available on request from your Sanyo representative. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 73096HA (OT) No. 5221-1/19 LC65E1104 LC651104/1102 series organization Model name LC651104N/F/L, LC651102N/F/L LC65E1104 LC65P1104 Pins 30 30 30 ROM capacity 4 k/2 k 4k 4k RAM capacity 256 W 256 W 256 W Package DIP30S, DIP30S-D, MFP30S DIC30S, MFC30S DIP30S-D, MFP30S Pin Assignment Common to DIC/MFC Usage Notes The LC65E1104 was designed for developing and evaluating programs for the LC651104/1102 series microcontrollers. Keep the following points in mind when using the LC65E1104. 1. Protecting EPROM data from UV exposure Keep the LC65E1104’s package window covered with an opaque seal when using the device. 2. The LC65E1104 differs from the LC651104N/F/L and LC651102N/F/L as listed in the table below. Item I/O circuit configuration Port C and D output levels at reset Resonator Oscillator Predivider option Watchdog reset Operating supply voltage range (VDD) Normal mode current drain Low-level input current (RES terminal) Operating temperature range Package LC65E1104 Open drain (N channel) High or low selected in 4-bit units (by EPROM data) RC/ceramic (by EPROM data) 1/1, 1/3, 1/4 (by EPROM data) Available/not available (by EPROM data) 3.0 to 6.0 V* Mask version + about 3 mA (typical) –50 µA (typical) +10 to +40°C DIC30S (with window) MFC30S (with window) 4.0 t 6.0 V 2 mA (typical) 1/1 only (user mask option) LC651104F/1102F LC651104N/1102N LC651104L/1102L Open drain or pull-up resistor-provided output selectable bit by bit (user mask option) High or low selected in 4-bit units (user mask option) RC/ceramic (user mask option) 1/1, 1/3, 1/4 (user mask option) Available/not available (user mask option) 3.0 to 6.0 V 1.5 mA (typical) –10 µA (typical) –40 to +85°C DIP30S, DIP30S-D MFP30S 2.5 to 6.0 V 1.5 mA (typical) Note: A/D converter operating supply voltage range: 4.7 to 5.3 V No. 5221-2/19 LC65E1104 Pin Names OSC1, OSC2 RES PA0 to PA3 PC0 to PC3 PD0 to PD3 PE0 to PE1 PF0 to PF3 PG0 to PG3 RC or ceramic oscillator Reset Shared-function I/O ports A0 to A3 Shared-function I/O ports C0 to C3 Shared-function I/O ports D0 to D3 Shared-function I/O ports E0 to E1 Shared-function I/O ports F0 to F3 Shared-function I/O ports G0 to G3 TEST INT SI SO SCK AD0 to AD7 AV+, AV– WDR Test Interrupt request pin Serial input pin Serial output pin Serial clock input/output pin AD converter input pin AD converter reference voltage input Watchdog reset pin Note: The SI, SO, SCK, and INT pins are shared function pins that are also used as the PF0 to PF3 pins, respectively. System Block Diagram RAM F WR AC ALU DP E CTL OSC TM Data memory Flag Working register Accumulator Arithmetic and logic unit Data pointer E register Control register Oscillator Timer ROM PC INT IR I.DEC CF, ZSF ZF, ZSC EXTF TMF STS Program memory Program counter Interrupt control Instruction register Instruction decoder Carry flag, Carry save flag Zero flag, zero save flag External interrupt request flag Internal interrupt request flag Status register No. 5221-3/19 LC65E1104 Pin Description Symbol VDD VSS Pins 1 1 I/O — — Power supply Function Option — 1. Pin 2: RC oscillator external clock 2. Pin 2: Ceramic oscillator 3. Predivider option • No predivider • 1/3 predivider • 1/4 predivider At reset — PROM mode — OSC1/DASEC 1 I OSC2 1 O • Connections for the external RC or ceramic oscillator circuit used as the system clock oscillator. • If external clock input is used, leave the OSC2 pin open. • I/O port: A0 to A3 Input in 4-bit units (IP instruction) Output in 4-bit units (OP instruction) Testing in single-bit units (BP and BNP instructions) Setting or clearing in single-bit units (SPB and RPB instructions) • Standby is controlled by PA3 • The PA3 pin must be free from chattering during the halt instruction execution cycle. Each of these four pins has two functions as listed below. PA0/AD0: AD converter input pin AD0 PA1/AD1: AD converter input pin AD1 PA2/AD2: AD converter input pin AD2 PA3/AD3: AD converter input pin AD3 • I/O port: C0 to C3 Identical to PA0 to PA3* • Option permits output at reset to be high or low. Note: * No standby control function is provided. — EPROM control signal DASEC PA0/AD0/A1 PA1/AD1/A2 PA2/AD2/A3 PA3/AD3/A4 4 I/O Open drain type output High-level output (Output Nch transistor: Off) Address inputs A1 to A4 PC0/D0 PC1/D1 PC2/D2 PC3/D3 4 I/O 1. Open drain type output 2. Output at reset: high 3. Output at reset: low 2., 3.: Specified in a group of 4 bits • High-level output • Low-level output (Option-selectable) Data lines D0 to D3 PD0/D4 PD1/D5 PD2/D6 PD3/D7 4 I/O I/O port: D0 to D3 Identical to PC0 to PC3 Identical to PC0 to PC3 Identical to PC0 to PC3 Data lines D4 to D7 PE0/CE PE1/WDR/A0 2 I/O • I/O port: E0 and E1 Input in 4-bit units (IP instruction) Output in 4-bit units (OP instruction) Setting or clearing in single-bit units (SPB, RPB instructions) Testing in single-bit units (BP and BNP instructions) • PE0 provides a continuous burst (64·Tcyc) function. • I/O ports F0 tp F3 Identical to PE0 to PE1* • Shared with the serial interface and INT input. Program-selectable SI Serial input port SO Serial output port SCK Serial clock input/output INT Interrupt request input The serial I/O function can be switched between 4-bit and 8-bit operation under program control. Note: * No burst pulse output function is provided. 1. Open drain type output High-level output (Output Nch transistor: Off) • EPROM control signal CE • Address input A0 PF0/SI/A9 PF1/SO/A10 PF2/SCK/A11 PF3/INT/TA 4 I/O Identical to PE0 to PE1 Identical to PE0 to PE1 Serial port: Disabled Interrupt source: INT • Address inputs A9 to A11 • EPROM control signal TA Continued on next page. No. 5221-4/19 LC65E1104 Continued from preceding page. Symbol Pins I/O Function • I/O ports G0 to G3 Identical to PE0 to PE1* Note: * No burst pulse output function is provided. • Each of these four pins has two functions as listed below. PG0/AD4: AD converter input pin AD4 PG1/AD5: AD converter input pin AD5 PG2/AD6: AD converter input pin AD6 PG3/AD7: AD converter input pin AD7 Reference voltage input pin for A/D conversion. • System reset input • Connect an external capacitor for power on reset. • Apply a low level for at least 4 clock cycles for the power-on reset. LSI test pin Normally connected to VSS Option At reset PROM mode PG0/AD4/A5 PG1/AD5/A6 PG2/AD6/A7 PG3/AD7/A8 4 I/O Identical to PE0 to PE1 Identical to PE0 to PE1 Address inputs A5 to A8 AV+ AV– 1 1 — — — — — RES/VPP/OE 1 — — EPROM control signal VPP/OE TEST/EPMOD 1 — — EPROM control signal EPMOD Oscillator circuit option Option Circuit Conditions and notes 1. External clock Leave the OSC2 pin open. 2. 2-pin RC OSC 3. Ceramic oscillator Predivider option Option Circuit Conditions and notes • Applicable to all 3 oscillator options. • The oscillator or external clock frequency must not exceed 1444 kHz. (LC651104N, LC651102N) • The oscillator or external clock frequency must not exceed 4330 kHz. (LC651104F, LC651102F) • The oscillator or external clock frequency must not exceed 1040 kHz. (LC651104L, LC651102L) • Applicable to the external clock and ceramic oscillator options. • The oscillator or external clock frequency must not exceed 4330 kHz. 1. No predivider (1/1) 2. 1/3 predivider 3. 1/4 predivider • Applicable to the external clock and ceramic oscillator options. • The oscillator or external clock frequency must not exceed 4330 kHz. Note: The oscillator and predivider options are summarized in the LC651104/1102 semiconductor news. No. 5221-5/19 LC65E1104 Port C and D reset output level options Either of the following two options may be selected for the C and D I/O ports. Note that these options are specified in 4bit units. Option name 1. Output at reset: high 1. Output at reset: low Conditions All 4 bits of the selected port(s) (C or D or both) All 4 bits of the selected port(s) (C or D or both) Port output configuration option All shared-function I/O ports have an open-drain output circuit in the LC65E1104. Option Circuit Conditions and notes 1. Open drain output Ports A, C, D, E and F Watchdog reset option This option specifies the use of the PE1/WDR pin. This pin can be specified to function either as the normal port PE1 or as the WDR watchdog reset pin. Usage Notes 1. Option specification The SU60K.EXE program is used for option specification. The option code for the option specification area (addresses 1000 to 100A (hexadecimal)) is created by assembling the output of the SU60K.EXE program using the Sanyo M60K.EXE macro assembler and then linking the macro assembler output with the Sanyo L60K.EXE linker. It is also possible to load data directly into the option specification area. Specify options according to the option code creation table on page 8. 2. PROM programming LC65E1104 can be programmed with a general-purpose EPROM programmer using either the W65EP1104D or W65EP1104M adapter. • Recommended EPROM programmers Manufacturer Advantest Ando AVAL Minato electronics EPROM programmer R4945, R4944, R4943 or equivalent programmer AF-9704 — — • The Intel 27512 (VPP: 12.5 V) high-speed programming method must be used to program this device. The address range must be set to 0 to 100A (hexadecimal) and the DASEC jumper must be set to the off position. 3. Using the data security function The data security function prevents data already written to the microcontroller's PROM from being overwritten. LC651104 data security function procedure • Move the DASEC jumper on the EPROM programming pin adapter to the on position. This enables the data security function. • Attempt to reprogram the EPROM. Since the data security function is enabled, the EPROM programmer will display an error. Note that this error is not due to an error in either the programmer or the LSI. No. 5221-6/19 LC65E1104 Note: 1. At step 2, the data security function will not operate if all the data at the addresses to be programmed have the value FF (hexadecimal). Note: 2. At step 2, the data security function will not apply to (i.e., will not prevent) programming using the sequence BLANK Æ PROGRAM Æ VERIFY. Note: 3. Return the jumper to the off position after executing the data security function. DASEC jumper setting No. 5221-7/19 LC65E1104 Option specification area ROM area Bit 7 6 5 1000H 4 3 2 1 0 7 6 5 1001H 4 3 2 1 0 7 6 5 1002H 4 3 2 1 0 7 6 5 1003H 4 3 2 1 0 7 6 5 1004H to 100AH 4 3 2 1 0 Note: Since all LC65E1104 ports are open-drain output circuits, the pull-up resistor options are ignored. However, the port options must be selected when using the LC651104/1102 mask ROM products. PU: Built-in pull-up resistor output circuit, OD: Open-drain output circuit Unused 0 (fixed) Unused Watchdog reset PD PC Output level at reset Option specified 0 (fixed) 0: Disabled, 1: Enabled 0: Low level, 1: High level Option/data relationship OSC predivider (XX = bits 3, bit 2) 00: 1/1, 01: 1/3, 10: 1/4,. 11: unused OSC resonator (XX = bits 1, bit 0) PC3 PC2 PC1 PC0 PA3 PA2 PA1 PA0 Unused PE1 PE0 PD3 PD2 PD1 PD0 PG3 PG2 PG1 PG0 PF3 PF2 PF1 PF0 Output configuration Output configuration Output configuration Output configuration Output configuration 00: unused, 01: unused, 10: (2RC, EXT), 11: Ceramic 0: OD, 1: PU* 0: OD, 1: PU* 0 (fixed) Output configuration 0: OD, 1: PU* 0: OD, 1: PU* 0: OD, 1: PU* 0: OD, 1: PU* No. 5221-8/19 LC65E1104 Specifications For LC651104N, 651102N Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Output voltage Input voltage Symbol VDD max VO VI1 VI2 VIO1 VIO2 IOP IOA Average output current ΣIOA1 ΣIOA2 Allowable power dissipation Operating temperature Storage temperature Pd max1 Pd max2 Topr Tstg VDD OSC2 OSC1*1 TEST, RES, AV+, AV– PC0 to PC3, PD0 to PD3, PE0, PE1, PF0 to PF3 PA0 to PA3, PG0 to PG3 I/O port I/O port: Per pin over a 100 ms period PC0 to PC3, PD0 to PD3, PE0, PE1:Total current for PC0 to PC3, PD0 to PD3, and PE0, PE1*2 PF0 to PF3, PG0 to PG3, PA0 to PA3: Total current for PF0 to PF3, PG0 to PG3, and PA0 to PA3*2 Ta = +10 to +40°C (DIC package) Ta = +10 to +40°C (MFC package) Conditions Ratings –0.3 to +7.0 Allowable up to the generated voltage –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –0.3 to +15 –0.3 to VDD + 0.3 –2 to +20 –2 to +20 –15 to +100 –15 to +100 250 150 +10 to +40 –55 to +125 Unit V V V V V V mA mA mA mA mW mW °C °C Input/output voltage Peak output current Allowable Operating Conditions at Ta = +10 to +40°C, VSS = 0 V, VDD = 3.0 to 6.0 V Parameter Operating supply voltage Standby supply voltage Symbol VDD VST VIH1 VIH2 High level input voltage VIH3 VIH4 VIH5 VIL1 VIL2 VIL3 VIL4 Low level input voltage VIL5 VIL6 VIL7 VIL8 VIL9 VIL10 Operating frequency (cycle time) [External clock conditions] Frequency Pulse width Rise/fall time [Oscillator guaranteed constants] Cext 2-pin RC oscillator Cext Rext Rext Ceramic OSC1, OSC2: Fig 2, VDD = 3 to 6 V OSC1, OSC2: Fig 2, VDD = 4 to 6 V OSC1, OSC2: Fig 2, VDD = 3 to 6 V OSC1, OSC2: Fig 2, VDD = 4 to 6 V Fig 3 270 ± 5% 270 ± 5% 12 ± 1% 4.7 ± 1% Table 1 pF pF kΩ kΩ text textH, textL textR, textF OSC1: Fig 1, when clock exceeds 1.444 MHz, the 1/3 or 1/4 predivider option must be selected. VDD = 3 to 6 V 200 69 50 4330 kHz ns ns fop (Tcyc) VDD VDD: RAM, register hold*3 Port C, D, E, F: Output Nch Tr. off Port A, G: Output Nch Tr. off INT, SCK, SI: Output Nch Tr. off RES: VDD = 1.8 to 6 V OSC1: External clock mode Port: Output Nch Tr. off, VDD = 4 to 6 V Port: Output Nch Tr. off, VDD = 3 to 6 V INT, SCK, SI: Output Nch Tr. off, VDD = 4 to 6 V INT, SCK, SI: Output Nch Tr. off, VDD = 3 to 6 V OSC1: External clock mode, VDD = 4 to 6 V OSC1: External clock mode, VDD = 3 to 6 V TEST: VDD = 4 to 6 V TEST: VDD = 3 to 6 V RES: VDD = 4 to 6 V RES: VDD = 3 to 6 V When the 1/3 or 1/4 predivider option is selected, clock must not exceed 4.33 MHz. VDD = 3 to 6 V Conditions Ratings min 3.0 1.8 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD 0.8 VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 200 (20) typ max 6.0 6.0 +13.5 VDD +13.5 VDD VDD 0.3 VDD 0.25 VDD 0.25 VDD 0.2 VDD 0.25 VDD 0.2 VDD 0.3 VDD 0.25 VDD 0.25 VDD 0.2 VDD 1444 (2.77) Unit V V V V V V V V V V V V V V V V V kHz (µs) No. 5221-9/19 LC65E1104 Electrical Characteristics at Ta = +10 to +40°C, VSS = 0 V, VDD = 3.0 to 6.0 V Parameter Symbol IIH1 High-level input current IIH2 IIH3 IIL1 Low-level input current IIL2 IIL3 VOL1 Low-level output current [Schmitt characteristics] Hysteresis voltage High-level threshold voltage Low-level threshold voltage [Current dissipation] 2-pin RC oscillator IDDOP1 IDDOP2 Ceramic oscillator IDDOP3 IDDOP4 IDDOP5 External clock IDDOP6 VDD: Output Nch Tr. off at operating, port = VDD, Fig. 2, fosc = 900 kHz (typ) VDD: Fig 3, 4 MHz, 1/3 predivider VDD: Fig 3, 4 MHz, 1/4 predivider VDD: Fig 3, 400 kHz VDD: Fig 3, 800 kHz VDD: 200 kHz to 1444 kHz, 1/1 predivider; 600 kHz to 4330 kHz, 1/3 predivider; 800 kHz to 4330 kHz, 1/4 predivider VDD: Output Nch Tr. off, VDD = 6 V VDD: Port = VDD, VDD = 3 V OSC1, OSC2: Fig 3, fo = 400 kHz OSC1, OSC2: Fig 3, fo = 800 kHz Ceramic OSC frequency fCFOSC*5 OSC1, OSC2: Fig 3, fo = 1 MHz OSC1, OSC2: Fig 3, fo = 4 MHz, 1/3 predivider, 1/4 predivider Fig 4, fo = 400 kHz Stabilization tCFS Fig 4, fo = 800 kHz, 1 MHz, 4 MHz, 1/3 predivider, 1/4 predivider OSC1, OSC2: Fig. 2, Cext = 270 pF ± 5%, Fig. 2, Rext = 4.7 kΩ ± 1%, VDD = 4 to 6 V OSC1, OSC2: Fig. 2, Cext = 270 pF ± 5%, Fig. 2, Rext = 12 kΩ ± 1%, VDD = 3 to 6 V RES: VIN = VSS, VDD = 5 V 666 283 900 400 384 768 960 3840 4.5 4.5 4.5 4.0 4.5 4.5 0.05 0.025 6 7 6 4.5 6 7 10 5 mA mA mA mA mA mA µA µA VHIS VtH VtL RES, INT, SCK, SI, OSC1 of Schmitt type*4 0.4 VDD 0.2 VDD 0.1 VDD 0.8 VDD 0.6 VDD V V V VOL2 Conditions Port C, D, E, F: Output Nch Tr. off (including off leak current of Nch Tr.), VIN = +13.5 Port A, G: Output Nch Tr. off (including off leak current of Nch Tr.), VIN = VDD OSC1: External clock mode, VIN = VDD Port: Output Nch Tr. off, VIN = VSS RES: VIN = VSS OSC1: External clock mode, VIN = VSS Port: IOL = 10 mA, VDD = 4.0 to 6.0 V Port: IOL = 1 mA, IOL of each port; 1 mA or less VDD = 3.0 to 6.0 V –1.0 –150 –1.0 1.5 0.5 –50 Ratings min typ max +5.0 +5.0 +1.0 Unit µA µA µA µA µA µA V V Standby mode [Oscillator characteristics] IDDst 400 800 1000 4000 416 832 1040 4160 10 10 1334 717 kHz kHz kHz kHz ms ms kHz kHz 2-pin RC oscillator frequency [Pull-up resistance] I/O port RES: [External reset characteristics] Reset time Pin capacitance [Serial clock] Input clock cycle time Output clock cycle time Input clock low-level pulse width Output clock low-level pulse width Input clock high-level pulse width Output clock high-level pulse width [Serial input] Data setup time Data hold time fMOSC RU 50 100 250 kΩ tRST CP f = 1 MHz. VIN = VSS for all pins other than those being tested. See Fig. 5 10 pF tCKCY1 tCKCY2 tCKL1 tCKL2 tCKH1 tCKH2 SCK: Fig. 6 SCK: Fig. 6 SCK: Fig. 6 SCK: Fig. 6 SCK: Fig. 6 SCK: Fig. 6 3.0 64 × tCYC*6 1.0 32 × tCYC 1.0 32 × tCYC 0.4 0.4 µs µs µs µs µs µs tICK tCKI SI: Specified from the rising edge of SCK. Fig. 6 µs µs Continued on next page. No. 5221-10/19 LC65E1104 Continued from preceding page. Parameter [Serial output] Output delay time [Pulse output] Period High-level pulse width Low-level pulse width [AD conversion characteristics] Resolution Absolute accuracy VDD = 4.7 to 5.3 V AV+ = VDD, AV– = VSS, VDD = 4.7 to 5.3 V AD speed 1/1, at 26 × tCYC, VDD = 4.7 to 5.3 V Conversion time TCAD AD speed 1/2, at 51 × tCYC, VDD = 4.7 to 5.3 V Reference input voltage Reference input current range Analog input voltage range AV+ AV– IRIF VAIN AV+: VDD = 4.7 to 5.3 V AV–: VDD = 4.7 to 5.3 V AV+, AV–: AV+ = VDD, VDD = 4.7 to 5.3 V, AV– = VSS AD0 to AD7: VDD = 4.7 to 5.3 V Port pins AD0 to AD7 Including output OFF leakage current. VAIN = VDD, VDD= 4.7 to 5.3 V Port pins AD0 to AD7 VAIN = VSS, VDD= 4.7 to 5.3 V [Watchdog timer] Cw Guaranteed constant*7 Rw RI Clear time (discharge) Clear time (charge) tWCT tWCCY Cw Guaranteed constant*7 Rw RI Clear time (discharge) Clear time (charge) tWCT tWCCY WDR: VDD = 3 to 6 V WDR: VDD = 3 to 6 V WDR: VDD = 3 to 6 V WDR: Fig. 8, VDD = 3 to 6 V WDR: Fig. 8, VDD = 3 to 6 V WDR: VDD = 4 to 6 V WDR: VDD = 4 to 6 V WDR: VDD = 4 to 6 V WDR: Fig. 8, VDD = 4 to 6 V WDR: Fig. 8, VDD = 4 to 6 V 40 18 100 36 0.047 ± 5% 680 ± 1% 100 ± 1% 0.1 ± 5% 680 ± 1% 100 ± 1% µF kΩ Ω µs ms µF kΩ Ω µs ms 72 (tCYC = 2.77 µs) 141 (tCYC = 2.77 µs) AV– VSS 75 AV– 150 8 ±1 ±2 312 (tCYC = 12 µs) 612 (tCYC = 12 µs) VDD AV+ 300 AV+ bits LSB tPCY tPH tPL PE0: Fig. 7, tCYC = 4 × system clock period, Nch OD only, external 1 kΩ, external 50 pF 64 ×tCYC 32 × tCYC ± 10% 32 × tCYC ± 10% µs µs µs tCKO SO: Specified from the falling edge of SCK. Nch OD only, external 1kΩ, external 50 pF, Fig. 6 0.6 µs Symbol Conditions Ratings min typ max Unit µs V µA V 1 µA –1 Analog port input current IAIN Note: 1. The LC65E1104 will accept input voltages up to the generated oscillator amplitude if the oscillator circuit in figure 4 with circuit constants in the guaranteed constants ranges is driven from within the IC. 2. Average over a 100 ms period 3. The operating supply voltage VDD must be held until standby mode is enterd after the execution of a HALT instruction. The PA3 pin must be free from chattering during the HALT instruction cycle. 4. The OSC1 pin input circuit has Schmitt trigger characteristics when the 2-terminal RC oscillator option or the external clock oscillator option is selected. 5. fCFOSC: oscillator frequency. The center frequency of a ceramic oscillator has a tolerance range of about 1% around the nominal value specified by the manufacturer of the oscillator element. For details, refer to the specifications of the ceramic resonator. 6. TCYC = 4 × system clock period 7. If the LC65E1104 is used in an environment subject to condensation, leakage between PE1 and adjacent pins and leakage associated with external RCA circuits require special attention. No. 5221-11/19 LC65E1104 Fig. 1 External Clock Input Waveform Fig. 2 2-pin RC Oscillator Circuit Fig. 3 Ceramic Oscillator Fig. 4 Oscillator Stabilization Period No. 5221-12/19 LC65E1104 Table 1 Constants Guaranteed for Ceramic Resonator Oscillator 4 MHz (Murata) CSA4.00MG CST4.00MGW (built-in C) 4 MHz (Kyocera) KBR4.0 MSA KBR4.0MKS (built-in C) 1 MHz (Murata) CSB1000J C1 C2 R C1 C2 R C1 C2 R C1 1 MHz (Kyocera) KBR1000F C2 R C1 800 kHz (Murata) CSB800J C2 R C1 800 kHz (Kyocera) KBR800F C2 R C1 400 kHz (Murata) CSB400P C2 R C1 400 kHz (Kyocera) KBR400BK C2 R 33 pF ± 10% 33 pF ± 10% 0Ω 33 pF ± 10% 33 pF ± 10% 0Ω 100 pF ± 10% 100 pF ± 10% 2.2 kΩ 100 pF ± 10% 100 pF ± 10% 0 kΩ 100 pF ± 10% 100 pF ± 10% 2.2 kΩ 220 pF ± 10% 220 pF ± 10% 0 kΩ 220 pF ± 10% 220 pF ± 10% 2.2 kΩ 330 pF ± 10% 330 pF ± 10% 0 kΩ Fig. 5 Reset Circuit Note: When the rise time of the power supply is close to 0, the reset time will be between 10 and 100 ms for a CRES of 0.5 µF. If the rise time of the power supply is significantly longer, the value of CRES must be increased so that the reset time will be 10 ms or longer. Note: The constants above are preliminarlly. Final ratings will be fixed after evaluation. Fig. 6 Serial Input /Output Timing Fig. 7 Pulse Output Timing at Port PE0 No. 5221-13/19 LC65E1104 Note: 1. tWCCT: The charge time due to the time constant of the external Cw, Rw, and R1 components 2. tWCT: The discharge time due to program operation Fig. 8 Watchdog Timer Waveform No. 5221-14/19 LC65E1104 For LC651104F, 651102F Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Output voltage Input voltage Symbol VDD max VO VI1 VI2 VIO1 VIO2 IOP IOA Average output current ΣIOA1 ΣIOA2 Allowable power dissipation Operating temperature Storage temperature Pd max1 Pd max2 Topr Tstg VDD OSC2 OSC1*1 TEST, RES, AV+, AV– PC0 to PC3, PD0 to PD3, PE0, PE1, PF0 to PF3 PA0 to PA3, PG0 to PG3 I/O port I/O port: Per pin over a 100 ms period PC0 to PC3, PD0 to PD3, PE0, PE1:Total current for PC0 to PC3, PD0 to PD3, and PE0, PE1*2 PF0 to PF3, PG0 to PG3, PA0 to PA3: Total current for PF0 to PF3, PG0 to PG3, and PA0, PA3*2 Ta = +10 to +40°C (DIC package) Ta = +10 to +40°C (MFC package) Conditions Ratings –0.3 to +7.0 Allowable up to the generated voltage –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –0.3 to +15 –0.3 to VDD + 0.3 –2 to +20 –2 to +20 –15 to +100 –15 to +100 250 150 +10 to +40 –55 to +125 Unit V V V V V V mA mA mA mA mW mW °C °C Input/output voltage Peak output current Allowable Operating Conditions at Ta = +10 to +40°C, VSS = 0 V, VDD = 4.0 to 6.0 V Parameter Operating supply voltage Standby supply voltage Symbol VDD VST VIH1 VIH2 High-level input voltage VIH3 VIH4 VIH5 VIL1 VIL2 Low-level input voltage VIL3 VIL4 VIL5 Operating frequency (cycle time) [External clock conditions] Frequency Pulse width Rise/fall time Oscillation guaranteed constants ceramic resonator oscillator text textH, textL OSC1: Fig. 1 textR, textF OSC1: Fig. 1 Fig. 2 See Table 1 200 69 50 4330 kHz ns ns fOP (Tcyc) VDD VDD: RAM, register hold*3 Port C, D, E, F: Output Nch Tr. OFF Port A, G: Output Nch Tr. OFF INT, SCK, SI: Output Nch Tr. OFF RES: VDD = 1.8 to 6.0 V OSC1: External clock mode Port: Output Nch Tr. OFF INT, SCK, SI: Output Nch Tr. OFF OSC1: External clock TEST RES Conditions Ratings min 4.0 1.8 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD 0.8 VDD VSS VSS VSS VSS VSS 200 (20) typ max 6.0 6.0 +13.5 VDD +13.5 VDD VDD 0.3 VDD 0.25 VDD 0.25 VDD 0.3 VDD 0.25 VDD Unit V V V V V V V V V V V V 4330 (0.92) kHz (µs) No. 5221-15/19 LC65E1104 Electrical Characteristics at Ta = +10 to +40°C, VSS = 0 V, VDD = 4.0 to 6.0 V Parameter Symbol IIH1 High-level input current IIH2 IIH3 IIL1 Low-level input current IIL2 IIL3 Low-level output voltage [Schmitt characteristics] Hysteresis voltage High-level threshold voltage Low-level threshold voltage [Current drain] Ceramic resonator oscillator External clock Standby mode [Oscillator characteristics] Ceramic resonator oscillator Frequency stabilization time [Pull-up resistance] I/O port RES [External reset characteristics] Reset time Pin capacitance [Serial clock] Input clock cycle time Output clock cycle time Input clock low-level pulse width Output clock low-level pulse width Input clock high-level pulse width Output clock high-level pulse width [Serial input] Data setup time Data hold time [Serial output] Output delay time [Pulse output] Period High-level pulse width Low-level pulse width tPCY tPH tPL PE0: Fig. 6, tCYC = 4 × system clock period, Nch OD only, external 1 kΩ, external 50 pF 64 × tCYC 32 × tCYC ± 10% 32 × tCYC ± 10% µs µs µs tCKO SO: Specified from the falling edge of SCK. Nch OD only, external 1 kΩ, external 50 pF, Fig.5 0.4 µs tICK tCKI SI: Specified from the rising edge of SCK. Fig. 5 0.2 0.2 µs µs tCKCY1 tCKCY2 tCKL1 tCKL2 tCKH1 tCKH2 SCK: Fig. 5 SCK: Fig. 5 SCK: Fig. 5 SCK: Fig. 5 SCK: Fig. 5 SCK: Fig. 5 0.6 32 × tCYC 0.6 32 × tCYC 2.0 64 × tCYC*6 µs µs µs µs µs µs tRST CP f = 1 MHz. VIN = VSS for all pins other than those being tested. See Fig. 4 10 pF RU RES: VIN = VSS, VDD = 5 V 50 100 250 kΩ fCFOSC tCFS OSC1, OSC2: Fig.2, fo = 4 MHz*5 Fig. 3, fo = 4 MHz 3840 4000 4160 10 kHz ms IDDOP1 IDDOP2 IDDst VDD: Fig. 2, 4 MHz, 200 kHz to 4330 kHz* Note: * Output Nch Tr. OFF at operating mode, port = VDD VDD: Output Nch Tr. OFF, VDD = 6 V VDD: Port = VDD, VDD = 3 V 5 5 0.05 0.025 8 8 10 5 mA mA µA µA VHIS VtH VtL RES, INT, SCK, SI, OSC1 of Schmitt type*4 0.4 VDD 0.25 VDD 0.1 VDD 0.8 VDD 0.6 VDD V V V VOL1 VOL2 Conditions Port C, D, E, F: Output Nch Tr. OFF, (Including the Nch. transistor off state leakage current.), VIN = +13.5 Port A, G: Output Nch Tr. OFF, (Including the Nch. transistor off state leakage current.), VIN = VDD OSC1: External clock mode, VIN = VDD Port of OD type: Output Nch Tr. OFF, VIN = VSS RES: VIN = VSS OSC1: External clock mode, VIN = VSS Port: IOL = 10 mA Port: IOL = 1 mA, IOL of each port; 1 mA or less –1.0 –150 –1.0 1.5 0.5 –50 Ratings min typ max +5.0 +5.0 +1.0 Unit µA µA µA µA µA µA V V Continued on next page. No. 5221-16/19 LC65E1104 Continued from preceding page. Parameter [AD conversion characteristics] Resolution Absolute accuracy VDD = 4.7 to 5.3 V AV+ = VDD, AV– = VSS, VDD = 4.7 to 5.3 V AD speed 1/1, at 26 × tCYC, VDD = 4.7 to 5.3 V Conversion time tCAD AD speed 1/2, at 51 × tCYC, VDD = 4.7 to 5.3 V Reference input voltage Reference input current range Analog input voltage range AV+ AV– IRIF VAIN AV+: VDD = 4.7 to 5.3 V AV–: VDD = 4.7 to 5.3 V AV+, AV–: AV+ = VDD, VDD = 4.7 to 5.3 V, AV– = VSS AD0 to AD7: VDD = 4.7 to 5.3 V Port pins AD0 to AD7 Including output OFF leakage current. VAIN = VDD, VDD= 4.7 to 5.3 V Port pins AD0 to AD7 VAIN = VSS, VDD= 4.7 to 5.3 V [Watchdog timer] Cw Guaranteed constants Rw RI Clear time (discharge) Clear time (charge) tWCT tWCCY WDR WDR WDR WDR: Fig. 7 WDR: Fig. 7 10 42 0.01 ± 5% 680 ± 1% 100 ± 1% µF kΩ Ω µs ms 25 (tCYC = 0.98 µs) 50 (tCYC = 0.98 µs) AV– VSS 75 AV– 150 8 ±1 ±2 312 (tCYC = 12 µs) 612 (tCYC = 12 µs) VDD AV+ 300 AV+ bits LSB µs µs V µA V Symbol Conditions Ratings min typ max Unit 1 µA –1 Analog port input current IAIN Note: 1. The LC65E1104 will accept input voltages up to the generated oscillator amplitude if the oscillator circuit in figure 2 with circuit constants in the guaranteed constants ranges is driven internally. 2. Average over a period of 100 ms. 3. The operating supply voltage VDD must be held until standby mode is entered after the execution of a HALT instruction. The PA3 pin must be free from chattering during the HALT instruction execution cycle. 4. The OSC1 pin input circuit has Schmitt trigger characteristics when the external clock oscillator option is selected. 5. fCFOSC: Oscillator frequency 6. TCYC = 4 × system clock period 7. If the LC65E1104 is used in an environment subject to condensation, leakage between PE1 and adjacent pins and leakage associated with external RCA circuits require special attention. Fig. 1 External Clock Input Waveform No. 5221-17/19 LC65E1104 Fig. 2 Ceramic Oscillator Circuit Fig. 3 Oscillator Stabilization Period Table 1 Constants Guaranteed for Ceramic Resonator Oscillator 4 MHz (Murata) CSA4.00MG CST4.00MGW (built-in C) 4 MHz (Kyocera) KBR4.0 MSA KBR4.0MKS (built-in C) C1 C2 R C1 C2 R 33 pF ± 10% 33 pF ± 10% 0Ω 33 pF ± 10% 33 pF ± 10% 0Ω Note: The constants above are preliminarlly. Final ratings will be fixed after evaluation. Fig. 4 Reset Circuit Note: When the rise time of the power supply is close to 0, the reset time will be between 10 and 100 ms for a CRES of 0.5 µF. If the rise time of the power supply is significantly longer, the value of CRES must be increased so that the reset time will be 10 ms or longer. Fig. 5 Serial Input /Output Timing No. 5221-18/19 LC65E1104 Fig. 6 Pulse Output Timing at Port PE0 Note: 1. tWCCY: The charge time due to the time constant of the external Cw, Rw, and R1 components 2. tWCT: The discharge time due to program operation Fig. 7 Watchdog Timer Waveform s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5221-19/19