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SFP70N06

SFP70N06

  • 厂商:

    SEMIWELL

  • 封装:

  • 描述:

    SFP70N06 - N-Channel MOSFET - SemiWell Semiconductor

  • 数据手册
  • 价格&库存
SFP70N06 数据手册
PRELIMINARY SemiWell Semiconductor SFP70N06 N-Channel MOSFET Features ■ ■ ■ ■ ■ ■ Low RDS(on) (0.014Ω )@VGS=10V Low Gate Charge (Typical 70nC) Low Crss (Typical 160pF) Improved dv/dt Capability 100% Avalanche Tested Maximum Junction Temperature Range (175°C) Symbol ● 2. Drain 1. Gate ◀ ● ● ▲ 3. Source General Description This Power MOSFET is produced using SemiWell’s advanced planar stripe, DMOS technology. This latest technology has been especially designed to minimize on-state resistance, have a low gate charge with superior switching performance, and rugged avalanche characteristics. This Power MOSFET is well suited for synchronous DC-DC Converters and Power Management in portable and battery operated products. TO-220 12 3 Absolute Maximum Ratings Symbol VDSS ID IDM VGS EAS dv/dt PD TSTG, TJ TL Drain to Source Voltage Continuous Drain Current(@TC = 25°C) Continuous Drain Current(@TC = 100°C) Drain Current Pulsed Gate to Source Voltage Single Pulsed Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation(@TC = 25 °C) Derating Factor above 25 °C Operating Junction Temperature & Storage Temperature Maximum Lead Temperature for soldering purpose, 1/8 from Case for 5 seconds. (Note 2) (Note 3) (Note 1) Parameter Value 60 70 51 280 ±25 800 7.0 158 1.05 - 55 ~ 175 300 Units V A A A V mJ V/ns W W/°C °C °C Thermal Characteristics Symbol RθJC RθCS RθJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Case to Sink Thermal Resistance, Junction-to-Ambient Value Min. - Typ. 0.5 - Max. 0.95 62.5 Units °C/W °C/W °C/W September, 2002. Rev. 0. Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. 1/7 SFP70N06 Electrical Characteristics Symbol Off Characteristics BVDSS Δ BVDSS/ Δ TJ IDSS Drain-Source Breakdown Voltage Breakdown Voltage Temperature coefficient Zero Gate Voltage Drain Current Gate-Source Leakage, Forward Gate-Source Leakage, Reverse VGS = 0V, ID = 250uA ID = 250uA, referenced to 25 °C VDS = 60V, VGS = 0V VDS = 48V, TC = 150 °C VGS = 25V, VDS = 0V VGS = -25V, VDS = 0V VDS = VGS, ID = 250uA VGS =10 V, ID = 35A 60 0.066 1 10 100 -100 V V/°C uA uA nA nA ( TC = 25 °C unless otherwise noted ) Parameter Test Conditions Min Typ Max Units IGSS On Characteristics VGS(th) RDS(ON) Gate Threshold Voltage Static Drain-Source On-state Resistance 2.0 4.0 0.014 V Ω Dynamic Characteristics Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance VGS =0 V, VDS =25V, f = 1MHz 2350 690 160 3050 890 200 pF Dynamic Characteristics Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge(Miller Charge) VDS =48V, VGS =10V, ID =70A ※ see fig. 12. (Note 4, 5) VDD =30V, ID =35A, RG =50Ω ※ see fig. 13. (Note 4, 5) 30 60 125 95 70 18 24 70 130 260 200 90 nC ns - Source-Drain Diode Ratings and Characteristics Symbol IS ISM VSD trr Qrr Parameter Continuous Source Current Pulsed Source Current Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Test Conditions Integral Reverse p-n Junction Diode in the MOSFET IS =70A, VGS =0V IS=70A,VGS=0V,dIF/dt=100A/us Min. - Typ. 62 110 Max. 70 280 1.5 - Unit. A V ns nC ※ NOTES 1. Repeativity rating : pulse width limited by junction temperature 2. L = 250 uH, IAS = 70A, VDD = 25V, RG = 0Ω , Starting TJ = 25°C 3. ISD ≤ 70A, di/dt ≤ 300A/us, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse Width ≤ 300us, Duty Cycle ≤ 2% 5. Essentially independent of operating temperature. 2/7 Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. SFP70N06 Fig 1. On-State Characteristics VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V Top : Fig 2. Transfer Characteristics 10 2 10 2 ID, Drain Current [A] ID, Drain Current [A] 175 C 10 1 o 10 1 25 C -55 C o o ※ Notes : 1. 250µ s Pulse Test 2. TC = 25℃ ※ Notes : 1. VDS = 25V 2. 250µ s Pulse Test 10 -1 10 0 10 0 10 1 10 0 2 4 6 8 10 VDS, Drain-Source Voltage [V] VGS, Gate-Source Voltage [V] Fig 3. On Resistance Variation vs. Drain Current and Gate Voltage 30 Fig 4. On State Current vs. Allowable Case Temperature RDS(ON), Drain-Source On-Resistance [mΩ ] 20 VGS = 10V 15 VGS = 20V IDR, Reverse Drain Current [A] 25 10 2 10 1 10 175℃ 25℃ ※ Notes : 1. VGS = 0V 2. 250µ s Pulse Test 5 ※ Note : TJ = 25℃ 0 0 50 100 150 200 250 300 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ID, Drain Current [A] VSD, Source-Drain voltage [V] Fig 5. Capacitance Characteristics 5500 5000 4500 4000 Ciss=Cgs+Cgd(Cds=shorted) Coss=Cds+Cgd Crss=Cgd Fig 6. Gate Charge Characteristics 12 VGS, Gate-Source Voltage [V] 10 VDS = 30V VDS = 48V Capacitance [pF] 3500 3000 2500 2000 1500 1000 500 0 0 5 ※ Notes : 1. VGS = 0V 2. f=1MHz 8 Ciss 6 4 Coss 2 ※ Note : ID = 70.0 A Crss 10 15 20 25 30 35 0 0 10 20 30 40 50 60 70 VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] 3/7 Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. SFP70N06 Fig 7. Breakdown Voltage Variation vs. Junction Temperature 1.2 3.0 Fig 8. On-Resistance Variation vs. Junction Temperature BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.1 RDS(ON), (Normalized) Drain-Source On-Resistance 2.5 2.0 1.0 1.5 1.0 0.9 ※ Notes : 1. VGS = 0 V 2. ID = 250 µ A 0.5 ※ Notes : 1. VGS = 10 V 2. ID = 35 A 0.8 -100 -50 0 50 100 o 150 200 0.0 -100 -50 0 50 100 o 150 200 TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Fig 9. Maximum Safe Operating Area 10 3 Fig 10. Maximum Drain Current vs. Case Temperature 70 Operation in This Area is Limited by R DS(on) 60 ID, Drain Current [A] 100 µs 10 2 1 ms 10 ms DC ID' Drain Current [A] 50 40 30 20 10 0 25 10 1 ※ Notes : 1. TC = 25 C 2. TJ = 175 C 3. Single Pulse o o 10 0 10 -1 10 0 10 1 10 2 50 75 100 125 o 150 175 VDS, Drain-Source Voltage [V] TC' Case Temperature [ C] Fig 11. Transient Thermal Response Curve 10 0 Zθ JC Thermal Response (t), D = 0 .5 0 .2 10 -1 0 .1 0 .0 5 0 .0 2 0 .0 1 s in g le p u ls e ※ N o te s : 1 . Z θ J C t) = 0 .9 5 ℃ /W M a x . ( 2 . D u ty F a c to r , D = t 1 /t 2 3 . T J M - T C = P D M * Z θ J C t) ( 10 -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a r e W a v e P u ls e D u ra tio n [s e c ] 4/7 Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. SFP70N06 Fig. 12. Gate Charge Test Circuit & Waveforms 50KΩ 12V 200nF 300nF Same Type as DUT VDS VGS 10V Qgs Qg VGS Qgd DUT 1mA Charge Fig 13. Switching Time Test Circuit & Waveforms VDS RL VDD ( 0.5 rated V DS ) VDS 90% 10V V Pulse Generator RG DUT Vin 10% td(on) t on tr td(off) t off tf Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms VDS ID RG L VDD BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD BVDSS IAS ID (t) 10V DUT VDD tp VDS (t) Time 5/7 Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. SFP70N06 Fig. 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ IS L Driver RG Same Type as DUT VDD VGS • dv/dt controlled by RG • IS controlled by pulse period VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current IS ( DUT ) IRM di/dt Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt Vf VDD Body Diode Forward Voltage Drop 6/7 Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. SFP70N06 TO-220 Package Dimension Dim. A B C D E F G H I J K L M N O Min. 9.7 6.3 9.0 12.8 1.2 mm Typ. Max. 10.1 6.7 9.47 13.3 1.4 Min. 0.382 0.248 0.354 0.504 0.047 Inch Typ. Max. 0.398 0.264 0.373 0.524 0.055 1.7 2.5 3.0 1.25 2.4 5.0 2.2 1.14 0.45 0.75 3.6 3.4 1.4 2.7 5.15 2.6 1.40 0.6 0.95 0.118 0.049 0.094 0.197 0.087 0.045 0.018 0.030 0.067 0.098 0.134 0.055 0.106 0.203 0.102 0.055 0.024 0.037 0.142 Ø E B A H I φ F C M G 1 D 2 3 L 1. Gate 2. Drain 3. Source N O J K 7/7 Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
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