SP3222EU / SP3232EU
3.3V, 1000 kbps RS-232 Transceivers
FEATURES
■ Meets true EIA/TIA-232-F Standards
from a +3.0V to +5.5V power supply
■ Minimum 1000kbps Data Rate
■ 1µA Low Power Shutdown with
Receivers active (SP3222EU)
■ Interoperable with RS-232 down to a
+2.7V power source
■ Enhanced ESD Specifications:
+15kV Human Body Model
+15kV IEC61000-4-2 Air Discharge
+8kV IEC61000-4-2 Contact Discharge
■ Ideal for Handheld, Battery Operated
Applications
EN
18 SHDN
1
C1+ 2
17 VCC
V+ 3
16 GND
C1- 4
C2+ 5
15 T1OUT
SP3222EU 14 R1IN
13 R1OUT
C2- 6
V-
7
12 T1IN
T2OUT 8
11 T2IN
R2IN 9
10 R2OUT
nSOIC
Now Available in Lead Free Packaging
DESCRIPTION
The SP3222EU and the SP3232EU are 2 driver, 2 receiver RS-232 transceiver solutions
intended for portable or hand-held applications such as notebook or palmtop computers.
Their data transmission rate of 1000 kbps meets the demands of high speed RS-232 applications. The SP3222EU/SP3232EU series has a high-efficiency, charge-pump power
supply that requires only 0.1µF capacitors in 3.3V operation. This charge pump allows the
SP3222EU/SP3232EU series to deliver true RS-232 performance from a single power supply
ranging from +3.0V to +5.5V. The ESD tolerance of the SP3222EU/SP3232EU devices are
over +/-15kV for both Human Body Model and IEC61000-4-2 Air discharge test methods. The
SP3222EU device has a low-power shutdown mode where the devices' driver outputs and
charge pumps are disabled. During shutdown, the supply current falls to less than 1µA.
SELECTION TABLE
MODEL
Power
Supplies
RS-232 RS-232
Drivers Receivers
External
Components
Shutdown
TTL
3-State
# of
Pins
SP3222EU +3.0V to +5.5V
2
2
4 Capacitors
Yes
Yes
18, 20
SP3232EU +3.0V to +5.5V
2
2
4 Capacitors
No
No
16
SP3222EU/SP3232EU_103_031920
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability and cause permanent damage to the
device.
Power Dissipation per package
VCC.......................................................-0.3V to +6.0V
V+ (NOTE 1).......................................-0.3V to +7.0V
V- (NOTE 1)........................................+0.3V to -7.0V
V+ + |V-| (NOTE 1)...........................................+13V
ICC (DC VCC or GND current).........................+100mA
20-pin SSOP (derate 9.25mW/oC above +70oC)..............750mW
18-pin SOIC (derate 15.7mW/oC above +70oC)..............1260mW
20-pin TSSOP (derate 11.1mW/oC above +70oC).............890mW
16-pin SSOP (derate 9.69mW/oC above +70oC)...............775mW
16-pin PDIP (derate 14.3mW/oC above +70oC)...............1150mW
16-pin Wide SOIC (derate 11.2mW/oC above +70oC)........900mW
16-pin TSSOP (derate 10.5mW/oC above +70oC)..............850mW
16-pin nSOIC (derate 13.57mW/oC above +70oC)...........1086mW
Input Voltages
TxIN, EN, SHDN.........................-0.3V to Vcc + 0.3V
RxIN...................................................................+15V
Output Voltages
TxOUT.............................................................+13.2V
RxOUT, .......................................-0.3V to (VCC +0.3V)
Short-Circuit Duration
TxOUT....................................................Continuous
Storage Temperature......................-65°C to +150°C
NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX, C1 to
C4 = 0.1µF. Typical values apply at Vcc = +3.3V and TAMB = 25°C
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Supply Current
0.3
1.0
mA
no load, VCC = 3.3V,
TAMB = 25oC, TxIN = GND or VCC
Shutdown Supply Current
1.0
10
µA
SHDN = GND, VCC = 3.3V,
TAMB = 25oC, TxIN = Vcc or GND
0.8
V
TxIN, EN, SHDN, Note 2
DC CHARACTERISTICS
LOGIC INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold LOW
GND
Input Logic Threshold HIGH
2.0
Input Logic Threshold HIGH
2.4
V
Vcc = 3.3V, Note 2
Vcc
V
Vcc = 5.0V, Note 2
Input Leakage Current
+0.01
+1.0
µA
TxIN, EN, SHDN,
TAMB = +25oC, VIN = 0V to VCC
Output Leakage Current
+0.05
+10
µA
Receivers disabled, VOUT = 0V to VCC
0.4
V
IOUT = 1.6mA
Output Voltage LOW
Output Voltage HIGH
VCC -0.6
VCC -0.1
V
IOUT = -1.0mA
+5.0
+5.4
V
All driver outputs loaded with 3kΩ to
GND, TAMB = +25oC
DRIVER OUTPUTS
Output Voltage Swing
SP3222EU/SP3232EU_103_031920
2
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX, C1 to
C4 = 0.1µF. Typical values apply at Vcc = +3.3V and TAMB = 25°C
PARAMETER
MIN.
TYP.
MAX.
UNITS
+35
+60
mA
+25
µA
+15
V
CONDITIONS
DRIVER OUTPUTS (continued)
Output Resistance
300
Output Short-Circuit Current
Ω
Output Leakage Current
VCC = V+ = V- = 0V, TOUT=+2V
VOUT = 0V
VCC = 0V or 3.0V to 5.5V,
VOUT = +12V, Drivers disabled
RECEIVER INPUTS
Input Voltage Range
-15
Input Threshold LOW
0.6
1.2
V
Vcc = 3.3V
Input Threshold LOW
0.8
1.5
V
Vcc = 5.0V
Input Threshold HIGH
1.5
2.4
V
Vcc = 3.3V
Input Threshold HIGH
1.8
2.4
V
Vcc = 5.0V
Input Hysteresis
0.3
Input Resistance
3
5
V
7
kΩ
TIMING CHARACTERISTICS
Maximum Data Rate
1000
kbps
RL = 3kΩ, CL = 250pF, one driver
switching
Receiver Propagation Delay, tPHL
0.15
µs
Receiver input to Receiver
output, CL = 150pF
Receiver Propagation Delay, tPLH
0.15
µs
Receiver input to Receiver
output, CL = 150pF
Receiver Output Enable Time
200
ns
Receiver Output Disable Time
200
ns
Driver Skew
100
ns
| tPHL - tPLH |, TAMB = 25°C
Receiver Skew
50
ns
| tPHL - tPLH |
Transition-Region Slew Rate
90
V/µs
Vcc = 3.3V, RL = 3kΩ,
CL =1000pF, TAMB = 25°C,
measurements taken from -3.0V
to +3.0V or +3.0V to -3.0V
NOTE 2: Driver input hysteresis is typically 250mV.
SP3222EU/SP3232EU_103_031920
3
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 1000kbps data rate, all
drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = +25°C.
120
4
T1 at 1Mbps
T2 at 62.5Kbps
2
Slew Rate (V/µs)
Transmitter
Output Voltage (V)
6
0
-2
-4
-6
250
500
1000
Load Capacitance (pF)
40
20
250
500
1000
1500
Load Capacitance (pF)
2000
20
Supply Current (mA)
30
20
15
10
T1 at 1Mbps
T2 at 62.5Kbps
5
0
0
Figure 2. Slew Rate vs Load Capacitance for the
SP3222EU and SP3232EU
35
Supply Current (mA)
60
1500
Figure 1. Transmitter Output Voltage vs Load
Capacitance for the SP3222EU and SP3232EU
0
250
500
1000
Load Capacitance (pF)
T1 at 1Mbps
T2 at 62.5Kbps
10
5
2.7
3
3.5
4
Supply Voltage (V)
4.5
5
Figure 4. Supply Current VS. Supply Voltage for the
SP3222EU and SP3232EU
200
6
4
Skew (nS)
2
T1 at 1Mbps
T2 at 62.5Kbps
0
-2
150
100
T1 at 500Kbps
T2 at 31.2Kbps
All TX loaded 3K // CLoad
50
-4
-6
15
0
1500
Figure 3. Supply Current VS. Load Capacitance
when Transmitting Data for the SP3222EU and
SP3232EU
Transmitter Output
Voltage (V)
80
0
0
T1 at 1Mbps
T2 at 62.5Kbps
All TX loaded 3K // CLoad
100
2.7
3
3.5
4
Supply Voltage (V)
4.5
0
5
Figure 5. Transmitter Output Voltage vs Supply
Voltage for the SP3222EU and SP3232EU
0
250
500
1000
1500
Load Capacitance (pF)
2000
Figure 6. Transmitter Skew VS. Load Capacitance
for the SP3222EU and SP3232EU
SP3222EU/SP3232EU_103_031920
4
PIN FUNCTION
PIN NUMBER
NAME
SP3222EU
FUNCTION
SOIC
SSOP
TSSOP
SP3232EU
EN
Receiver Enable. Apply Logic LOW for normal operation.
Apply logic HIGH to disable the receiver outputs (high-Z state)
1
1
-
C1+
Positive terminal of the voltage doubler charge-pump capacitor
2
2
1
V+
+5.5V output generated by the charge pump
3
3
2
C1-
Negative terminal of the voltage doubler charge-pump capacitor
4
4
3
C2+
Positive terminal of the inverting charge-pump capacitor
5
5
4
C2-
Negative terminal of the inverting charge-pump capacitor
6
6
5
-5.5V output generated by the charge pump
7
7
6
T1OUT
RS-232 driver output.
15
17
14
T2OUT
RS-232 driver output.
8
8
7
R1IN
RS-232 receiver input
14
16
13
R2IN
RS-232 receiver input
9
9
8
R1OUT
TTL/CMOS receiver output
13
15
12
R2OUT
TTL/CMOS receiver output
10
10
9
T1IN
TTL/CMOS driver input
12
13
11
T2IN
TTL/CMOS driver input
11
12
10
GND
Ground
16
18
15
+3.0V to +5.5V supply voltage
17
19
16
Shutdown Control Input. Drive HIGH for normal device operation.
Drive LOW to shutdown the drivers (high-Z output) and the onboard power supply
18
20
-
-
11, 14
-
V-
VCC
SHDN
N.C.
No Connect
Table 1. Device Pin Description
SP3222EU/SP3232EU_103_031920
5
PINOUT
EN
1
C1+ 2
V+ 3
C1-
4
C2+ 5
20 SHDN
EN 1
18 SHDN
19 VCC
C1+ 2
17 VCC
V+ 3
16 GND
18 GND
17 T1OUT
C1- 4
SP3222EU 16 R1IN
C2-
6
15 R1OUT
V-
7
14 N.C.
T2OUT 8
13 T1IN
C2+ 5
SP3222EU 14 R1IN
13 R1OUT
C2- 6
V- 7
12 T1IN
11 T2IN
9
12 T2IN
T2OUT 8
R2OUT 10
11 N.C.
R2IN 9
R2IN
15 T1OUT
10 R2OUT
nSOIC
SSOP/TSSOP
Figure 7. Pinout Configurations for the SP3222EU
C1+ 1
16 VCC
V+ 2
15 GND
C1- 3
C2+ 4
14 T1OUT
SP3232EU 13 R1IN
C2- 5
12 R1OUT
V- 6
11 T1IN
T2OUT 7
10 T2IN
R2IN 8
9 R2OUT
Figure 8. Pinout Configuration for the SP3232EU
SP3222EU/SP3232EU_103_031920
6
TYPICAL OPERATING CIRCUITS
VCC
C5
C1
C2
LOGIC
INPUTS
+
+
+
0.1µF
2 C1+
0.1µ F
19
VCC
6 C2-
V+
SP3222EU
SSOP
TSSOP
3
*C3
+
0.1µF
+
C1
V- 7
C4
13 T1IN
T1OUT 17
12 T2IN
T2OUT 8
+
0.1µF
+
C2
RS-232
OUTPUTS
5kΩ
10 R2OUT
R2IN 9
17
VCC
0.1µF
2 C1+
0.1µF
0.1µF
LOGIC
INPUTS
V+
6 C2-
SP3222EU
WSOIC
C4
11 T2IN
T2OUT 8
0.1µF
+
0.1µF
RS-232
OUTPUTS
R1IN 14
5kΩ
LOGIC
OUTPUTS
+
V- 7
T1OUT 15
10 R2OUT
R2IN 9
5kΩ
1 EN
*C3
12 T1IN
13 R1OUT
RS-232
INPUTS
3
4 C15 C2+
R1IN 16
15 R1OUT
LOGIC
OUTPUTS
+
C5
4 C15 C2+
0.1µF
VCC
RS-232
INPUTS
5kΩ
SHDN
GND
1 EN
20
SHDN
GND
*can be returned to
either VCC or GND
18
16
18
*can be returned to
either VCC or GND
WSOIC version is obsolete
Figure 9. SP3222EU Typical Operating Circuits
VCC
C5
C1
C2
LOGIC
INPUTS
+
+
+
0.1µF
1 C1+
0.1µF
V+
SP3232EU
*C3
V-
+
0.1µF
6
C4
5 C211 T1IN
T1OUT
14
10 T2IN
T2OUT
7
+
0.1µF
RS-232
OUTPUTS
R1IN 13
12 R1OUT
LOGIC
OUTPUTS
2
3 C14 C2+
0.1µF
16
VCC
5kΩ
R2IN
9 R2OUT
8
RS-232
INPUTS
5kΩ
GND
15
*can be returned to
either VCC or GND
Figure 10. SP3232EU Typical Operating Circuit
SP3222EU/SP3232EU_103_031920
7
DESCRIPTION
The SP3222EU/SP3232EU transceivers
meet the EIA/TIA-232 and ITU-T V.28/V.24
communication protocols and can be implemented in battery-powered, portable, or
hand-held applications such as notebook
or palmtop computers. The SP3222EU/
SP3232EU devices feature Exar's proprietary on-board charge pump circuitry that
generates ±5.5V for RS-232 voltage levels
from a single +3.0V to +5.5V power supply.
This series is ideal for +3.3V-only systems,
mixed +3.3V to +5.5V systems, or +5.0Vonly systems that require true RS-232
performance. The SP3222EU/SP3232EU
devices can operate at a minimum data rate
of 1000kbps.
The drivers have a minimum data rate of
1000kbps fully loaded with 3kΩ in parallel
with 250pF, ensuring compatability with PCto-PC communication software.
Figure 11 shows a loopback test circuit
used to test the RS-232 Drivers. Figure
12 shows the test results of the loopback
circuit with all drivers active at 250kbps
with RS-232 loads in parallel with a
1000pF capacitor. Figure 13 shows the
test results where one driver was active
at 1000kbps and all drivers loaded with an
RS-232 receiver in parallel with 250pF
capacitors.
The SP3222EU driver's output stages are
turned off (tri-state) when the device is in
shutdown mode. When the power is off, the
SP3222EU device permits the outputs to be
driven up to +/-12V. The driver's inputs do
not have pull-up resistors. Designers should
connect unused inputs to Vcc or GND.
The SP3222EU and SP3232EU are 2driver/2- receiver devices ideal for portable
or hand-held applications. The SP3222EU
features a 1µA shutdown mode that reduces
power consumption and extends battery life
in portable systems. Its receivers remain
active in shutdown mode, allowing external
devices such as modems to be monitored
using only 1µA supply current.
In the shutdown mode, the supply current
falls to less than 1µA, where SHDN = LOW.
When the SP3222EU device is shut down,
the device's driver outputs are disabled (tristated) and the charge pumps are turned off
with V+ pulled down to Vcc and V- pulled to
GND. The time required to exit shutdown is
typically 100µs. Connect SHDN to Vcc if the
shutdown mode is not used.
THEORY OF OPERATION
The SP3222EU/SP3232EU series is made
up of three basic circuit blocks:
1. Drivers
2. Receivers
3. The Exar proprietary charge pump
Receivers
The Receivers convert EIA/TIA-232 levels
to TTL or CMOS logic output levels. The
SP3222EU receivers have an inverting
tri-state output. These receiver outputs
(RxOUT) are tri-stated when the enable
control EN = HIGH. In the shutdown mode,
the receivers can be active or inactive. EN
has no effect on TxOUT. The truth table logic
of the SP3222EU driver and receiver outputs
can be found in Table 2.
Drivers
The drivers are inverting level transmitters
that convert TTL or CMOS logic levels to
+5.0V EIA/TIA-232 levels with an inverted
sense relative to the input logic levels.
Typically, the RS-232 output voltage swing
is +5.4V with no load and +5V minimum fully
loaded. The driver outputs are protected
against infinite short-circuits to ground without degradation in reliability. Driver outputs
will meet EIA/TIA-562 levels of +/-3.7V with
supply voltages as low as 2.7V.
SP3222EU/SP3232EU_103_031920
8
DESCRIPTION
Since receiver input is usually from a transmission line where long cable lengths and
system interference can degrade the signal,
the inputs have a typical hysteresis margin
of 300mV. This ensures that the receiver
is virtually immune to noisy transmission
lines. Should an input be left unconnected,
an internal 5kΩ pulldown resistor to ground
will commit the output of the receiver to a
HIGH state.
VCC
C5
C1
+
+
0.1µF
0.1µF
VCC
C1+
C3
C1-
C2
+
V+
C2+
0.1µF
SP3222EU
SP3232EU
LOGIC
OUTPUTS
0.1µF
VC4
C2LOGIC
INPUTS
+
+
0.1µF
TxOUT
TxIN
RxIN
RxOUT
5kΩ
EN*
*SHDN
VCC
GND
250pF or 1000pF
* SP3222EU only
SHDN
EN
TxOUT
RxOUT
0
0
Tri-state
Active
0
1
Tri-state
Tri-state
1
0
Active
Active
1
1
Active
Tri-state
Table 2. SP3222EU Truth Table Logic for Shutdown
and Enable Control
Figure 11. SP3222EU/SP3232EU Driver Loopback
Test Circuit
Charge Pump
The charge pump is an Exar-patended
design (U.S. 5,306,954) and uses a unique
approach compared to older less-efficient
designs. The charge pump still requires four
external capacitors, but uses a four-phase
voltage shifting technique to attain symmetrical 5.5V power supplies. The internal
power supply consists of a regulated dual
charge pump that provides output voltages
of +/-5.5V regardless of the input voltage
(Vcc) over the +3.0V to +5.5V range.
In most circumstances, decoupling the
power supply can be achieved adequately
using a 0.1µF bypass capacitor at C5 (refer
to figures 9 and 10). In applications that are
sensitive to power-supply noise, decouple
Vcc to ground with a capacitor of the same
value as charge-pump capacitor C1. Physically connect bypass capcitors as close to
the IC as possible.
Figure 12. Loopback Test results at 250kbps
Figure 13. Loopback Test results at 1000kbps
SP3222EU/SP3232EU_103_031920
9
DESCRIPTION
The charge pump operates in a discontinuous mode using an internal oscillator. If the
output voltages are less than a magnitude
of 5.5V, the charge pump is enabled. If the
output voltages exceed a magnitude of 5.5V,
the charge pump is disabled. This oscillator
controls the four phases of the voltage shifting. A description of each phase follows.
to VCC and the negative side is connected to GND, allowing the charge
pump cycle to begin again. The charge
pump cycle will continue as long as the
operational conditions for the internal
oscillator are present.
Since both V+ and V– are separately generated from VCC, in a no–load condition V+
and V– will be symmetrical. Older charge
pump approaches that generate V– from
V+ will show a decrease in the magnitude
of V– compared to V+ due to the inherent
inefficiencies in the design.
Phase 1
— VSS charge storage — During this phase
of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC.
Cl+ is then switched to GND and the charge
in C1– is transferred to C2–. Since C2+ is connected to VCC, the voltage potential across
capacitor C2 is now 2 times VCC.
The clock rate for the charge pump typically
operates at greater than 250kHz. The external capacitors can be as low as 0.1µF with
a 16V breakdown voltage rating.
Phase 2
— VSS transfer — Phase two of the clock
connects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal of
C2 to GND. This transfers a negative generated voltage to C3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1
is switched to VCC and the negative side is
connected to GND.
Phase 3
— VDD charge storage — The third phase of
the clock is identical to the first phase — the
charge transferred in C1 produces –VCC in
the negative terminal of C1, which is applied
to the negative side of capacitor C2. Since
C2+ is at VCC, the voltage potential across C2
is 2 times VCC.
Phase 4
— VDD transfer — The fourth phase of
the clock connects the negative terminal
of C2 to GND, and transfers this positive
generated voltage across C2 to C4, the
VDD storage capacitor. This voltage is
regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C4, the
positive side of capacitor C1 is switched
SP3222EU/SP3232EU_103_031920
10
DESCRIPTION
VCC = +5V
C4
+5V
C1
+
+
C2
–
–5V
–
+
–
VDD Storage Capacitor
–
+
VSS Storage Capacitor
C3
–5V
Figure 14. Charge Pump — Phase 1
VCC = +5V
C4
+
C1
C2
–
+
–
+
–
–
+
VDD Storage Capacitor
VSS Storage Capacitor
C3
-5.5V
Figure 15. Charge Pump — Phase 2
[
T
]
+6V
a) C2+
T
GND 1
GND 2
b) C2-6V
T
Ch1 2.00V
Ch2
2.00V M 1.00µs Ch1 5.48V
Figure 16. Charge Pump Waveforms
VCC = +5V
C4
+5V
C1
+
–
C2
–5V
+
+
–
–
–
VDD Storage Capacitor
+
VSS Storage Capacitor
C3
–5V
Figure 17. Charge Pump — Phase 3
VCC = +5V
+5.5V
C1
+
–
C2
C4
+
+
–
–
–
+
VDD Storage Capacitor
VSS Storage Capacitor
C3
Figure 18. Charge Pump — Phase 4
SP3222EU/SP3232EU_103_031920
11
DESCRIPTION
ESD TOLERANCE
The SP3222E/SP3232E series incorporates ruggedized ESD cells on all driver
output and receiver input pins. The ESD
structure is improved over our previous
family for more rugged applications and
environments sensitive to electro-static
discharges and associated transients. The
improved ESD tolerance is at least +15kV
without damage nor latch-up.
61000-4-2 is that the system is required to
withstand an amount of static electricity when
ESD is applied to points and surfaces of the
equipment that are accessible to personnel
during normal usage. The transceiver IC
receives most of the ESD current when the
ESD source is applied to the connector pins.
The test circuit for IEC 61000-4-2 is shown
on Figure 20. There are two methods within
IEC 61000-4-2, the Air Discharge method
and the Contact Discharge method.
There are different methods of ESD testing
applied:
With the Air Discharge Method, an ESD
voltage is applied to the equipment under
test (EUT) through air. This simulates an
electrically charged person ready to connect
a cable onto the rear of the system only to
find an unpleasant zap just before the person
touches the back panel. The high energy
potential on the person discharges through
an arcing path to the rear panel of the system
before he or she even touches the system.
This energy, whether discharged directly or
through air, is predominantly a function of the
discharge current rather than the discharge
voltage. Variables with an air discharge such
as approach speed of the object carrying the
ESD potential to the system and humidity
will tend to change the discharge current.
For example, the rise time of the discharge
current varies with the approach speed.
a) MIL-STD-883, Method 3015.7
b) IEC 61000-4-2 Air-Discharge
c) IEC 61000-4-2 Direct Contact
The Human Body Model has been the
generally accepted ESD testing method
for semi-conductors. This method is also
specified in MIL-STD-883, Method 3015.7
for ESD testing. The premise of this ESD test
is to simulate the human body’s potential to
store electro-static energy and discharge it
to an integrated circuit. The simulation is
performed by using a test model as shown
in Figure 19. This method will test the IC’s
capability to withstand an ESD transient
during normal handling such as in manufacturing areas where the ICs tend to be
handled frequently.
The Contact Discharge Method applies the
ESD current directly to the EUT. This method
was devised to reduce the unpredictability
of the ESD arc. The discharge current rise
time is constant since the energy is directly
transferred without the air-gap arc. In situations such as hand held systems, the ESD
charge can be directly discharged to the
The IEC-61000-4-2, formerly IEC801-2, is
generally used for testing ESD on equipment
and systems. For system manufacturers,
they must guarantee a certain amount of
ESD protection since the system itself is
exposed to the outside environment and
human presence. The premise with IEC
RS
RC
SW1
DC Power
Source
SW2
CS
Figure 19. ESD Test Circuit for Human Body Model
Device
Under
Test
SP3222EU/SP3232EU_103_031920
12
DESCRIPTION
Contact-Discharge Model
RS
RC
RV
SW1
SW2
Device
Under
Test
CS
DC Power
Source
R S and RV add up to 330Ω for IEC61000-4-2.
Figure 20. ESD Test Circuit for IEC61000-4-2
equipment from a person already holding
the equipment. The current is transferred
on to the keypad or the serial port of the
equipment directly and then travels through
the PCB and finally to the IC.
The higher CS value and lower RS value in
the IEC61000-4-2 model are more stringent
than the Human Body Model. The larger
storage capacitor injects a higher voltage
to the test point when SW2 is switched on.
The lower current limiting resistor increases
the current charge onto the test point.
I→
The circuit models in Figures 19 and 20 represent the typical ESD testing circuit used for
all three methods. The CS is initially charged
with the DC power supply when the first
switch (SW1) is on. Now that the capacitor
is charged, the second switch (SW2) is on
while SW1 switches off. The voltage stored
in the capacitor is then applied through RS,
the current limiting resistor, onto the device
under test (DUT). In ESD tests, the SW2
switch is pulsed so that the device under
test receives a duration of voltage.
30A
15A
For the Human Body Model, the current
limiting resistor (RS) and the source capacitor
(CS) are 1.5kΩ an 100pF, respectively. For
IEC-61000-4-2, the current limiting resistor
(RS) and the source capacitor (CS) are 330Ω
an 150pF, respectively.
DEVICE PIN
TESTED
Driver Outputs
Receiver Inputs
0A
t = 0ns
t = 30ns
Figure 21. ESD Test Waveform for IEC61000-4-2
HUMAN BODY
MODEL
Air Discharge
+15kV
+15kV
t→
+15kV
+15kV
IEC61000-4-2
Direct Contact
Level
+8kV
+8kV
4
4
Table 3. Transceiver ESD Tolerance Levels
SP3222EU/SP3232EU_103_031920
13
PACKAGE: 16 PIN SSOP
SP3222EU/SP3232EU_103_031920
14
PACKAGE: 18 PIN WSOIC
WSOIC18 version is obsolete
SP3222EU/SP3232EU_103_031920
15
PACKAGE: 16 PIN nSOIC
SP3222EU/SP3232EU_103_031920
16
PACKAGE: 16 PIN TSSOP
SP3222EU/SP3232EU_103_031920
17
PACKAGE: 20 PIN TSSOP
SP3222EU/SP3232EU_103_031920
18
ORDERING INFORMATION(1)
Part Number
Temp. Range
Package
Packaging
Method
LeadFree(2)
SP3222EUCY-L/TR
0°C to +70°C
20 Pin TSSOP
Tape and Reel
Yes
SP3222EUEY-L/TR
-40°C to +85°C
20 Pin TSSOP
Tape and Reel
Yes
NOTES:
1. Refer to www.maxlinear.com/SP3222EU for most up-to-date Ordering Information.
2. Visit www.maxlinear.com for additional information on Environmental Rating.
3. 18-pin WSOIC versions are obsolete.
Part Number
Temp. Range
Package
Packaging
Method
LeadFree(2)
SP3232EUCN-L
0°C to +70°C
16 Pin NSOIC
Tube
Yes
SP3232EUCN-L/TR
0°C to +70°C
16 Pin NSOIC
Tape and Reel
Yes
SP3232EUCY-L/TR
0°C to +70°C
16 Pin TSSOP
Tape and Reel
Yes
SP3232EUEA-L/TR
-40°C to +85°C
16 Pin SSOP
Tape and Reel
Yes
SP3232EUEY-L/TR
-40°C to +85°C
16 Pin TSSOP
Tape and Reel
Yes
NOTES:
1. Refer to www.maxlinear.com/SP3232EU for most up-to-date Ordering Information.
2. Visit www.maxlinear.com for additional information on Environmental Rating.
SP3222EU/SP3232EU_103_031920
19
REVISION HISTORY
DATE
REVISION DESCRIPTION
02/31/06
--
Legacy Sipex Datasheet
12/08/10
1.0.0
Convert to Exar Format and update ordering information.
06/17/11
1.0.1
Remove EOL devices per PDN 110510-05
03/14/13
1.0.2
Correct type error to RX input voltage range and driver transition region slew rate test condition.
03/19/20
1.0.3
Update to MaxLinear logo. Update ordering information.
MaxLinear, Inc.
5966 La Place Court, Suite 100
Carlsbad, CA 92008
760.692.0711 p.
760.444.8598 f.
www.maxlinear.com
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