SL74HC595

SL74HC595 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs High-Performance Silicon-Gate CMOS The SL74HC595 is identical in pinout to the LS/ALS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC595 consists of an 8-bit shift register and an 8-bit Dtype latch with three-state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8 -bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC595N Plastic SL74HC595D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND SLS System Logic Semiconductor SL74HC595 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD T stg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±35 ±75 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN a nd VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC595 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 °C to -55°C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 ±0.5 ≤85 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 ±5.0 ≤125 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 ±10 µA µA V V V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage, QAQH VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage, QAQH VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA VOH Minimum High-Level Output Voltage, SQH VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA VOL Maximum Low-Level Output Voltage, SQH VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA IIN IOZ Maximum Input Leakage Current Maximum Three-State Leakage Current, QAQH Maximum Quiescent Supply Current (per Package) VIN=VCC or GND Output in High-Impedance State VIN= VIL or VIH VIN=VCC or GND VIN=VCC or GND IOUT=0µA ICC 6.0 4.0 40 160 µA SLS System Logic Semiconductor SL74HC595 SLS System Logic Semiconductor SL74HC595 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol fmax Parameter Minimum Clock Frequency (50% Duty Cycle) (Figures 1and 7) Maximum Propagation Delay, Shift Clock to SQH (Figures 1and 7) Maximum Propagation Delay , Reset to SQH (Figures 2 and 7) Maximum Propagation Delay , Latch Clock to QAQH (Figures 3 and 7) Maximum Propagation Delay , Output Enable to QA-QH (Figures 4 and 8) Maximum Propagation Delay , Output Enable to QA-QH (Figures 4 and 8) Maximum Output Transition Time, QA-QH (Figures 3 and 7) Maximum Output Transition Time, SQH (Figures 1 and 7) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State), QA-QH Power Dissipation Capacitance (Per Package) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 6.0 30 35 140 28 24 145 29 25 140 28 24 150 30 26 135 27 23 60 12 10 75 15 13 10 15 ≤85 °C 4.8 24 28 175 35 30 180 36 31 175 35 30 190 38 33 170 34 29 75 15 13 95 19 16 10 15 ≤125 °C 4.0 20 24 210 42 36 220 44 38 210 42 36 225 45 38 205 41 35 90 18 15 110 22 19 10 15 Unit MHz tPLH, t PHL ns tPHL ns tPLH, t PHL ns tPLZ, t PHZ ns tPZL, t PZH ns tTLH, t THL ns tTLH, t THL ns CIN COUT pF pF Typical @25°C,VCC=5.0 V 300 pF SLS System Logic Semiconductor SL74HC595 TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol Tsu Parameter Minimum Setup Time,Serial Data Input A to Shift Clock (Figure 5) Minimum Setup Time, Shift Clock to Latch Clock (Figure 6) Minimum Hold Time, Shift Clock to Serial Data Input A (Figure 5) Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 2) Minimum Pulse Width, Reset (Figure 2) Minimum Pulse Width, Shift Clock (Figure 1) Minimum Pulse Width, Latch Clock (Figure 6) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 50 10 9 75 15 13 5 5 5 50 10 9 60 12 10 50 10 9 50 10 9 1000 500 400 ≤85°C 65 13 11 95 19 16 5 5 5 65 13 11 75 15 13 65 13 11 65 13 11 1000 500 400 ≤125°C 75 15 13 110 22 19 5 5 5 75 15 13 90 18 15 75 15 13 75 15 13 1000 500 400 Unit ns Tsu ns th ns Trec ns Tw ns Tw ns Tw ns tr, t f ns SLS System Logic Semiconductor SL74HC595 FUNCTION TABLE Inputs Operation Reset Serial Shift Latch Output Input Clock Clock Enable A L X X L,H, L Shift Register Contents L Resulting Function Latch Register Contents U Serial Output SQH L Parallel Outputs QA-QH U Reset shift register Shift data into shift register Shift register remains unchanged Transfer shift register contents to latch register Latch register remains unchanged Enable parallel outputs Force outputs into high-impedance state H H H D X X L,H, L,H, L,H, L,H, L L L D SRA SRN SRN+1 U U U U SRN LRN SRG SRH U U U U SRN X X X X X X X X X L,H, X X L L H * * * U ** ** * * * U Enabled Z SR = shift register contents LR = latch register contents D = data (L,H) logic level U = remains unchanged X = don’t care Z = high impedance * = depends on Reset and Shift Clock inputs ** = depends on Latch Clock input PIN DESCRIPTIONS INPUTS: A - Serial Data Input. The data on this pin is shifted into the 8-bit serial shift register. CONTROL INPUTS: Shift Clock - Shift Register Clock Input. A low-tohigh transition on this input causes the data at the Serial Input pin to be shifted into the 8 -bit shift register. Reset - Active-low, Asynchronous, Shift Register Reset Input. A low on this pin resets the shift register portion of this device only. The 8-bit latch is not affected. Latch Clock - Storage Latch Clock Input. A low-tohigh transition on this input latches the shift register data. Output Enable - Active-Low Output Enable. A low on this input allows the data from the latches to bepresented at the outputs. A high on this input forces the outputs (QA-QH) into the high-impedance state. The serial output is not affected by this control unit. OUTPUTS: QA-QH - Noninverted, 3-state, latch outputs. S QH - Voninverted, Serial Data Output. This is the output of the eighth stage of the 8-bit shift register. This output does not have three-state capability. SLS System Logic Semiconductor SL74HC595 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Switching Waveforms Figure 7. Test Circuit Figure 8. Test Circuit SLS System Logic Semiconductor SL74HC595 TIMING DIAGRAM SLS System Logic Semiconductor SL74HC595 EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor