74VHCT16373ATTR

74VHCT16373A 16-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS: VIH =2V (MIN.) VIL = 0.8 (MAX.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.) ) (s DESCRIPTION The 74VHCT16373A is an advanced high-speed CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 16 bit D-TYPE latches are byte controlled by two latch enable inputs (nLE) and two output enable inputs(nOE). While the nLE input is held at a high level, the nQ outputs will follow the data (D) inputs. When the nLE is taken LOW, the nQ outputs will be latched at the logic level of D data inputs. When the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level); when nOE is at high level ,the outputs will be in a high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ) s ( ct TSSOP PACKAGE t e l o TSSOP u d o r P e ORDER CODES TUBE T&R 74VHCT16373ATTR PIN CONNECTION s b O t c u d o r P e t e l o s b O February 2003 1/10 74VHCT16373A INPUT EQUIVALENT CIRCUIT PIN No SYMBOL 1 1OE ) (s t c u d o r P e TRUTH TABLE s b O INPUTS OUTPUT OE LE D Q H L L L X L H H X X L H Z NO CHANGE * L H X : Don‘t Care Z : High Impedance * : Q outputs are latched at the time when the LE input is taken low logic level. 2/10 u d o NAME AND FUNCTION 3 State Output Enable Input (Active LOW) 2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs 19, 20, 22, 23 3 State Output Enable 24 2OE Input (Active LOW) 25 2LE Latch Enable Input 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1LE Latch Enable Input 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 VCC Positive Supply Voltage t e l o ) s ( ct IEC LOGIC SYMBOLS PIN DESCRIPTION r P e s b O t e l o 74VHCT16373A LOGIC DIAGRAM ) s ( ct u d o r P e This logic diagram has not to be used to estimate propagation delays t e l o ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current ) (s s b O t c u d o r ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL P e Lead Temperature (10 sec) t e l o Value Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to VCC + 0.5 - 20 V mA ± 20 mA ± 25 mA ± 75 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied s b O RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage Top Operating Temperature dt/dv Input Rise and Fall Time (note 1) (Vcc= 5.0±0.5V) Value Unit 4.5 to 5.5 V 0 to 5.5 V 0 to VCC V -55 to 125 °C 0 to 20 ns/V 1) VIN from 0.8V to 2.0V 3/10 74VHCT16373A DC SPECIFICATIONS Test Condition Symbol VIH Parameter VIL VOH VOL 4.5 to 5.5 4.5 to 5.5 Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current IOZ II ICC TA = 25°C VCC (V) High Level Input Voltage Low Level Input Voltage High Level Output Voltage Value Min. Typ. 2 tPLH tPHL tPLH tPHL tPZL tPZH e t e l so tPLZ tPHZ b O tw ts th tOSLH tOSHL Propagation Delay Time LE to Qn Propagation Delay Time Dn to Qn Output Enable Time 4.5 IO=-50 µA 4.4 4.5 IO=-8 mA 3.94 4.5 IO=50 µA 4.5 4.5 0.0 4.4 3.8 3.7 0.36 0.44 5.5 VI = VIH or VIL VO = VCC or GND ±0.25 ± 2.5 0 to 5.5 VI = 5.5V or GND ± 0.1 5.5 VI = VCC or GND o s b CL (pF) O ) s ( t c ) s ( ct 0.55 µA ±1 ±1 µA 40 40 µA Value Unit -40 to 85°C -55 to 125°C Max. Min. Max. Min. Max. du 15 5.0 8.5 1 9.5 1 9.5 50 6.0 9.5 1 10.5 1 10.5 5.0(*) 15 5.5 8.5 1 9.5 1 9.5 5.0(*) 50 6.2 9.5 1 10.5 1 10.5 5.0(*) 15 5.2 9.5 1 10.5 1 10.5 5.0(*) 50 6.5 10.5 1 11.5 1 11.5 5.0(*) 15 6 10.2 1 11.0 1 11.0 (**) 50 7 11.2 1 12.0 1 12.0 5.0(*) 5.0 V ± 2.5 Typ. 5.0(*) V V 0.1 u d o r P e TA = 25°C Min. 0.8 4.4 IO=8 mA 4 Max. V 0.8 let Unit 2 0.1 ns ns ns ns Pulse Width (LE) HIGH Setup Time Dn to LE HIGH or LOW Hold Time Dn to LE HIGH or LOW 5.0(*) 5 5 5 ns 5.0(*) 4 4 4 ns 5.0(*) 1 1 1 ns Output to Output Skew time (note 1) 5.0(*) 50 (*) Voltage range is 5.0V ± 0.5V (Note 1 : Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn| 4/10 Min. Max. 0.1 VCC (V) o r P Output Disable Time Min. 0.8 Test Condition Parameter -55 to 125°C 2 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns) Symbol Max. -40 to 85°C 1.. 1.5 1.5 ns 74VHCT16373A CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter CIN Input Capacitance COUT Output Capacitance Power Dissipation Capacitance (note 1) CPD TA = 25°C VCC (V) 5.0 Value Min. fIN = 10MHz Typ. Max. 4 10 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF 6 pF 21 pF ) s ( ct 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per Latch) DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP VOLV VIHD VILD Parameter Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) Min. 5.0 5.0 -0.9 CL = 50 pF t c u ) (s let Typ. Max. 0.6 0.9 b O so u d o r P e TA = 25°C VCC (V) 5.0 Value -0.6 3.5 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. V V 1.5 V 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V ILD), 0V to threshold (VIHD), f=1MHz. d o r P e t e l o s b O 5/10 74VHCT16373A TEST CIRCUIT ) s ( ct u d o r P e TEST let tPLH, tPHL tPZL, tPLZ so tPZH, tPHZ CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) ) (s b O SWITCH Open VCC GND WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) t c u d o r P e t e l o s b O 6/10 74VHCT16373A WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o ) (s s b O WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) t c u d o r P e t e l o s b O 7/10 74VHCT16373A TSSOP48 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 0.047 0.15 A2 0.002 0.006 0.9 0.035 b 0.17 0.27 0.0067 c 0.09 0.20 0.0035 D 12.4 12.6 0.488 E E1 0˚ L 0.50 0.236 bs let o s b O ) 8˚ ro 0.0079 0.496 s ( t c 0.75 0.244 0.0197 BSC 0˚ 8˚ 0.020 0.030 u d o r P e A t e l o 6.2 0.5 BSC K du 0.318 BSC 6.0 e 0.011 P e 8.1 BSC ) s ( ct A2 A1 b K e L E c D O E1 PIN 1 IDENTIFICATION 1 7065588C 8/10 74VHCT16373A Tape & Reel TSSOP48 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 330 MAX. 12.992 C 12.8 13.2 D 20.2 0.795 N 60 2.362 T 0.504 0.519 ) s ( ct 30.4 1.197 Ao 8.7 8.9 0.343 Bo 13.1 13.3 0.516 Ko 1.5 1.7 0.059 Po 3.9 4.1 P 11.9 12.1 ) (s let 0.153 so b O P e 0.468 ro du 0.350 0.524 0.067 0.161 0.476 t c u d o r P e t e l o s b O 9/10 74VHCT16373A ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. 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