EMIF02-USB02F2

EMIF02-USB02F2 2-line IPAD™, EMI filter with ESD protection Features ■ 2-line low-pass filter + ESD protection ■ High efficiency in EMI filtering ■ Lead-free package ■ Very low PCB space occupation < 3.2 mm2 ■ Very thin package: 0.65 mm ■ High efficiency in ESD suppression ■ High reliability offered by monolithic integration ■ High reduction of parasitic elements through integration and wafer level packaging ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c Application u O d o ) r s ( t Description P c e t u e l d o o r s P b O e t e l o s b O Flip Chip (10 bumps) Figure 1. Pin layout (bump side) 4 3 2 1 VCC Complies with the following standards: ■ ■ I2 O2 I3 Figure 2. EMI filtering and ESD protection for USB port. C D GND O1 MIL STD 883E - Method 3015-6 Class 3 A B I5 I4 IEC 61000-4-2 – 15 kV (air discharge) – 8 kV (contact discharge) I6 I1 E Basic cell configuration I6 I5 I4 VCC R3 1.3kΩ D1 R2 33Ω R4 10kΩ I3 The EMIF02-USB02F2 is a highly integrated array designed to suppress EMI / RFI noise for a USB port. The EMIF02-USB02F2 Flip Chip packaging means the package size is equal to the die size. O2 25pF 25pF GND GND 25pF 25pF R1 33Ω Additionally, this filter includes ESD protection circuitry which prevents damage to the application when subjected to ESD surges up to 15 kV. April 2008 I2 I1 Rev 2 O1 1/7 www.st.com 7 Characteristics 1 EMIF02-USB02F2 Characteristics Table 1. Absolute ratings (Tamb = 25 °C) Symbol VPP Tj Parameter and test conditions Value Unit ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge 15 8 kV Junction temperature 125 °C Top Operating temperature range - 40 to + 85 °C Tstg Storage temperature range - 55 to + 150 °C ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameter VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Series resistance between input and output Cline Input capacitance per line Symbol 2/7 Test conditions VBR IR = 1 mA IRM VRM = 3V Cline @ 0V I IPP IR IRM VCL VBR VRM IRM IR VRM VBR VCL V IPP Min. Typ. Max. 6 Unit V 0.1 0.5 µA 50 pF R1,R2 Tolerance ± 5% 33 Ω R3 Tolerance ± 5% 1.3 kΩ R4 Tolerance ± 5% 10 kΩ VF @ 1 mA (D1 diode) 1 V EMIF02-USB02F2 Figure 3. Characteristics Attenuation measurement 0.00 Figure 4. Analog crosstalk measurement (I1- O2) 0.00 dB dB - 5.00 - 10.00 - 10.00 - 20.00 - 15.00 - 30.00 - 20.00 - 40.00 - 25.00 - 50.00 - 30.00 - 35.00 - 60.00 - 40.00 - 70.00 - 45.00 - 80.00 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O - 50.00 100.0k Figure 5. 1.0M 10.0M f/Hz 100.0M 1.0G ESD response to IEC 61000-4-2 (+15kV contact discharge) - 90.00 100.0k 1.0M Figure 6. 10.0M f/Hz 100.0M 1.0G Line capacitance versus reverse applied voltage C(pF) 40 35 30 25 20 15 VR(V) 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 3/7 Application information 2 EMIF02-USB02F2 Application information Figure 7. Aplac model of D+ & D- cells C1 0.8pF + + Csub A3 650 650 + + Csub Csub + 0.8pF D2 rsub_1k3 rsub_1k3 bulk C1 or E1 16.5 50pH C3 or E3 16.5 Cbump + 0.8pF + Csub + Csub + Csub I/O + 0.8pF + Rbump bulk 50m ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t 3 Ordering information scheme c e t u e l d o o r s P b O e t e l o s b O MODEL = D02_usb MODEL = D02_usb rsub_33R rsub_33R 100m D2 bulk Lhole MODEL = D02_usb MODEL = D02_5p MODEL = D02_usb MODEL = D02_5p Rsub_D 100m Rsub_D D2 D2 bulk Figure 8. Aplac model parameters Cz 17pF opt Ls 0.4nH Rs 0.1 Rsub_D 10 Csub 0.3pF Rsub_33R 16 Rsub_1k3 18 lhole 170pH opt Cbump 1.2pF opt Rbump 350 Figure 9. D02_usb diodes model + BV = 7 + IBV = 1m + CJO = Cz + M = 0.3333 + RS = 2 + VJ = 0.6 + TT = 100n D02_5p diodes model + BV = 100 + IBV = 1m + CJO = 5p + M = 0.3333 + RS = 2 + VJ = 0.6 + TT = 100n Ordering information scheme EMIF EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip-Chip x 2: Lead free, pitch = 500 µm, bump = 315 µm 4/7 yy - xxx zz Fx EMIF02-USB02F2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 10. Flip Chip package dimensions 700µm ± 50 650µm ± 65 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e x x z t u e l d y ww o o r s P b O e t e l o s b O 1.97mm ± 50µm 315µm ± 50 495µm ± 50 495µm ± 50 1.62mm ± 50µm Figure 11. Footprint recommendations Copper pad Diameter: 250 µm recommended, 300 µm max. 285 µm 285 µm Figure 12. Marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) E Solder stencil opening: 330 µm recommended Solder mask opening recommendation: 340 µm min. for 300 µm copper pad diameter 5/7 Ordering Information EMIF02-USB02F2 Figure 13. Flip Chip tape and reel specification Dot identifying Pin A1 location 1.75 ± 0.1 Ø 1.5 ± 0.1 4 ± 0.1 3.5 ± 0.1 2.07 ST E xxz yww 1.72 xxz yww ST E ST E xxz yww 8 ± 0.3 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s 5 Ordering Information P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e history 6 Revision t u e l d o o r s P b O e t e l o s b O 0.73 ± 0.05 4 ± 0.1 User direction of unreeling All dimensions in mm Note: More information is available in the application notes: AN1235: “Flip Chip: Package description and recommendations for use” AN1751: "EMI Filters: Recommendations and measurements" Table 3. Order code Marking Package Weight Base qty Delivery mode EMIF02-USB02F2 FG Flip Chip 4.25 mg 5000 Tape and reel 7” Table 4. 6/7 Ordering information Document revision history Date Revision Changes 14-Dec-2004 1 First issue 28-Apr-2008 2 Updated ECOPACK statement. Updated Figure 9, Figure 10, Figure 12, and Figure 13. Reformatted to current standards. EMIF02-USB02F2 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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