ISO8200BQ
Galvanic isolated octal high-side smart power solid state-relay
Datasheet - production data
Applications
Programmable logic control
Industrial PC peripheral input/output
Numerical control machines
Drivers for all types of loads (resistive,
capacitive, inductive)
TFQFPN32
Features
Description
Vdemag = VCC - 45 V (per channel)
The ISO8200BQ is a galvanic isolated 8-channel
driver featuring a very low supply current. It
contains 2 independent galvanic isolated voltage
domains (VCC for the power stage and VDD for the
digital stage). Additional embedded functions are:
loss of GND protection, undervoltage shutdown
with hysteresis, and reset function for immediate
power output shutdown.
RDS(on) = 0.12 (per channel)
IOUT = 0.7 A (per channel)
VCC = 45 V
Parallel input interface
Direct and synchronous control mode
High common mode transient immunity
Short-circuit protection
Channel overtemperature protection
Thermal independence of separate channels
Common output disable pin
Case overtemperature protection
Loss of GNDCC and VCC protection
Undervoltage shutdown with auto-restart and
hysteresis
Overvoltage protection (VCC clamping)
Very low supply current
Common fault open-drain output
5 V and 3.3 V TTL/CMOS compatible I/Os
Fast demagnetization of inductive loads
Reset function for IC output disable
ESD protection
IC is intended to drive any kind of load with one
side connected to ground. Active channel current
limitation combined with thermal shutdown,
(independent for each channel), and automatic
restart, protect the device against overload and
short-circuit. In overload conditions, if junction
temperature overtakes threshold, the channel
involved is turned off and on again automatically
after the IC temperature decreases below a reset
threshold. If this condition causes case
temperature to reach TCR limit threshold, the
overloaded channel is turned off and it only
restarts when case and junction temperature
decrease down to the reset thresholds. Nonoverloaded channels continue operating normally.
An internal circuit provides an OR-wired nonlatched common FAULT indicator signaling the
channel OVT. The FAULT pin is an open-drain
active low fault indication pin.
Designed to meet IEC 61000-4-2, IEC 610004-4, IEC 61000-4-5 and IEC 61000-4-8
UL1577 and UL508 certified
Safety Limits as per VDE0884-11
May 2020
This is information on a product in full production.
DS10781 Rev 9
1/40
www.st.com
Contents
ISO8200BQ
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
Parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.1
Input signals (IN1 to IN8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.2
Load input data (LOAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.3
Output synchronization (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.4
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1.5
Output enable (OUT_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2
Direct control mode (DCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Synchronous control mode (SCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4
Fault indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.4.1
7
Junction overtemperature and case overtemperature . . . . . . . . . . . . . . 23
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9
Reverse polarity on VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10
Demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Supply voltage and power output conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/40
DS10781 Rev 9
ISO8200BQ
12
Contents
Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.1
14
TFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
14.1
TFQFPN32 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
14.1.1
TFQFPN32 packing method concept . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
14.1.2
TFQFPN32 winding direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
14.1.3
TFQFPN32 leader and trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
15
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DS10781 Rev 9
3/40
40
List of tables
ISO8200BQ
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
4/40
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Digital supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Diagnostic pin and output protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power switching characteristics (VCC = 24 V; -40 °C < TJ < 125 °C) . . . . . . . . . . . . . . . . 11
Logic input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Parallel interface timings (VDD = 5 V; VCC = 24 V; -40 °C < TJ < 125 °C) . . . . . . . . . . . . 14
Insulation and safety-related specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Insulation characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Safety limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interface signal operation (general) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interface signal operation in direct control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interface signal operation in synchronous control mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Tolerance of form and position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DS10781 Rev 9
ISO8200BQ
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection (top through view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RDS(on) measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
dV/dT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
td(ON) - td(OFF) synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
td(ON) - td(OFF) direct control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Watchdog behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output channel enable timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Direct control mode IC configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Direct control mode time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Synchronous control mode IC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Synchronous control mode time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Multiple device synchronous control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Thermal status update (DCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Thermal status update (SCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Current limitation with different load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Thermal protection flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reverse polarity protection on VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Maximum demagnetization energy vs. load current, typical values Tamb = 125 °C . . . . . 30
Supply voltage and power output conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Simplified thermal model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TFQFPN32 package detail outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TFQFPN32 suggested footprint (measured in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TFQFPN32 packing method concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TFQFPN32 carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TFQFPN32 reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TFQFPN32 winding direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TFQFPN32 leader and trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DS10781 Rev 9
5/40
40
Block diagram
1
ISO8200BQ
Block diagram
Figure 1. Block diagram
6/40
DS10781 Rev 9
ISO8200BQ
2
Pin connection
Pin connection
Figure 2. Pin connection (top through view)
Table 1. Pin description
Pin
Name
1
GNDDD
2
NC
3
GNDCC
4
OUT8
5
OUT8
6
OUT7
7
OUT7
8
OUT6
9
OUT6
10
OUT5
11
OUT5
12
OUT4
13
OUT4
14
OUT3
15
OUT3
16
OUT2
17
OUT2
Description
Input logic ground, negative logic supply
Not connected
Output power ground
Channel 8 power output
Channel 7 power output
Channel 6 power output
Channel 5 power output
Channel 4 power output
Channel 3 power output
Channel 2 power output
DS10781 Rev 9
7/40
40
Pin connection
ISO8200BQ
Table 1. Pin description (continued)
Pin
Name
18
OUT1
19
OUT1
20
VDD
21
8/40
Description
Channel 1 power output
Positive logic supply
OUT_EN Output enable
22
SYNC
Input-to-output synchronization signal. Active low, see Section 6.3:
Synchronous control mode (SCM) on page 21.
23
LOAD
Load input data signal. Active low, see Section 6.3
24
IN1
Channel 1 input
25
IN2
Channel 2 input
26
IN3
Channel 3 input
27
IN4
Channel 4 input
28
IN5
Channel 5 input
29
IN6
Channel 6 input
30
IN7
Channel 7 input
31
IN8
Channel 8 input
32
FAULT
TAB(VCC)
VCC
TAB(GNDCC)
GNDCC
Common fault indication, active low
Exposed tab internally connected to VCC, positive power supply voltage
Exposed tab internally connected to GNDCC
DS10781 Rev 9
ISO8200BQ
3
Absolute maximum ratings
Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
VCC
Power supply voltage
-0.3
45
V
VDD
Digital supply voltage
-0.3
6.5
V
VIN
DC input pin voltage (INx, OUT_EN, LOAD, SYNC)
-0.3
+6.5
V
VFAULT
Fault pin voltage
-0.3
+6.5
V
IGNDDD
DC digital ground reverse current
-
-25
mA
Channel output current (continuous)
-
Internally limited
A
IGNDcc
DC power ground reverse current
-
-250
mA
-IOUT
Reverse output current (single channel)
-
-5
A
DC input pin current (INx, OUT_EN, LOAD, SYNC)
-10
+ 10
mA
IFAULT
Fault pin current
-10
+ 10
mA
VESD
Electrostatic discharge with human body model
(R = 1.5 k; C = 100 pF)
-
2000
V
Single pulse avalanche energy per channel not
simultaneously at Tamb= 125 °C, IOUT = 0.5 A
-
1.8
Single pulse avalanche energy per channel, all channels
driven simultaneously at Tamb = 125 °C, IOUT = 0.5 A
-
0.35
PTOT
Power dissipation at Tc = 25 °C
-
Internally limited(1)
W
TJ
Junction operating temperature
-
Internally limited(1)
°C
Storage temperature
-
-55 to 150
°C
IOUT
IIN
EAS
TSTG
J
1. Protection functions are intended to avoid IC damage in fault conditions and are not intended for
continuous operation. Continuous or repetitive operations of protection functions may reduce the IC
lifetime.
4
Thermal data
Table 3. Thermal data
Symbol
Rthj-case
Rthj-amb
Parameter
Thermal resistance, junction-case((1)
Thermal resistance,
junction-ambient(2)
Max. value
Unit
2
°C/W
15
°C/W
1. For each channel.
2. TFQFPN32 mounted on the product evaluation board (FR4, 4 layers, 8 cm2 for each layer, copper
thickness 35 mm).
DS10781 Rev 9
9/40
40
Electrical characteristics
5
ISO8200BQ
Electrical characteristics
(10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C, unless otherwise specified)
Table 4. Power section
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VCC(THON)
VCC undervoltage turn-ON
threshold
-
-
9.5
10.5
V
VCC(THOFF)
VCC undervoltage turn-OFF
threshold
-
8
9
-
V
VCC(hys)
VCC undervoltage hysteresis
-
0.25
0.5
-
V
VCCclamp
Clamp on VCC pin
Iclamp = 20 mA
45
50
52
V
On-state resistance(1)
IOUT = 0.5 A, TJ = 25 °C
IOUT = 0.5 A TJ = 125 °C
RDS(on)
Rpd
Output pull-down resistor
ICC
Power supply current
Ground disconnection output
current
ILGND
VOUT(OFF) Off-state output voltage
IOUT(OFF)
Off-state output current
-
0.12
0.24
-
210
-
k
All channels in OFF-state
All channels in ON-state
-
5
9
-
mA
VCC = VGND = 0 V
VOUT = -24 V
-
-
500
μA
Channel OFF and IOUT = 0 A
-
-
1
V
Channel OFF and VOUT = 0 V
-
-
5
μA
1. See Figure 3: RDS(on) measurement.
Table 5. Digital supply voltage
Symbol
VDD
Test conditions
Min. Typ. Max. Unit
Operating voltage
-
2.75
-
5.5
V
VDD(THON)
VDD undervoltage turn-ON
threshold
-
2.55
-
2.75
V
VDD(THOFF)
VDD undervoltage turn-OFF
threshold
-
2.45
-
2.65
V
VDD undervoltage hysteresis -
0.04
0.1
-
V
-
4.5
6
mA
-
4.4
5.9
mA
VDD(hys)
IDD
10/40
Parameter
IDD supply current
VDD = 5 V and input channel
with a steady logic level
VDD = 3.3 V and input channel
with a steady logic level
DS10781 Rev 9
ISO8200BQ
Electrical characteristics
Table 6. Diagnostic pin and output protection function
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VFAULT
FAULT pin open-drain voltage
output low
IFAULT = 10 mA
-
-
0.4
V
ILFAULT
FAULT output leakage current
VFAULT = 5 V
-
-
1
μA
IPEAK
Maximum DC output current
before limitation
VCC = 24 V
RLOAD = 0
-
1.6
-
A
ILIM
Short-circuit current limitation
-
0.7
1.3
1.9
A
Hyst
ILIM tracking limits
-
-
0.3
-
A
TJSD
Junction shutdown temperature
-
150
170
-
°C
TJR
Junction reset temperature
-
-
150
-
°C
THIST
Junction thermal hysteresis
-
-
20
-
°C
TCSD
Case shutdown temperature
-
115
130
145
°C
TCR
Case reset temperature
-
-
110
-
°C
TCHYST
Case thermal hysteresis
-
-
20
-
°C
Vdemag
Output voltage at turn-OFF
IOUT = 0.5 A
ILOAD > = 1 mH
VCC -45
VCC -50
VCC -52
V
Table 7. Power switching characteristics (VCC = 24 V; -40 °C < TJ < 125 °C)
Symbol
dV/dt(ON)
Parameter
Test conditions
Turn-ON voltage slope
dV/dt(OFF) Turn-OFF voltage slope
td(ON)
Turn-ON delay time(1)
td(OFF)
Turn-OFF delay
tf
time(1)
tr
Fall
(1)
Rise time
time(1)
Min. Typ. Max. Unit
IOUT = 0.5 A, resistive load 48
-
5.6
-
V/μs
IOUT = 0.5 A, resistive load 48
-
2.81
-
V/μs
IOUT = 0.5 A, resistive load 48
-
17
22
μs
IOUT = 0.5 A, resistive load 48
-
22
40
μs
IOUT = 0.5 A, resistive load 48
-
5
-
μs
IOUT = 0.5 A, resistive load 48
-
5
-
μs
1. See Figure 3: RDS(on) measurement , Figure 4: dV/dT and Figure 6: td(ON) - td(OFF) direct control mode.
DS10781 Rev 9
11/40
40
Electrical characteristics
ISO8200BQ
Figure 3. RDS(on) measurement
Figure 4. dV/dT
12/40
DS10781 Rev 9
ISO8200BQ
Electrical characteristics
Figure 5. td(ON) - td(OFF) synchronous mode
Figure 6. td(ON) - td(OFF) direct control mode
DS10781 Rev 9
13/40
40
Electrical characteristics
ISO8200BQ
Table 8. Logic input and output
Symbol
Parameter
Test conditions
VIL
Logic input pin low level voltage (INx, OUT_EN,
LOAD, SYNC)
VIH
Logic input pin high level voltage (INx, OUT_EN,
LOAD, SYNC)
Min.
Max.
Unit
-0.3
0.3 x VDD
V
0.7 x VDD
VDD + 0.3
V
-
Typ.
VI(HYST)
Logic input hysteresis voltage (INx, OUT_EN,
LOAD, SYNC)
VDD = 5 V
-
100
-
mV
IIN
Logic input pin current (INx, OUT_EN, LOAD,
SYNC)
VIN = 5 V
10
-
-
μA
Power side watchdog time
-
272
320
400
μs
tWM
Table 9. Parallel interface timings (VDD = 5 V; VCC = 24 V; -40 °C < TJ < 125 °C)
Symbol
Parameter
tdis(SYNC) SYNC disable time
Test conditions
Min.
Typ.
Max.
Unit
Sync. control mode
10
-
-
μs
tdis(DCM)
SYNC, LOAD disable time
Direct control mode
80
-
-
ns
tw(SYNC)
SYNC negative pulse width
Sync. control mode
20
-
195
μs
tsu(LOAD)
LOAD setup time
Sync. control mode
80
-
-
ns
th(LOAD)
LOAD hold time
Sync. control mode
400
-
-
ns
tw(LOAD)
LOAD pulse width
Sync. control mode
240
-
-
ns
tsu(IN)
Input setup time
-
80
-
-
ns
th(IN)
Input hold time
-
10
-
-
ns
tw(IN)
Input pulse width
Sync. control mode
160
-
-
ns
Direct control mode
20
-
-
μs
tINLD
IN to LOAD time
Direct control mode
From IN variation to LOAD falling edge
80
-
-
ns
tLDIN
LOAD to IN time
Direct control mode
From LOAD falling edge to IN variation
400
-
-
ns
-
150
-
-
ns
tp(OUT_EN) OUT_EN propagation delay -
-
22
40
μs
tjitter(SCM)
tw(OUT_EN) OUT_EN pulse width
tjitter(DCM)
frefresh
14/40
Jitter on single channel
Sync. mode
Direct mode
-
-
6
20
μs
Refresh delay
-
-
15
-
kHz
DS10781 Rev 9
ISO8200BQ
Electrical characteristics
Table 10. Insulation and safety-related specifications
Symbol
Parameter
Test conditions
Value Unit
CLR
Clearance (minimum
external air gap)
Measured from input terminals to output
terminals, the shortest distance through air
3.3
mm
CPG
Creepage (minimum
external tracking)
Measured from input terminals to output
terminals, the shortest distance path along body
3.3
mm
600
V
I
-
CTI
Comparative tracking
DIN IEC 112/VDE 0303 part 1
index (tracking resistance)
Isolation group
Material group (DIN VDE 0110, 1/89, Table 1)
Table 11. Insulation characteristics
Symbol
Parameter
Test conditions
Value
Unit
-
937
VPEAK
Method a, type test,
VPR = VIORM x 1.6, tm = 10s
partial discharge < 5 pC
1500
VPEAK
Method b, 100% production test,
VPR = VIORM x 1.875, tm = 1s
partial discharge < 5 pC
1758
VPEAK
IEC 60747-5-5
VIORM
VPR
Maximum working isolation
Input to output test voltage
VIOTM
Transient overvoltage
Type test
tini = 60 s
4245
VPEAK
VIOSM
Maximum surge insulation
voltage
Type test
4245
VPEAK
Insulation resistance
VIO = 500 V at ts
>109
Insulation withstand voltage
1 min. type test
2500/3536 Vrms/VPEAK
1 s 100% production
3000/4245 Vrms/VPEAK
RIO
UL1577
VISO
VISO test Insulation withstand test
DS10781 Rev 9
15/40
40
Electrical characteristics
ISO8200BQ
Table 12. Safety limits
Parameter
Description
Test Condition
Limit value
Unit
-
150
o
0.9
W
150
o
4.5
W
Input safety, Logic side
Tsi
Psi
Safety temperature of Logic side
Safety power of Logic side
VDD ≤ 6.5V,
VLOGIC(x) ≤ 6.5V,
ILOGIC(x) ≤ 10mA,
TJ ≤ Tsi
C
Output safety, Process side
Note:
Tso
Safety temperature of Process side
Pso
Safety power of Process side
VCC ≤ 36V,
IOUT(x) ≤ 1.5A,
TJ ≤ Tso
The above limits are measured according to VDE 0884-11. Respecting above limits
prevents potential damage potential damage to the isolation barrier upon failure on logic or
process side circuitry. User can use these values to protect the IC and consequently
guarantee the safety of the embedded isolation barrier.
LOGIC(X) stands for "any pin of logic side".
OUT(X) stands for "any of the 8 output pins of process side".
16/40
C
DS10781 Rev 9
ISO8200BQ
Functional description
6
Functional description
6.1
Parallel interface
Smart parallel interface built-in ISO8200BQ offers three interfacing signals easily managed
by a microcontroller.
The LOAD signal enables the input buffer storing the value of the channel inputs.
The SYNC signal copies the input buffer value into the transmission buffer and manages the
synchronization between low voltage side and the channel outputs on the isolated side. The
OUT_EN signal enables the channel outputs.
An internal refresh signal updates the configuration of the channel outputs with a frefresh
frequency. This signal can be disabled forcing low the SYNC input when LOAD is high.
SYNC and LOAD pins can be in direct control mode (DCM) or synchronous control mode
(SCM).
The operation of these two signals is described as follows:
Table 13. Interface signal operation (general)
LOAD
SYNC
Don't care Don't care
OUT_EN
Low(1)
Device behavior
The outputs are disabled (turned off)
High
High
High
The outputs are left unchanged
Low
High
High
The input buffer is enabled
The outputs are left unchanged
High
Low
High
The internal refresh signal is disabled
The transmission buffer is updated
The outputs are left unchanged
Low
Low
High
The device operates in direct control mode as described in
Section 6.2: Direct control mode (DCM)
1. The outputs are turned off on OUT_EN falling edge and they are kept disabled as long as it is low.
6.1.1
Input signals (IN1 to IN8)
Inputs from IN1 to IN8 are the driving signals of the corresponding OUT1 to OUT8 outputs.
Data are direct loaded on related outputs if SYNC and LOAD inputs are low (DCM
operation) or stored into input buffer when LOAD is low and SYNC is high.
6.1.2
Load input data (LOAD)
The input is active low; it stores the data from IN1 to IN8 into the input buffer.
6.1.3
Output synchronization (SYNC)
The input is active low; it enables the ISO8200BQ transmission buffer loading input buffer
data and manages the transmission between the two isolated sides of the device.
DS10781 Rev 9
17/40
40
Functional description
6.1.4
ISO8200BQ
Watchdog
The isolated side of the device provides a watchdog function in order to guarantee a safe
condition when VDD supply voltage is missing.
If the logic side does not update the output status within tWD, all outputs are disabled until a
new update request is received.
The refresh signal is also considered a valid update signal, so the isolated side watchdog
does not protect the system from a failure of the host controller (MCU freezing).
Figure 7. Watchdog behavior
18/40
DS10781 Rev 9
ISO8200BQ
6.1.5
Functional description
Output enable (OUT_EN)
This pin provides a fast way to disable all outputs simultaneously. When the OUT_EN pin is
driven low the outputs are disabled. To enable the output stage, the OUT_EN pin has to be
raised. This timing execution is compatible with an external reset push, safety requirement,
and allows, in a PLC system, the microcontroller polling to obtain all internal information
during a reset procedure.
Figure 8. Output channel enable timing
6.2
Direct control mode (DCM)
When SYNC and LOAD inputs are driven by the same signal, the device operates in direct
control mode (DCM).
In DCM the SYNC / LOAD signal operates as an active low input enable:
When the signal is high, the current output configuration is kept regardless the input
values
When the signal is low, each channel input directly drives the respective output
This operation mode can also be set shorting both signals to the digital ground; in this case
the channel outputs are always directly driven by the inputs except when OUT_EN is low
(outputs disabled).
Table 14. Interface signal operation in direct control mode
SYNC / LOAD
Don't care
OUT_EN
Low
(1)
Device behavior
The outputs are disabled (turned off)
High
High
The outputs are left unchanged
Low
High
The channel inputs drive the outputs
1. The outputs are turned off on OUT_EN falling edge and they are kept disabled as long as it is low.
DS10781 Rev 9
19/40
40
Functional description
ISO8200BQ
Figure 9. Direct control mode IC configuration
Figure 10. Direct control mode time diagram
20/40
DS10781 Rev 9
ISO8200BQ
6.3
Functional description
Synchronous control mode (SCM)
When SYNC and LOAD inputs are independently driven, the device can operate in
synchronous control mode (SCM). The SCM is used to reduce the jittering of the outputs
and to drive all outputs of different devices at the same time.
In SCM the LOAD signal is forced low to update the input buffer while the SYNC signal is
high. The LOAD signal is raised and the SYNC one is forced low for at least tSYNC(SCM).
During this period, the internal refresh is disabled and any pending transmission between
the low voltage and the isolated side is completed. When the SYNC signal is raised the
channel output configuration is changed according to the one stored in the input.
If the tSYNC(SCM) limit is met, the maximum jitter of the channel outputs is tjitter(SCM).
If more devices share the same SYNC signal, all device outputs change simultaneously with
a maximum jitter related to maximum delay and maximum jitter for single device.
Table 15. Interface signal operation in synchronous control mode
LOAD
SYNC
OUT_EN
Device behavior
Don't care
Don't care
Low(1)
High
High
High
The outputs are left unchanged
Low
High
High
The input buffer is enabled. The outputs are left unchanged.
High
Low
High
The internal refresh signal is disabled. The transmission buffer
is updated. The outputs are left unchanged.
High
Rising
edge
High
The outputs are updated according to the current transmission
buffer value
Low
Low
High
Should be avoided (DCM operation only)
The outputs are disabled (turned off)
1. The outputs are turned off on OUT_EN falling edge and they are kept disabled as long as it is low.
Figure 11. Synchronous control mode IC configuration
DS10781 Rev 9
21/40
40
Functional description
ISO8200BQ
Figure 12. Synchronous control mode time diagram
Figure 13. Multiple device synchronous control mode
22/40
DS10781 Rev 9
ISO8200BQ
6.4
Functional description
Fault indication
The FAULT pin is an active low open-drain output indicating fault conditions. This pin is
active when at least one of the following conditions occurs:
Junction overtemperature of one or more channels (TJ >TTJSD)
Communication error
The communication error is intended as an internal data corruption event in the data transfer
through isolation. In case of communication error the outputs are initially kept in the previous
status and then reset (turned off) at the first communication error during data transfer of the
refresh signal.
6.4.1
Junction overtemperature and case overtemperature
The thermal status of the device is updated during each transmission sequence between
the two isolated sides.
In SCM operation, when the LOAD signal is high and the SYNC one is low, the
communication is disabled. In this case the thermal status of the device cannot be updated
and the FAULT indication can be different from the current status.
In any case, the thermal protection of the channel outputs is always operative.
Figure 14. Thermal status update (DCM)
DS10781 Rev 9
23/40
40
Functional description
ISO8200BQ
Figure 15. Thermal status update (SCM)
24/40
DS10781 Rev 9
ISO8200BQ
Power section
7
Power section
7.1
Current limitation
The current limitation process is active when the current sense connected on the output
stage measures a current value, which is higher than a fixed threshold.
When this condition is verified the gate voltage is modulated to avoid the increase of the
output current over the limitation value.
Figure 16 shows typical output current waveforms with different load conditions.
Figure 16. Current limitation with different load conditions
DS10781 Rev 9
25/40
40
Power section
7.2
ISO8200BQ
Thermal protection
The device is protected against overheating in case of overload conditions. During the
driving period, if the output is overloaded, the device suffers two different thermal stresses,
the former related to the junction, and the latter related to the case.
The two faults have different trigger thresholds: the junction protection threshold is higher
than the case protection one; generally the first protection, that is active in thermal stress
conditions, is the junction thermal shutdown. The output is turned off when the temperature
is higher than the related threshold and turned back on when it goes below the reset
threshold. This behavior continues until the fault on the output is present.
If the thermal protection is active and the temperature of the package increases over the
fixed case protection threshold, the case protection is activated and the output is switched
off and back on when the junction temperature of each channel in fault and case
temperature is below the respective reset thresholds.
Figure 17 shows the thermal protection behavior, while Figure 18 reports typical
temperature trends and output vs. input state.
Figure 17. Thermal protection flowchart
26/40
DS10781 Rev 9
ISO8200BQ
Power section
Figure 18. Thermal protection
DS10781 Rev 9
27/40
40
Reverse polarity protection
8
ISO8200BQ
Reverse polarity protection
Reverse polarity protection can be implemented on board using two different solutions:
1. Placing a resistor (RGND) between IC GND pin and load GND
2. Placing a diode in parallel to a resistor between IC GND pin and load GND
If option 1 is selected, the minimum resistance value has to be selected according to
Equation 1:
Equation 1
RGND VCC/IGNDcc
where IGNDcc is the DC reverse ground pin current and can be found in Section 3: Absolute
maximum ratings on page 9.
Power dissipated by RGND during reverse polarity situations is:
Equation 2
PD = (VCC)2/RGND
If option 2 is selected, the diode has to be chosen by taking into account VRRM > |VCC| and
its power dissipation capability:
Equation 3
PD IS * VF
Note:
In normal operation (no reverse polarity), there is a voltage drop (ΔV) between GND of
the device and GND of the system. Using option 1, ΔV = Rgnd * Icc. Using option 2,
ΔV = VF@(IF).
Figure 19. Reverse polarity protection
This schematic can be used with any type of load.
28/40
DS10781 Rev 9
ISO8200BQ
9
Reverse polarity on VDD
Reverse polarity on VDD
The reverse polarity on VDD can be implemented on board by placing a diode between
GNDDD pin and GND digital ground.
The diode has to be chosen by taking into account VRRM > |VDD| and its power dissipation
capability:
Equation 4
PD IDD * VF
Note:
In normal operation (no reverse polarity), there is a voltage drop (ΔV = VF@(Idd))
between GNDDD of the device and digital ground of the system.
In order to guarantee to proper triggering of the input signal, ΔV(max.) must result lower
than VIH(MIN).
Figure 20. Reverse polarity protection on VDD
DS10781 Rev 9
29/40
40
Demagnetization energy
10
ISO8200BQ
Demagnetization energy
Figure 21. Maximum demagnetization energy vs. load current, typical values
Tamb = 125 °C
11
Conventions
Supply voltage and power output conventions
Figure 22 shows the convention used in this paper for voltage and current usage.
Figure 22. Supply voltage and power output conventions
30/40
DS10781 Rev 9
ISO8200BQ
12
Thermal information
Thermal information
Thermal impedance
Figure 23. Simplified thermal model
DS10781 Rev 9
31/40
40
Package information
13
ISO8200BQ
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
13.1
TFQFPN32 package information
Figure 24. TFQFPN32 package outline
32/40
DS10781 Rev 9
ISO8200BQ
Package information
Figure 25. TFQFPN32 package detail outline
Figure 26. TFQFPN32 suggested footprint (measured in mm)
0.3
0
0.3
0
0.7
0
0.3
0
0.9
0
0.2
0
0.2
0
0.9
0
DS10781 Rev 9
33/40
40
Package information
ISO8200BQ
Table 16. TFQFPN32 package mechanical data
Dimensions (mm]
Symbol
Min.
Typ.
Max.
A
0.95
1.00
1.05
A1
0
-
0.05
A2
-
0.20 REF
-
b(1)
0.20
0.25
0.30
0.25
0.30
0.35
D
10.90
11.0
11.10
E(1)
8.90
9.00
9.10
D2
4.30
4.40
4.50
E2
6.70
6.80
6.90
D3
1.40
1.50
1.60
E3
3.20
3.30
3.40
D4
1.13
1.23
1.33
E4
1.00
1.10
1.20
e
-
0.65
-
e2
-
0.40
-
e3
-
1.05
-
e4
-
3.15
-
e5
-
4.85
-
k
0
0.30
-
z1
-
0.80
-
z2
-
4.07
-
z3
-
3.80
-
z4
-
1.10
-
z5
-
1.15
-
z6
-
2.85
-
0.45
0.50
0.55
b1
(1)
(1)
L
1. Dimensions “b” and “L” are measured on terminal plating surface.
34/40
DS10781 Rev 9
ISO8200BQ
Package information
Table 17. Tolerance of form and position
Symbol
Tolerance of form
and position
aaa
0.15
The bilateral profile tolerance that controls the position
of the plastic body sides. The centers of the profile
zones are defined by the basic dimensions D and E.
bbb
0.10
The tolerance that controls the position of the entire
terminal pattern with respect to datum's A and B. The
center of the tolerance zone for each terminal is defined
by the basic dimension "e" as related to datum's A and
B.
ccc
0.10
The tolerance located parallel to the seating plane in
which the top surface of the package must be located.
0.08
The tolerance that controls the position of the terminals
to each other. The centers of the profile zones are
defined by basic dimension "e".
0.08
This tolerance is
The unilateral tolerance located above the seating plane
commonly known as
where in the bottom surface of all terminals must be
the “coplanarity” of the
located.
package terminals.
fff
0.10
The tolerance that controls the position of the exposed
metal heat feature. The center of the tolerance zone will
be datum's defined by the centerlines of the package
body.
REF
-
-
ddd
eee
Definition
DS10781 Rev 9
Notes
This tolerance is
normally compounded
with tolerance zone
defined by bbb.
No tolerance for A2
35/40
40
Packing information
ISO8200BQ
14
Packing information
14.1
TFQFPN32 packing information
14.1.1
TFQFPN32 packing method concept
Figure 27. TFQFPN32 packing method concept
36/40
DS10781 Rev 9
ISO8200BQ
Packing information
Figure 28. TFQFPN32 carrier tape
Reel – 330 mm diameter x 101 mm hub x 24 mm width
Figure 29. TFQFPN32 reel
DS10781 Rev 9
37/40
40
Packing information
14.1.2
ISO8200BQ
TFQFPN32 winding direction
Figure 30. TFQFPN32 winding direction
14.1.3
TFQFPN32 leader and trailer
Figure 31. TFQFPN32 leader and trailer
Note:
38/40
Leader and trailer length as per EAI-481specification.
DS10781 Rev 9
ISO8200BQ
15
Ordering information
Ordering information
Table 18. Ordering information
16
Order code
Package
Packing
ISO8200BQ
TFQFPN32
Tube
ISO8200BQTR
TFQFPN32
Tape and reel
Revision history
Table 19. Document revision history
Date
Revision
17-Nov-2016
3
Datasheet promoted from preliminary to production data. Updated
Table 6: Diagnostic pin and output protection function.
21-Apr-2017
4
Updated Table 10: “Insulation and safety-related specifications”.
Minor text changes.
05-Oct-2017
5
Updated Table 11: “IEC 60747-5-2 insulation characteristics”.
6
Updated Section : Features on page 1.
Replaced Vdd by VDD in whole document.
Updated titles of Table 7 on page 11 and Table 9 on page 14 .
Updated titles of Figure 3 on page 12, Figure 5 on page 13, Figure 6
on page 13, Figure 20 on page 29 and Figure 21 on page 30 .
Added cross-reference to Section 6.2 in Table 13 on page 17.
Updated Figure 9 on page 20 and Figure 11 on page 21 (replaced
ISO8200B by ISO8200BQ).
Added Section on page 34.
Minor modifications throughout document.
24-Apr-2019
7
Added Table 12: Safety limits on page 15,
Updated Table 2: Absolute maximum ratings on page 9
Updated Section : Features on page 1.
Minor text changes.
18-Oct-2019
8
Updated Section : Features on page 1.
08-May-2020
9
Table 4, 11 and 16 updated. Figure 24 replaced. Table 17 added.
18-May-2018
Changes
DS10781 Rev 9
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40
ISO8200BQ
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DS10781 Rev 9
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