L6491D

L6491 High voltage high and low-side 4 A gate driver Datasheet - production data Applications  Motor driver for home appliances, factory automation, industrial drives and fans  HID ballasts  Power supply unit SO-14  Induction heating  Wireless chargers Features  Industrial inverters  UPS  High voltage rail up to 600 V  dV/dt immunity ± 50 V/ns in full temperature range Description  Driver current capability: 4 A source/sink The L6491 is a high voltage device manufactured with the BCD6 “OFF-LINE” technology. It is a single-chip half-bridge gate driver for N-channel power MOSFET or IGBT.  Switching times 15 ns rise/fall with 1 nF load  3.3 V, 5 V TTL/CMOS inputs with hysteresis  Integrated bootstrap diode  Comparator for fault protections  Smart shutdown function  Adjustable deadtime  Interlocking function  Compact and simplified layout The high-side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing microcontroller/DSP. An integrated comparator is available for fast protection against overcurrent, overtemperature, etc.  Bill of material reduction Table 1. Device summary  Effective fault protection  Flexible, easy and fast design March 2015 This is information on a product in full production. Order code Package Packaging L6491D SO-14 Tube L6491DTR SO-14 Tape and reel DocID024832 Rev 1 1/24 www.st.com Contents L6491 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 DocID024832 Rev 1 L6491 1 Block diagram Block diagram Figure 1. Block diagram VCC PGND DocID024832 Rev 1 3/24 24 Pin connection 2 L6491 Pin connection Figure 2. Pin connection (top view) /,1   %227 6' 2'   +9* +,1   287 9&&   1& '7   &3 6*1'   &3 3*1'   /9* $0 Table 2. Pin description Pin number Pin name Type 1 LIN I 2 SD/OD(1) I/O 3 HIN I High-side driver logic input (active high) 4 VCC P Lower section supply voltage 5 DT I Deadtime setting 6 SGND P Signal ground 7 PGND P Power ground 8 (1) LVG O Low-side driver output 9 CP- I Comparator negative input 10 CP+ I Comparator positive input 11 NC 12 OUT P High-side (floating) common voltage 13 HVG(1) O High-side driver output 14 BOOT P Bootstrapped supply voltage Function Low-side driver logic input (active low) Shutdown logic input (active low)/open-drain comparator output Not connected 1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low. When the SD is set low, gate driver outputs are forced low and assure low impedance. 4/24 DocID024832 Rev 1 L6491 3 Truth table Truth table Table 3. Truth table Input Output SD LIN HIN LVG HVG L X(1) X(1) L L H H L L L H L H L L H L L H L H H H L H 1. X: don't care. DocID024832 Rev 1 5/24 24 Electrical data L6491 4 Electrical data 4.1 Absolute maximum ratings Table 4. Absolute maximum ratings(1) Value Symbol Parameter Unit Min. Max. -0.3 21 V Low-side driver ground VCC - 21 VCC + 0.3 V Vout Output voltage Vboot - 21 Vboot + 0.3 V Vboot Bootstrap voltage -0.3 620 V Vhvg High-side gate output voltage Vout - 0.3 Vboot + 0.3 V Vlvg Low-side gate output voltage PGND - 0.3 VCC + 0.3 V -0.3 5.5 V -0.3 5.5 V VCC VPGND VcpVcp+ Supply voltage Comparator negative input Comparator positive input voltage(2) voltage(2) Vi Logic input voltage -0.3 15 V VOD Open-drain voltage -0.3 15 V 50 V/ns dvout / dt Allowed output slew rate Ptot Total power dissipation (TA = 25 °C) 1.0 W TJ Junction temperature 150 °C Tstg Storage temperature 150 °C ESD Human body model -50 2 kV 1. Each voltage referred to SGND unless otherwise specified. 2. Spikes up to 20 V can be tolerated if the duration is shorter than 50 ns (fSW = 120 kHz). 4.2 Thermal data Table 5. Thermal data Symbol Rth(JA) 6/24 Parameter Thermal resistance junction to ambient DocID024832 Rev 1 SO-14 Unit 120 °C/W L6491 4.3 Electrical data Recommended operating conditions Table 6. Recommended operating conditions Symbol Pin VCC 4 VPS(1) 7-6 VBO(2) 1. Parameter Test conditions Min. Max. Unit 10 20 V Low-side driver ground -1.5 +1.5 V 14 - 12 Floating supply voltage 9.3 20 V 580 V Supply voltage (3) Vout 12 DC output voltage -9 VCP- 9 Comparator negative input pin voltage VCP+ 2.5 V 5(4) V VCP+ 10 Comparator positive input pin voltage VCP- 2.5 V 5(4) V fsw Switching frequency HVG, LVG load CL = 1 nF 800 kHz TJ Junction temperature 125 °C -40 VPS = VPGND - SGND. 2. VBO = Vboot - Vout. 3. LVG off. VCC = 12.5 V. Logic is operational if Vboot > 5 V. 4. At least one of the comparator's inputs must be lower than 2.5 V to guarantee proper operation. DocID024832 Rev 1 7/24 24 Electrical characteristics L6491 5 Electrical characteristics 5.1 AC operation Table 7. AC operation electrical characteristics (VCC = 15 V; PGND = SGND; TJ = +25 °C) Symbol ton toff tsd Pin Parameter Test conditions High/low-side driver turn-on OUT = 0 V 1 vs. 8 propagation delay 3 vs 13 High/low-side driver turn-off BOOT = VCC CL = 1 nF propagation delay Vi = 0 to 3.3 V 2 vs. Shutdown to high/low-side see Figure 3 8, 13 driver propagation delay tisd Comparator triggering to Measured applying a voltage step from high/low-side driver turn-off 0 V to 3.3 V to pin CP+; CP- = 0.5 V propagation delay MT Delay matching, HS and LS turn-on/off(1) DT Deadtime setting range see Figure 4 5 MDT tr tf Matching 8,13 deadtime(2) 85 120 ns 85 120 ns 85 120 ns 175 220 ns 30 ns RDT = 0 , CL = 1 nF 0.12 0.18 0.24 µs RDT = 100 k, CL = 1 nF, CDT = 100 nF 1.2 1.4 1.6 µs RDT = 200 k, CL = 1 nF, CDT = 100 nF 2.2 2.6 3 µs RDT = 0 , CL = 1 nF 50 ns RDT = 100 k, CL = 1 nF, CDT = 100 nF 165 ns RDT = 200 k, CL = 1 nF, CDT = 100 nF 260 ns Rise time CL = 1 nF 15 40 ns Fall time CL = 1 nF 15 40 ns 1. MT = max. (|ton(LVG) - toff(LVG)|, |ton(HVG) - toff(HVG)|, |toff(LVG) - ton(HVG)|, |toff(HVG) - ton(LVG)|). 2. MDT = | DTLH - DTHL | (see Figure 5 on page 14). 8/24 Min. Typ. Max. Unit DocID024832 Rev 1 L6491 Electrical characteristics Figure 3. Timing   /,1 WU WI    /9*  W RQ W RII   +,1 WU WI    +9*  W RQ W RII  6' WI  /9*+9*  W VG $0 DocID024832 Rev 1 9/24 24 Electrical characteristics L6491 Figure 4. Typical deadtime vs. DT resistor value   $SSUR[LPDWHGIRUPXODIRU5GW FDOFXODWLRQW\S 5 GW >N:@ '7>—V@   '7>—V@               5GW >N:@ 10/24 DocID024832 Rev 1   $0 L6491 5.2 Electrical characteristics DC operation Table 8. DC operation electrical characteristics (VCC = 15 V; PGND = SGND; TJ = + 25 °C) Symbol Pin Min. Typ. Max. Unit VCC UV hysteresis 0.5 0.6 0.72 V Vcc_thON VCC UV turn-ON threshold 8.7 9.3 9.8 V Vcc_thOFF VCC UV turn-OFF threshold 8.2 8.7 9.2 V Undervoltage quiescent supply current VCC = 8 V SD = 5 V; LIN = 5 V; HIN = SGND; RDT = 0 ; CP+ = SGND; CP- = 5 V 160 210 A Quiescent current VCC = 15 V SD = 5 V; LIN = 5 V; HIN = SGND; RDT = 0 ; CP+ = SGND; CP- = 5 V 540 700 A 0.48 0.6 0.7 V Vcc_hys Iqccu Iqcc 4 Parameter Test conditions Bootstrapped supply voltage section(1) VBO_hys VBO UV hysteresis VBO_thON VBO UV turn-ON threshold 8 8.6 9.1 V VBO_thOFF VBO UV turn-OFF threshold 7.5 8.0 8.5 V IQBOU VCC = VBO = 7 V SD = 5 V; LIN and Undervoltage VBO quiescent HIN = 5 V; 14-12 current RDT = 0 ; CP+ = SGND; CP- = 5 V 20 30 A IQBO VBO = 15 V SD = 5 V; LIN and HIN = 5 V; RDT = 0 ; CP+ = SGND; CP- = 5 V 90 120 A 8 A ILK RDS(on) VBO quiescent current High voltage leakage current BOOT = HVG = OUT = 600 V Bootstrap driver on resistance(2) 175 DocID024832 Rev 1  11/24 24 Electrical characteristics L6491 Table 8. DC operation electrical characteristics (VCC = 15 V; PGND = SGND; TJ = + 25 °C) (continued) Symbol Pin Parameter Test conditions Min. Typ. LVG/HVG ON TJ = 25 °C 3.5 4 Full temperature range 2.5 LVG/HVG OFF TJ = 25 °C 3.5 Full temperature range 2.5 Max. Unit Driving buffer section High/low-side source peak current Iso 8, 13 High/low-side sink peak current Isi A A 4 A A Logic inputs Vil Low level logic threshold Vih 1, 2, 3 High level logic threshold voltage VSSD 2 1, 3 LIN and HIN connected together and floating HIN logic “1” input bias current HIN = 15 V IHINl HIN logic “0” input bias current HIN = 0 V ILINl LIN logic “0” input bias current LIN = 0 V ILINh LIN logic “1” input bias current LIN = 15 V ISDh SD logic “1” input bias current SD = 15 V SD logic “0” input bias current SD = 0 V IHINh 3 1 2 ISDl 1.45 V 2 2.5 V 0.8 V 0.8 V 260 A 1 A 15 A 1 A 60 A 1 A SmartSD unlatch threshold Single input voltage Vil_S 0.95 120 5 20 200 10 40 1. VBO = Vboot - Vout. 2. RDS(on) is tested in the following way: RDS(on) = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1(VCC, VBOOT1) - I2(VCC, VBOOT2)] where I1 is pin 14 current when VBOOT = VBOOT1, I2 when VBOOT = VBOOT2. 12/24 DocID024832 Rev 1 L6491 Electrical characteristics Table 9. Sense comparator(1) (VCC = 15 V, TJ = +25 °C) Symbol Pin Parameter Vio 9, 10 Input offset voltage Iib 9, 10 Input bias current IOD 2 td_comp SR 2 Test conditions Min. Typ. Max. Unit 15 mV 1 A 20 27 mA 155 ns -15 VCP+ = 1 V, VCP- = 1 V Open-drain low level sink current SD\OD = 400 mV, VCP+ = 1 V; VCP - = 0.5 V; Comparator delay Rpu = 100 k to 5 V; VCP - = 0.5 V; voltage step on CP+ = 0 to 3.3 V; 50% CP+ to 90% SD 100 Slew rate CL = 10 nF; Rpu = 5 k to 5 V; 90% SD to 10% SD 10 13 V/s 1. Comparator is disabled when VCC is in UVLO condition. DocID024832 Rev 1 13/24 24 Waveform definitions 6 L6491 Waveform definitions Figure 5. Deadtime and interlocking waveform definitions /9* ,,17 (5/ 2&. ,1 +,1 ,17 &21752/6,*1$/('*( 29(5/$33(' ,17(5/2&.,1*'($'7,0( (5/ 2&. ,1 * * /,1 '7+/ '7/+ +9* JDWHGULYHURXWSXWV2)) +$/)%5,'*(67$7( JDWHGULYHURXWSXWV2)) +$/)%5,'*(67$7( /,1 &21752/6,*1$/('*( 6