STB14N80K5

STB14N80K5 N-channel 800 V, 0.400 Ω typ., 12 A MDmesh™ K5 Power MOSFET in a D²PAK package Datasheet - production data Features TAB      2 3 1 D²PAK Order code VDS RDS(on) max. ID STB14N80K5 800 V 0.445 Ω 12 A Industry’s lowest RDS(on) x area Industry’s best figure of merit (FoM) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STB14N80K5 14N80K5 D²PAK Tape and reel February 2016 DocID027723 Rev 1 This is information on a product in full production. 1/16 www.st.com Contents STB14N80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 5 2/16 4.1 D2PAK (TO-263) type A package information................................. 10 4.2 D2PAK (TO-263) packing information ............................................. 13 Revision history ............................................................................ 15 DocID027723 Rev 1 STB14N80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 12 A ID Drain current (continuous) at TC = 100 °C 7.4 A Drain current (pulsed) 48 A W (1) ID PTOT Total dissipation at TC = 25 °C 130 dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range TJ Operating junction temperature range - 55 to 150 V/ns °C Notes: (1) Pulse width limited by safe operating area. (2) ISD ≤ 12 A, di/dt ≤ 100 A/μs; VDS(peak) < V(BR)DSS,VDD= 640 V (3) VDS ≤ 640 V Table 3: Thermal data Symbol Parameter Rthj-case Rthj-pcb (1) Value Unit Thermal resistance junction-case 0.96 °C/W Thermal resistance junction-pcb 30 °C/W Notes: (1) When mounted on FR-4 board of 1 inch², 2 oz Cu Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 4 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 270 mJ DocID027723 Rev 1 3/16 Electrical characteristics 2 STB14N80K5 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol Parameter V(BR)DSS Drain-source breakdown voltage Test conditions Min. VGS = 0 V, ID = 1 mA 800 Typ. Max. Unit V VGS = 0 V, VDS = 800 V 1 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 800 V (1) TC = 125 °C 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 6 A 0.400 0.445 Ω 3 Notes: (1) Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance (1) Co(tr) (2) Co(er) Test conditions Equivalent capacitance time related Equivalent capacitance energy related VDS = 0 to 640 V, VGS = 0 V Min. Typ. Max. Unit - 620 - pF - 60 - pF - 0.8 - pF - 107 - pF - 39 - pF 6.5 - Ω - nC Rg Intrinsic gate resistance f = 1 MHz , ID= 0 A - Qg Total gate charge - Qgs Gate-source charge Qgd Gate-drain charge VDD = 640 V, ID = 12 A VGS= 10 V (see Figure 16: "Test circuit for gate charge behavior" 22 - 4.3 - nC - 16.5 - nC Notes: (1) Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when V DS increases from 0 to 80% VDSS (2) Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/16 DocID027723 Rev 1 STB14N80K5 Electrical characteristics Table 7: Switching times Symbol td(on) tr Parameter Turn-on delay time Rise time td(off) tf Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD= 400 V, ID =6 A, RG = 4.7 Ω VGS = 10 V see ( Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform") - 12.5 - ns - 8 - ns - 33 - ns - 10 - ns Min. Typ. Max. Unit Table 8: Source-drain diode Symbol Parameter Test conditions Source-drain current - 12 A (1) Source-drain current (pulsed) - 48 A (2) Forward on voltage ISD = 12 A, VGS = 0 V - 1.5 V trr Reverse recovery time - 365 ns Qrr Reverse recovery charge - 4.77 µC IRRM Reverse recovery current ISD = 12 A, di/dt = 100 A/µs,VDD = 60 V (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 26 A ISD = 12 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 485 ns - 5.85 µC - 24 A Min. Typ. Max. Unit 30 - - V ISD ISDM VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1) (2) Pulse width limited by safe operating area Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS= ± 1mA, ID= 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DocID027723 Rev 1 5/16 Electrical characteristics 2.2 6/16 STB14N80K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID027723 Rev 1 STB14N80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Maximum avalanche energy vs starting TJ Figure 13: Source-drain diode forward characteristics DocID027723 Rev 1 7/16 Electrical characteristics STB14N80K5 Figure 14: Maximum avalanche energy vs starting TJ 8/16 DocID027723 Rev 1 STB14N80K5 3 Test circuits Test circuits Figure 15: Test circuit for resistive load switching times Figure 16: Test circuit for gate charge behavior Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform DocID027723 Rev 1 9/16 Package information 4 STB14N80K5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 4.1 D2PAK (TO-263) type A package information Figure 21: D²PAK (TO-263) type A package outline 0079457_A_rev22 10/16 DocID027723 Rev 1 STB14N80K5 Package information Table 10: D²PAK (TO-263) type A package mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10 E1 8.50 8.70 8.90 E2 6.85 7.05 7.25 e 10.40 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 0.4 0° DocID027723 Rev 1 8° 11/16 Package information STB14N80K5 Figure 22: D²PAK (TO-263) recommended footprint (dimensions are in mm) 12/16 DocID027723 Rev 1 STB14N80K5 4.2 Package information 2 D PAK (TO-263) packing information Figure 23: Tape outline DocID027723 Rev 1 13/16 Package information STB14N80K5 Figure 24: Reel outline Table 11: D²PAK tape and reel mechanical data Tape Reel mm mm Dim. 14/16 Dim. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 DocID027723 Rev 1 Min. Max. 330 13.2 26.4 30.4 STB14N80K5 5 Revision history Revision history Table 12: Document revision history Date Revision 18-Feb-2016 1 DocID027723 Rev 1 Changes First release. 15/16 STB14N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 16/16 DocID027723 Rev 1