STB17N80K5

STB17N80K5 N-channel 800 V, 0.29 Ω typ., 14 A MDmesh™ K5 Power MOSFET in a D²PAK package Datasheet - production data Features TAB      2 3 1 D²PAK Order code VDS RDS(on) max. ID STB17N80K5 800 V 0.34 Ω 14 A Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STB17N80K5 17N80K5 D²PAK Tape and reel May 2016 DocID027690 Rev 2 This is information on a product in full production. 1/15 www.st.com Contents STB17N80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 D²PAK (TO-263) package information .............................................. 9 4.2 D²PAK (TO-263) packing information .............................................. 12 Revision history ............................................................................ 14 DocID027690 Rev 2 STB17N80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS Gate-source voltage Value Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 14 A ID Drain current (continuous) at TC = 100 °C 9 A (1) IDM Drain current (pulsed) 56 A PTOT W Total dissipation at TC = 25 °C 170 dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 TJ Operating junction temperature range Tstg Storage temperature range V/ns - 55 to 150 °C Notes: (1) Pulse width limited by safe operating area (2) ISD ≤ 14 A, di/dt = 100 A/μs; VDS peak < V(BR)DSS,VDD= 640 V (3) VDS ≤ 640 V Table 3: Thermal data Symbol Parameter Rthj-case Rthj-pcb (1) Value Unit Thermal resistance junction-case 0.74 °C/W Thermal resistance junction-pcb 30 °C/W Notes: (1) When mounted on FR-4 board of 1inch², 2oz Cu Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 4.7 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 340 mJ DocID027690 Rev 2 3/15 Electrical characteristics 2 STB17N80K5 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions Min. VGS = 0 V, ID = 1 mA 800 Typ. Max. Unit V VGS = 0 V, VDS = 800 V 1 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 800 V (1) TC = 125 °C 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±25 V ±10 µA VGS(th) Gate threshold voltage VDD = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 7 A 0.29 0.34 Ω Min. Typ. Max. Unit - 866 - pF - 64 - pF - 0.42 - pF - 142 - pF - 51 - pF 3 Notes: (1) Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance (1) Co(tr) (2) Co(er) Test conditions Equivalent capacitance time related Equivalent capacitance energy related VDS = 0 to 640 V, VGS = 0 V Rg Intrinsic gate resistance f = 1 MHz , ID= 0 A - 5 - Ω Qg Total gate charge - 26 - nC Qgs Gate-source charge - 7.2 - nC Qgd Gate-drain charge VDD = 640 V, ID = 14 A VGS= 10 V (see Figure 15: "Test circuit for gate charge behavior") - 15.2 - nC Notes: (1) Co(tr) is a constant capacitance value that gives the same charging time as C oss while VDS is rising from 0 to 80% VDSS. (2) Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. 4/15 DocID027690 Rev 2 STB17N80K5 Electrical characteristics Table 7: Switching times Symbol td(on) tr Parameter Turn-on delay time Rise time td(off) tf Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD= 400 V, ID =7 A, RG = 4.7 Ω VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 14.8 - ns - 10.8 - ns - 84.3 - ns - 10.1 - ns Min. Typ. Max. Unit Table 8: Source-drain diode Symbol Parameter Test conditions Source-drain current - 14 A (1) Source-drain current (pulsed) - 56 A (2) Forward on voltage - 1.6 V ISD ISDM VSD ISD = 14 A, VGS = 0 V trr Reverse recovery time Qrr Reverrse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 14 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") ISD = 14 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 439 ns - 6.37 µC - 29 A - 626 ns - 8.36 µC - 26.7 A Notes: (1) (2) Pulse width limited by safe operating area Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS= ± 1 mA, ID= 0 A Min. Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID027690 Rev 2 5/15 Electrical characteristics 2.2 STB17N80K5 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area K δ=0.5 0.2 0.1 10 -1 0.05 0.02 Zth= K*Rthj-c δ= tp/Ƭ 0.01 Single pulse 10 -2 10 -5 6/15 10 -4 10 tp -3 10 -2 Ƭ 10 -1 tP (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID027690 Rev 2 STB17N80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Maximum avalanche energy vs starting TJ DocID027690 Rev 2 7/15 Test circuits 3 8/15 STB17N80K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID027690 Rev 2 STB17N80K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 4.1 D²PAK (TO-263) package information Figure 20: D²PAK (TO-263) type A package outline 0079457_A_rev22 DocID027690 Rev 2 9/15 Package information STB17N80K5 Table 10: D²PAK (TO-263) type A package mechanical data mm Dim. Min. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10 E1 8.50 8.70 8.90 E2 6.85 7.05 7.25 e 10.40 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 10/15 Typ. 0.4 0° DocID027690 Rev 2 8° STB17N80K5 Package information Figure 21: D²PAK (TO-263) recommended footprint (dimensions are in mm) DocID027690 Rev 2 11/15 Package information 4.2 STB17N80K5 D²PAK (TO-263) packing information Figure 22: Tape outline 12/15 DocID027690 Rev 2 STB17N80K5 Package information Figure 23: Reel outline Table 11: D²PAK tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 DocID027690 Rev 2 Min. Max. 330 13.2 26.4 30.4 13/15 Revision history 5 STB17N80K5 Revision history Table 12: Document revision history Date Revision 02-Apr-2015 1 First release. 2 Modified: Table 2: "Absolute maximum ratings" and Table 3: "Thermal data". Added: Section 3.1: "Electrical characteristics (curves)". Minor text changes. 20-May-2016 14/15 Changes DocID027690 Rev 2 STB17N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID027690 Rev 2 15/15