STB18N65M5

STB18N65M5, STD18N65M5 Datasheet N-channel 650 V, 0.198 Ω typ., 15 A, MDmesh™ M5 Power MOSFETs in D²PAK and DPAK packages Features TAB Order codes TAB 1 3 DPAK D(2, TAB) ID 710 V 0.220 Ω 15 A STD18N65M5 1 D2PAK RDS(on) max. STB18N65M5 2 3 2 VDS @ TJmax • Extremely low RDS(on) • • • Low gate charge and input capacitance Excellent switching performance 100% avalanche tested Applications G(1) • Switching applications Description S(3) AM01475v1_noZen These devices are N-channel Power MOSFETs based on the MDmesh™ M5 innovative vertical process technology combined with the well-known PowerMESH™ horizontal layout. The resulting products offer extremely low on-resistance, making them particularly suitable for applications requiring high power and superior efficiency. Product status link STB18N65M5 STD18N65M5 Product summary STB18N65M5 Order code STB18N65M5 Marking 18N65M5 Package D2PAK Packing Tape and reel STD18N65M5 Order code STD18N65M5 Marking 18N65M5 Package DPAK Packing Tape and reel DS9171 - Rev 2 - August 2018 For further information contact your local STMicroelectronics sales office. www.st.com STB18N65M5, STD18N65M5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 15 A Drain current (continuous) at TC = 100 °C 9.4 A IDM(1) Drain current (pulsed) 60 A PTOT Total dissipation at TC = 25 °C 110 W Peak diode recovery voltage slope 15 V/ns -55 to 150 °C VGS ID dv/dt(2) Parameter Tj Operating junction temperature range T Storage temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 15 A, di/dt ≤ 400 A/μs, VDD = 400 V, VDS(peak) < V(BR)DSS. Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-pcb (1) Thermal resistance junction-pcb Value D2PAK DPAK 1.14 30 Unit °C/W 50 °C/W 1. When mounted on an 1 inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol DS9171 - Rev 2 Parameter IAR Avalanche current, repetitive or non-repetitive (pulse width limited by Tjmax) EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Value Unit 4 A 210 mJ page 2/23 STB18N65M5, STD18N65M5 Electrical characteristics 2 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 V Min. Typ. 650 Zero gate voltage drain current 1 µA 100 µA ±100 nA 4 5 V 0.198 0.220 Ω Typ. Max. Unit - pF VGS = 0 V, VDS = 650 V, TC = 125 °C (1) IGSS Gate body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS = 10 V, ID = 7.5 A 3 Unit V VGS = 0 V, VDS = 650 V IDSS Max. 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr) (1) Equivalent capacitance time related Co(er) (2) Equivalent capacitance Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V Min. 1240 - 32 3.2 - 99 - VDS = 0 to 520 V, VGS = 0 V pF energy related Rg Gate input resistance f = 1 MHz, ID = 0 A Qg Total gate charge VDD = 520 V, ID = 7.5 A, Qgs Gate-source charge Qgd Gate-drain charge VGS = 0 to 10 V (see Figure 17. Test circuit for gate charge behavior) - - 30 - 3 - 31 - 8 14 - Ω nC 1. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 2. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. Table 6. Switching times Symbol Test conditions td(v) Voltage delay time VDD = 400 V, ID = 9.5 A, tr(v) Voltage rise time RG = 4.7 Ω, VGS = 10 V Current fall time (see Figure 18. Test circuit for inductive load switching and diode recovery times and Figure 21. Switching time waveform) tf(i) tc(off) DS9171 - Rev 2 Parameter Crossing time Min. Typ. Max. Unit - ns 36 7 - 9 11 page 3/23 STB18N65M5, STD18N65M5 Electrical characteristics Table 7. Source drain diode Symbol ISD Parameter Test conditions Source-drain current Typ. Source-drain current (pulsed) VSD(2) Forward on voltage ISD = 15 A, VGS = 0 V trr Reverse recovery time ISD = 15 A, di/dt = 100 A/µs Qrr Reverse recovery charge VDD = 100 V Reverse recovery current (see Figure 18. Test circuit for inductive load switching and diode recovery times) trr Reverse recovery time ISD = 15 A, di/dt = 100 A/µs Qrr Reverse recovery charge VDD = 100 V, Tj = 150 °C IRRM Reverse recovery current (see Figure 18. Test circuit for inductive load switching and diode recovery times) 60 - - - Max. 15 - ISDM(1) IRRM Min. 1.5 Unit A V 290 ns 3.4 μC 23.5 A 352 ns 4 μC 24 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%. DS9171 - Rev 2 page 4/23 STB18N65M5, STD18N65M5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area for D2PAK Figure 2. Thermal impedance for D2PAK AM12487v1 ) on DS ( Op Lim e ra ite tio n d by in th m is ax ar R ea is ID (A) 10 10µs 100µs 1 1ms Tj=150°C Tc=25°C 10ms S ingle puls e 0.1 0.1 10 1 100 VDS (V) Figure 3. Safe operating area for DPAK AM124871v1 ) 100 100µs 1 0.1 0.1 Tj=150°C Tc=25°C 1ms S ingle puls e 10ms 10 1 100 VDS (V) Figure 5. Output characteristics AM12472v1 ID (A) VGS = 9, 10 V 35 10-2 10-5 10-4 10-3 10-2 10-1 tp (s) Figure 6. Transfer characteristics AM12486v1 ID (A) VDS = 25 V 30 VGS = 8 V 25 25 20 20 VGS = 7 V 15 10 15 10 VGS = 6 V 5 DS9171 - Rev 2 10-1 35 30 0 GC20460 K 10µs DS 10 (o n Op Lim e ra ite tio n d by in th m is ax ar R ea is ID (A) Figure 4. Thermal impedance for DPAK 0 5 10 15 20 VDS (V) 5 0 3 4 5 6 7 8 9 VGS (V) page 5/23 STB18N65M5, STD18N65M5 Electrical characteristics (curves) Figure 7. Gate charge vs gate-source voltage AM12474v1 VGS (V) 12 VDS (V) 500 VDD=520V ID=7.5A VDS AM12475v1 R DS (on) (Ω) 0.24 VGS =10V 0.23 10 400 8 300 0.22 0.21 0.2 6 200 4 100 2 0 0 Figure 8. Static drain-source on-resistance 5 10 15 20 25 30 0 Q g (nC) Figure 9. Capacitance variations 0.17 0.16 0 2 4 6 8 10 12 14 ID(A) Figure 10. Output capacitance stored energy AM12476v1 C (pF) 0.19 0.18 AM12484v1 E os s (µJ ) 6 10000 5 Cis s 1000 3 100 Cos s 10 Crs s 1 0.1 4 1 100 10 VDS (V) Figure 11. Normalized gate threshold voltage vs temperature AM12471v1 VGS (th) (norm) 1.10 ID = 250 µA VDS = VGS 2 1 0 0 400 200 600 VDS (V) Figure 12. Normalized on-resistance vs temperature AM12483v1 R DS (on) (norm) 2.1 1.9 VGS = 10V ID= 7.5 A 1.7 1.00 1.5 1.3 0.90 1.1 0.9 0.80 0.7 0.70 -50 -25 DS9171 - Rev 2 0 25 50 75 100 TJ (°C) 0.5 -50 -25 0 25 50 75 100 TJ (°C) page 6/23 STB18N65M5, STD18N65M5 Electrical characteristics (curves) Figure 14. Normalized V(BR)DSS vs temperature Figure 13. Source-drain diode forward characteristics AM05461v1 VSD (V) AM10399v1 V(BR)DSS (norm) TJ=-50°C 1.08 1.2 ID = 1mA 1.06 1.0 1.04 0.8 1.02 TJ=25°C 1.00 0.6 TJ=150°C 0.98 0.4 0.96 0.2 0 0.94 0 2 4 6 8 0.92 -50 -25 10 ISD(A) 0 25 50 75 100 TJ(°C) Figure 15. Switching losses vs gate resistance AM12485v1 E (μJ ) VDD=400V VGS =10V ID=9.5A 160 140 Eon 120 100 80 60 Eoff 40 20 0 DS9171 - Rev 2 0 10 20 30 40 R G (Ω) page 7/23 STB18N65M5, STD18N65M5 Test circuits 3 Test circuits Figure 16. Test circuit for resistive load switching times Figure 17. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 18. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A B L A B 3.3 µF D G + VD 100 µH fast diode B Figure 19. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 20. Unclamped inductive waveform V(BR)DSS Figure 21. Switching time waveform Concept waveform for Inductive Load Turn-off Id VD 90%Vds 90%Id Tdelay -off IDM Vgs 90%Vgs on ID Vgs(I(t )) VDD VDD 10%Vds 10%Id Vds Trise AM01472v1 DS9171 - Rev 2 Tfall Tcross --over AM05540v2 page 8/23 STB18N65M5, STD18N65M5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS9171 - Rev 2 page 9/23 STB18N65M5, STD18N65M5 D²PAK (TO-263) type A package information 4.1 D²PAK (TO-263) type A package information Figure 22. D²PAK (TO-263) type A package outline 0079457_25 DS9171 - Rev 2 page 10/23 STB18N65M5, STD18N65M5 D²PAK (TO-263) type A package information Table 8. D²PAK (TO-263) type A package mechanical data Dim. mm Min. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10.00 E1 8.30 8.50 8.70 E2 6.85 7.05 7.25 e 10.40 2.54 e1 4.88 5.28 H 15.00 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 DS9171 - Rev 2 Typ. 0.40 0° 8° page 11/23 STB18N65M5, STD18N65M5 D²PAK (TO-263) type A package information Figure 23. D²PAK (TO-263) recommended footprint (dimensions are in mm) Footprint DS9171 - Rev 2 page 12/23 STB18N65M5, STD18N65M5 DPAK (TO-252) type A2 package information 4.2 DPAK (TO-252) type A2 package information Figure 24. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev25 DS9171 - Rev 2 page 13/23 STB18N65M5, STD18N65M5 DPAK (TO-252) type A2 package information Table 9. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS9171 - Rev 2 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 14/23 STB18N65M5, STD18N65M5 DPAK (TO-252) type C2 package information 4.3 DPAK (TO-252) type C2 package information Figure 25. DPAK (TO-252) type C2 package outline 0068772_C2_25 DS9171 - Rev 2 page 15/23 STB18N65M5, STD18N65M5 DPAK (TO-252) type C2 package information Table 10. DPAK (TO-252) type C2 mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.10 E 6.50 E1 5.20 e 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 6.20 5.60 6.60 6.70 5.50 0.90 1.25 0.51 BSC 0.60 L6 DS9171 - Rev 2 6.10 5.46 2.90 REF L3 L4 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° page 16/23 STB18N65M5, STD18N65M5 DPAK (TO-252) type C2 package information Figure 26. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_25 DS9171 - Rev 2 page 17/23 STB18N65M5, STD18N65M5 D²PAK and DPAK packing information 4.4 D²PAK and DPAK packing information Figure 27. Tape outline DS9171 - Rev 2 page 18/23 STB18N65M5, STD18N65M5 D²PAK and DPAK packing information Figure 28. Reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 11. D²PAK tape and reel mechanical data Tape Dim. DS9171 - Rev 2 Reel mm mm Dim. Min. Max. Min. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T Max. 330 13.2 26.4 30.4 P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 page 19/23 STB18N65M5, STD18N65M5 D²PAK and DPAK packing information Table 12. DPAK tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS9171 - Rev 2 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 20/23 STB18N65M5, STD18N65M5 Revision history Table 13. Document revision history Date Version 18-Jul-2012 1 Changes First release. Removed maturity status indication from cover page. The document status is production data. 09-Aug-2018 2 Updated Section 4 Package information. Minor text changes DS9171 - Rev 2 page 21/23 STB18N65M5, STD18N65M5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 D²PAK (TO-263) type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 DPAK (TO-252) type C2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 D²PAK and DPAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 DS9171 - Rev 2 page 22/23 STB18N65M5, STD18N65M5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS9171 - Rev 2 page 23/23