STD5N60DM2

STD5N60DM2 Datasheet N-channel 600 V, 1.38 Ω typ., 3.5 A MDmesh™ DM2 Power MOSFET in a DPAK package Features TAB 2 3 1 • • • • • • DPAK D(2, TAB) Order code VDS RDS(on) max. ID PTOT STD5N60DM2 600 V 1.55 Ω 3.5 A 45 W Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected G(1) Applications • S(3) Switching applications AM01475V1 Description This high-voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high-efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Product status link STD5N60DM2 Product summary Order code STD5N60DM2 Marking 5N60DM2 Package DPAK Packing Tape and reel DS11742 - Rev 3 - June 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD5N60DM2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit Gate-source voltage ±30 V Drain current (continuous) at Tcase = 25 °C 3.5 Drain current (continuous) at Tcase = 100 °C 2 IDM (1) Drain current (pulsed) 14 A PTOT Total dissipation at Tcase = 25 °C 45 W dv/dt(2) Peak diode recovery voltage slope 40 dv/dt(3) MOSFET dv/dt ruggedness 40 Tstg Storage temperature range VGS ID Tj Operating junction temperature range A V/ns -55 to 150 °C 1. Pulse width is limited by safe operating area. 2. ISD ≤ 3.5 A, di/dt=400 A/μs; VDS peak < V(BR)DSS, VDD = 480 V. 3. VDS ≤ 480 V. Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Thermal resistance junction-case 2.78 Thermal resistance junction-pcb 50 Unit °C/W 1. When mounted on a 1-inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol IAR (1) EAS (2) Parameter Avalanche current, repetitive or not repetitive Single pulse avalanche energy Value Unit 1 A 132 mJ 1. Pulse width limited by Tjmax. 2. Starting Tj = 25 °C, ID = IAR, VDD = 50 V. DS11742 - Rev 3 page 2/18 STD5N60DM2 Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified). Table 4. Static Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 VGS = 0 V, VDS = 600 V, Tcase = 125 °C (1) 100 ±5 µA 4 5 V 1.38 1.55 Ω Unit IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 1.75 A 3 µA 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Min. Typ. Max. - 214 - - 12 - Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance - 3.5 - Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 21 - pF - 6.5 - Ω - 5.3 - - 1.4 - - 2.7 - Coss eq. (1) RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDS = 100 V, f = 1 MHz, VGS = 0 V f = 1 MHz, ID = 0 A VDD = 480 V, ID = 3.5 A, VGS = 0 to 10 V (see Figure 14. Test circuit for gate charge behavior) pF nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS11742 - Rev 3 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 300 V, ID = 1.75 A RG = 4.7 Ω, VGS = 10 V (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) Min. Typ. Max. - 7.2 - - 4.1 - - 17 - - 19.8 - Unit ns page 3/18 STD5N60DM2 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM (1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 3.5 A Source-drain current (pulsed) - 14 A 1.6 V 70 ns Forward on voltage VGS = 0 V, ISD = 3.5 A - trr Reverse recovery time - 58 Qrr Reverse recovery charge - 109 nC IRRM Reverse recovery current ISD = 3.5 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 4 A ISD = 3.5 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 109 ns - 309 nC - 5 A VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS11742 - Rev 3 page 4/18 STD5N60DM2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) GIPG270620160921SOA Operation in this area is limited by R DS(on) 10 1 tp =10 µs tp =100 µs 10 0 T j ≤150 °C T c = 25°C single pulse 10 -1 10 -1 tp =1 ms tp =10 ms 10 0 10 1 10 2 10 3 VDS (V) Figure 3. Output characteristics ID (A) 6 Figure 4. Transfer characteristics GIPG270620160824OCH VGS =8, 9, 10 V VDS = 20 V 5 4 4 3 3 VGS =6 V 2 1 DS11742 - Rev 3 GIPG270620160918TCH 6 VGS =7 V 5 0 0 ID (A) 2 1 VGS =5 V 4 8 12 16 VDS (V) 0 0 2 4 6 8 VGS (V) page 5/18 STD5N60DM2 Electrical characteristics (curves) Figure 5. Gate charge vs gate-source voltage VGS (V) 20 GADG010620181431QVG VDS (V) VDD = 480 V VDS 500 ID = 3.5 A 16 400 8 1.5 VGS =10 V 1.46 1.38 200 4 100 0 0 GIPG270620160822RID 300 Qgd Qgs RDS(on) (Ω) 1.42 Qg 12 Figure 6. Static drain-source on-resistance 2 4 6 8 0 Qg (nC) Figure 7. Capacitance variations C (pF) 1.34 1.3 1.26 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ID (A) Figure 8. Output capacitance stored energy EOSS (µJ) GADG010620181432CVR GIPG270620160920EOS 1.6 10 3 CISS 1.2 10 2 0.8 10 1 10 0 10 -1 f = 1 MHz COSS CRSS 10 0 10 1 10 2 VDS (V) Figure 9. Normalized gate threshold voltage vs temperature VGS(th) (norm.) GIPG270620160821VTH 100 200 300 400 500 600 VDS (V) Figure 10. Normalized on-resistance vs temperature RDS(on) (norm.) GIPG270620160822RON VGS = 10 V ID = 250 µA 1.8 1.0 1.4 0.9 1.0 0.8 0.6 0.7 DS11742 - Rev 3 0 0 2.2 1.1 0.6 -75 0.4 -25 25 75 125 Tj (°C) 0.2 -75 -25 25 75 125 Tj (°C) page 6/18 STD5N60DM2 Electrical characteristics (curves) Figure 11. Source-drain diode forward characteristics VSD (V) GIPG270620160823SDF Tj = -50 °C 1.0 0.9 GIPG270620160822BDV ID = 1 mA 1.04 Tj = 25 °C 1.00 0.7 0.96 Tj = 150 °C 0.6 DS11742 - Rev 3 V(BR)DSS (norm.) 1.08 0.8 0.5 0.5 Figure 12. Normalized V(BR)DSS vs temperature 0.92 1.0 1.5 2.0 2.5 3.0 3.5 ISD (A) 0.88 -75 -25 25 75 125 Tj (°C) page 7/18 STD5N60DM2 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS ton VD td(on) 90% IDM tf 90% 10% 10% 0 ID VDD toff td(off) tr VDD VGS 0 VDS 90% 10% AM01472v1 AM01473v1 DS11742 - Rev 3 page 8/18 STD5N60DM2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11742 - Rev 3 page 9/18 STD5N60DM2 DPAK (TO-252) type A package information 4.1 DPAK (TO-252) type A package information Figure 19. DPAK (TO-252) type A package outline 0068772_A_25 DS11742 - Rev 3 page 10/18 STD5N60DM2 DPAK (TO-252) type A package information Table 8. DPAK (TO-252) type A mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS11742 - Rev 3 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 11/18 STD5N60DM2 DPAK (TO-252) type E package information 4.2 DPAK (TO-252) type E package information Figure 20. DPAK (TO-252) type E package outline 0068772_type-E_rev.25 DS11742 - Rev 3 page 12/18 STD5N60DM2 DPAK (TO-252) type E package information Table 9. DPAK (TO-252) type E mechanical data Dim. A mm Min. Typ. 2.18 Max. 2.39 A2 0.13 b 0.65 0.884 b4 4.95 5.46 c 0.46 0.61 c2 0.46 0.60 D 5.97 6.22 D1 5.21 E 6.35 E1 4.32 6.73 e 2.286 e1 4.572 H 9.94 10.34 L 1.50 1.78 L1 L2 L4 2.74 0.89 1.27 1.02 Figure 21. DPAK (TO-252) type E recommended footprint (dimensions are in mm) FP_0068772_25 DS11742 - Rev 3 page 13/18 STD5N60DM2 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 22. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS11742 - Rev 3 page 14/18 STD5N60DM2 DPAK (TO-252) packing information Figure 23. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS11742 - Rev 3 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 15/18 STD5N60DM2 Revision history Table 11. Document revision history Date 05-Jul-2016 Revision Changes 1 First release. Updated Section 1: "Electrical ratings". 17-May-2017 2 Added Section 4.2: "DPAK (TO-252) type C package information". Minor text changes. 01-Jun-2018 3 Updated Table 3. Avalanche characteristics, Table 5. Dynamic, Figure 5. Gate charge vs gatesource voltage and Figure 7. Capacitance variations. Updated Section 4 Package information. DS11742 - Rev 3 page 16/18 STD5N60DM2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 DPAK (TO-252) type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 DPAK (TO-252) type E package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DS11742 - Rev 3 page 17/18 STD5N60DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11742 - Rev 3 page 18/18